arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/module.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/system.h>
  26 #include <asm/watch.h>
  27 #include <asm/spram.h>
  28 /*
  29  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  30  * the implementation of the "wait" feature differs between CPU families. This
  31  * points to the function that implements CPU specific wait.
  32  * The wait instruction stops the pipeline and reduces the power consumption of
  33  * the CPU very much.
  34  */
  35 void (*cpu_wait)(void);
  36 EXPORT_SYMBOL(cpu_wait);
  37
  38 static void r3081_wait(void)
  39 {
  40         unsigned long cfg = read_c0_conf();
  41         write_c0_conf(cfg | R30XX_CONF_HALT);
  42 }
  43
  44 static void r39xx_wait(void)
  45 {
  46         local_irq_disable();
  47         if (!need_resched())
  48                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  49         local_irq_enable();
  50 }
  51
  52 extern void r4k_wait(void);
  53
  54 /*
  55  * This variant is preferable as it allows testing need_resched and going to
  56  * sleep depending on the outcome atomically.  Unfortunately the "It is
  57  * implementation-dependent whether the pipeline restarts when a non-enabled
  58  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  59  * using this version a gamble.
  60  */
  61 void r4k_wait_irqoff(void)
  62 {
  63         local_irq_disable();
  64         if (!need_resched())
  65                 __asm__("       .set    push            \n"
  66                         "       .set    mips3           \n"
  67                         "       wait                    \n"
  68                         "       .set    pop             \n");
  69         local_irq_enable();
  70         __asm__("       .globl __pastwait       \n"
  71                 "__pastwait:                    \n");
  72         return;
  73 }
  74
  75 /*
  76  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  77  * have any pending stores when the WAIT instruction is executed.
  78  */
  79 static void rm7k_wait_irqoff(void)
  80 {
  81         local_irq_disable();
  82         if (!need_resched())
  83                 __asm__(
  84                 "       .set    push                                    \n"
  85                 "       .set    mips3                                   \n"
  86                 "       .set    noat                                    \n"
  87                 "       mfc0    $1, $12                                 \n"
  88                 "       sync                                            \n"
  89                 "       mtc0    $1, $12         # stalls until W stage  \n"
  90                 "       wait                                            \n"
  91                 "       mtc0    $1, $12         # stalls until W stage  \n"
  92                 "       .set    pop                                     \n");
  93         local_irq_enable();
  94 }
  95
  96 /*
  97  * The Au1xxx wait is available only if using 32khz counter or
  98  * external timer source, but specifically not CP0 Counter.
  99  * alchemy/common/time.c may override cpu_wait!
 100  */
 101 static void au1k_wait(void)
 102 {
 103         __asm__("       .set    mips3                   \n"
 104                 "       cache   0x14, 0(%0)             \n"
 105                 "       cache   0x14, 32(%0)            \n"
 106                 "       sync                            \n"
 107                 "       nop                             \n"
 108                 "       wait                            \n"
 109                 "       nop                             \n"
 110                 "       nop                             \n"
 111                 "       nop                             \n"
 112                 "       nop                             \n"
 113                 "       .set    mips0                   \n"
 114                 : : "r" (au1k_wait));
 115 }
 116
 117 static int __initdata nowait;
 118
 119 static int __init wait_disable(char *s)
 120 {
 121         nowait = 1;
 122
 123         return 1;
 124 }
 125
 126 __setup("nowait", wait_disable);
 127
 128 void __init check_wait(void)
 129 {
 130         struct cpuinfo_mips *c = &current_cpu_data;
 131
 132         if (nowait) {
 133                 printk("Wait instruction disabled.\n");
 134                 return;
 135         }
 136
 137         switch (c->cputype) {
 138         case CPU_R3081:
 139         case CPU_R3081E:
 140                 cpu_wait = r3081_wait;
 141                 break;
 142         case CPU_TX3927:
 143                 cpu_wait = r39xx_wait;
 144                 break;
 145         case CPU_R4200:
 146 /*      case CPU_R4300: */
 147         case CPU_R4600:
 148         case CPU_R4640:
 149         case CPU_R4650:
 150         case CPU_R4700:
 151         case CPU_R5000:
 152         case CPU_R5500:
 153         case CPU_NEVADA:
 154         case CPU_4KC:
 155         case CPU_4KEC:
 156         case CPU_4KSC:
 157         case CPU_5KC:
 158         case CPU_25KF:
 159         case CPU_PR4450:
 160         case CPU_BCM3302:
 161         case CPU_BCM6338:
 162         case CPU_BCM6348:
 163         case CPU_BCM6358:
 164         case CPU_CAVIUM_OCTEON:
 165         case CPU_CAVIUM_OCTEON_PLUS:
 166                 cpu_wait = r4k_wait;
 167                 break;
 168
 169         case CPU_RM7000:
 170                 cpu_wait = rm7k_wait_irqoff;
 171                 break;
 172
 173         case CPU_24K:
 174         case CPU_34K:
 175         case CPU_1004K:
 176                 cpu_wait = r4k_wait;
 177                 if (read_c0_config7() & MIPS_CONF7_WII)
 178                         cpu_wait = r4k_wait_irqoff;
 179                 break;
 180
 181         case CPU_74K:
 182                 cpu_wait = r4k_wait;
 183                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 184                         cpu_wait = r4k_wait_irqoff;
 185                 break;
 186
 187         case CPU_TX49XX:
 188                 cpu_wait = r4k_wait_irqoff;
 189                 break;
 190         case CPU_ALCHEMY:
 191                 cpu_wait = au1k_wait;
 192                 break;
 193         case CPU_20KC:
 194                 /*
 195                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 196                  * WAIT on Rev2.0 and Rev3.0 has E16.
 197                  * Rev3.1 WAIT is nop, why bother
 198                  */
 199                 if ((c->processor_id & 0xff) <= 0x64)
 200                         break;
 201
 202                 /*
 203                  * Another rev is incremeting c0_count at a reduced clock
 204                  * rate while in WAIT mode.  So we basically have the choice
 205                  * between using the cp0 timer as clocksource or avoiding
 206                  * the WAIT instruction.  Until more details are known,
 207                  * disable the use of WAIT for 20Kc entirely.
 208                    cpu_wait = r4k_wait;
 209                  */
 210                 break;
 211         case CPU_RM9000:
 212                 if ((c->processor_id & 0x00ff) >= 0x40)
 213                         cpu_wait = r4k_wait;
 214                 break;
 215         default:
 216                 break;
 217         }
 218 }
 219
 220 static inline void check_errata(void)
 221 {
 222         struct cpuinfo_mips *c = &current_cpu_data;
 223
 224         switch (c->cputype) {
 225         case CPU_34K:
 226                 /*
 227                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 228                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 229                  * making use of VPE1 will be responsable for that VPE.
 230                  */
 231                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 232                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 233                 break;
 234         default:
 235                 break;
 236         }
 237 }
 238
 239 void __init check_bugs32(void)
 240 {
 241         check_errata();
 242 }
 243
 244 /*
 245  * Probe whether cpu has config register by trying to play with
 246  * alternate cache bit and see whether it matters.
 247  * It's used by cpu_probe to distinguish between R3000A and R3081.
 248  */
 249 static inline int cpu_has_confreg(void)
 250 {
 251 #ifdef CONFIG_CPU_R3000
 252         extern unsigned long r3k_cache_size(unsigned long);
 253         unsigned long size1, size2;
 254         unsigned long cfg = read_c0_conf();
 255
 256         size1 = r3k_cache_size(ST0_ISC);
 257         write_c0_conf(cfg ^ R30XX_CONF_AC);
 258         size2 = r3k_cache_size(ST0_ISC);
 259         write_c0_conf(cfg);
 260         return size1 != size2;
 261 #else
 262         return 0;
 263 #endif
 264 }
 265
 266 /*
 267  * Get the FPU Implementation/Revision.
 268  */
 269 static inline unsigned long cpu_get_fpu_id(void)
 270 {
 271         unsigned long tmp, fpu_id;
 272
 273         tmp = read_c0_status();
 274         __enable_fpu();
 275         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 276         write_c0_status(tmp);
 277         return fpu_id;
 278 }
 279
 280 /*
 281  * Check the CPU has an FPU the official way.
 282  */
 283 static inline int __cpu_has_fpu(void)
 284 {
 285         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 286 }
 287
 288 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 289 {
 290 #ifdef __NEED_VMBITS_PROBE
 291         write_c0_entryhi(0x3fffffffffffe000ULL);
 292         back_to_back_c0_hazard();
 293         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 294 #endif
 295 }
 296
 297 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 298                 | MIPS_CPU_COUNTER)
 299
 300 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 301 {
 302         switch (c->processor_id & 0xff00) {
 303         case PRID_IMP_R2000:
 304                 c->cputype = CPU_R2000;
 305                 __cpu_name[cpu] = "R2000";
 306                 c->isa_level = MIPS_CPU_ISA_I;
 307                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 308                              MIPS_CPU_NOFPUEX;
 309                 if (__cpu_has_fpu())
 310                         c->options |= MIPS_CPU_FPU;
 311                 c->tlbsize = 64;
 312                 break;
 313         case PRID_IMP_R3000:
 314                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 315                         if (cpu_has_confreg()) {
 316                                 c->cputype = CPU_R3081E;
 317                                 __cpu_name[cpu] = "R3081";
 318                         } else {
 319                                 c->cputype = CPU_R3000A;
 320                                 __cpu_name[cpu] = "R3000A";
 321                         }
 322                         break;
 323                 } else {
 324                         c->cputype = CPU_R3000;
 325                         __cpu_name[cpu] = "R3000";
 326                 }
 327                 c->isa_level = MIPS_CPU_ISA_I;
 328                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 329                              MIPS_CPU_NOFPUEX;
 330                 if (__cpu_has_fpu())
 331                         c->options |= MIPS_CPU_FPU;
 332                 c->tlbsize = 64;
 333                 break;
 334         case PRID_IMP_R4000:
 335                 if (read_c0_config() & CONF_SC) {
 336                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 337                                 c->cputype = CPU_R4400PC;
 338                                 __cpu_name[cpu] = "R4400PC";
 339                         } else {
 340                                 c->cputype = CPU_R4000PC;
 341                                 __cpu_name[cpu] = "R4000PC";
 342                         }
 343                 } else {
 344                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 345                                 c->cputype = CPU_R4400SC;
 346                                 __cpu_name[cpu] = "R4400SC";
 347                         } else {
 348                                 c->cputype = CPU_R4000SC;
 349                                 __cpu_name[cpu] = "R4000SC";
 350                         }
 351                 }
 352
 353                 c->isa_level = MIPS_CPU_ISA_III;
 354                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 355                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 356                              MIPS_CPU_LLSC;
 357                 c->tlbsize = 48;
 358                 break;
 359         case PRID_IMP_VR41XX:
 360                 switch (c->processor_id & 0xf0) {
 361                 case PRID_REV_VR4111:
 362                         c->cputype = CPU_VR4111;
 363                         __cpu_name[cpu] = "NEC VR4111";
 364                         break;
 365                 case PRID_REV_VR4121:
 366                         c->cputype = CPU_VR4121;
 367                         __cpu_name[cpu] = "NEC VR4121";
 368                         break;
 369                 case PRID_REV_VR4122:
 370                         if ((c->processor_id & 0xf) < 0x3) {
 371                                 c->cputype = CPU_VR4122;
 372                                 __cpu_name[cpu] = "NEC VR4122";
 373                         } else {
 374                                 c->cputype = CPU_VR4181A;
 375                                 __cpu_name[cpu] = "NEC VR4181A";
 376                         }
 377                         break;
 378                 case PRID_REV_VR4130:
 379                         if ((c->processor_id & 0xf) < 0x4) {
 380                                 c->cputype = CPU_VR4131;
 381                                 __cpu_name[cpu] = "NEC VR4131";
 382                         } else {
 383                                 c->cputype = CPU_VR4133;
 384                                 __cpu_name[cpu] = "NEC VR4133";
 385                         }
 386                         break;
 387                 default:
 388                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 389                         c->cputype = CPU_VR41XX;
 390                         __cpu_name[cpu] = "NEC Vr41xx";
 391                         break;
 392                 }
 393                 c->isa_level = MIPS_CPU_ISA_III;
 394                 c->options = R4K_OPTS;
 395                 c->tlbsize = 32;
 396                 break;
 397         case PRID_IMP_R4300:
 398                 c->cputype = CPU_R4300;
 399                 __cpu_name[cpu] = "R4300";
 400                 c->isa_level = MIPS_CPU_ISA_III;
 401                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 402                              MIPS_CPU_LLSC;
 403                 c->tlbsize = 32;
 404                 break;
 405         case PRID_IMP_R4600:
 406                 c->cputype = CPU_R4600;
 407                 __cpu_name[cpu] = "R4600";
 408                 c->isa_level = MIPS_CPU_ISA_III;
 409                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 410                              MIPS_CPU_LLSC;
 411                 c->tlbsize = 48;
 412                 break;
 413         #if 0
 414         case PRID_IMP_R4650:
 415                 /*
 416                  * This processor doesn't have an MMU, so it's not
 417                  * "real easy" to run Linux on it. It is left purely
 418                  * for documentation.  Commented out because it shares
 419                  * it's c0_prid id number with the TX3900.
 420                  */
 421                 c->cputype = CPU_R4650;
 422                 __cpu_name[cpu] = "R4650";
 423                 c->isa_level = MIPS_CPU_ISA_III;
 424                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 425                 c->tlbsize = 48;
 426                 break;
 427         #endif
 428         case PRID_IMP_TX39:
 429                 c->isa_level = MIPS_CPU_ISA_I;
 430                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 431
 432                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 433                         c->cputype = CPU_TX3927;
 434                         __cpu_name[cpu] = "TX3927";
 435                         c->tlbsize = 64;
 436                 } else {
 437                         switch (c->processor_id & 0xff) {
 438                         case PRID_REV_TX3912:
 439                                 c->cputype = CPU_TX3912;
 440                                 __cpu_name[cpu] = "TX3912";
 441                                 c->tlbsize = 32;
 442                                 break;
 443                         case PRID_REV_TX3922:
 444                                 c->cputype = CPU_TX3922;
 445                                 __cpu_name[cpu] = "TX3922";
 446                                 c->tlbsize = 64;
 447                                 break;
 448                         }
 449                 }
 450                 break;
 451         case PRID_IMP_R4700:
 452                 c->cputype = CPU_R4700;
 453                 __cpu_name[cpu] = "R4700";
 454                 c->isa_level = MIPS_CPU_ISA_III;
 455                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 456                              MIPS_CPU_LLSC;
 457                 c->tlbsize = 48;
 458                 break;
 459         case PRID_IMP_TX49:
 460                 c->cputype = CPU_TX49XX;
 461                 __cpu_name[cpu] = "R49XX";
 462                 c->isa_level = MIPS_CPU_ISA_III;
 463                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 464                 if (!(c->processor_id & 0x08))
 465                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 466                 c->tlbsize = 48;
 467                 break;
 468         case PRID_IMP_R5000:
 469                 c->cputype = CPU_R5000;
 470                 __cpu_name[cpu] = "R5000";
 471                 c->isa_level = MIPS_CPU_ISA_IV;
 472                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 473                              MIPS_CPU_LLSC;
 474                 c->tlbsize = 48;
 475                 break;
 476         case PRID_IMP_R5432:
 477                 c->cputype = CPU_R5432;
 478                 __cpu_name[cpu] = "R5432";
 479                 c->isa_level = MIPS_CPU_ISA_IV;
 480                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 481                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 482                 c->tlbsize = 48;
 483                 break;
 484         case PRID_IMP_R5500:
 485                 c->cputype = CPU_R5500;
 486                 __cpu_name[cpu] = "R5500";
 487                 c->isa_level = MIPS_CPU_ISA_IV;
 488                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 489                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 490                 c->tlbsize = 48;
 491                 break;
 492         case PRID_IMP_NEVADA:
 493                 c->cputype = CPU_NEVADA;
 494                 __cpu_name[cpu] = "Nevada";
 495                 c->isa_level = MIPS_CPU_ISA_IV;
 496                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 497                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 498                 c->tlbsize = 48;
 499                 break;
 500         case PRID_IMP_R6000:
 501                 c->cputype = CPU_R6000;
 502                 __cpu_name[cpu] = "R6000";
 503                 c->isa_level = MIPS_CPU_ISA_II;
 504                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 505                              MIPS_CPU_LLSC;
 506                 c->tlbsize = 32;
 507                 break;
 508         case PRID_IMP_R6000A:
 509                 c->cputype = CPU_R6000A;
 510                 __cpu_name[cpu] = "R6000A";
 511                 c->isa_level = MIPS_CPU_ISA_II;
 512                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 513                              MIPS_CPU_LLSC;
 514                 c->tlbsize = 32;
 515                 break;
 516         case PRID_IMP_RM7000:
 517                 c->cputype = CPU_RM7000;
 518                 __cpu_name[cpu] = "RM7000";
 519                 c->isa_level = MIPS_CPU_ISA_IV;
 520                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 521                              MIPS_CPU_LLSC;
 522                 /*
 523                  * Undocumented RM7000:  Bit 29 in the info register of
 524                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 525                  * entries.
 526                  *
 527                  * 29      1 =>    64 entry JTLB
 528                  *         0 =>    48 entry JTLB
 529                  */
 530                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 531                 break;
 532         case PRID_IMP_RM9000:
 533                 c->cputype = CPU_RM9000;
 534                 __cpu_name[cpu] = "RM9000";
 535                 c->isa_level = MIPS_CPU_ISA_IV;
 536                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 537                              MIPS_CPU_LLSC;
 538                 /*
 539                  * Bit 29 in the info register of the RM9000
 540                  * indicates if the TLB has 48 or 64 entries.
 541                  *
 542                  * 29      1 =>    64 entry JTLB
 543                  *         0 =>    48 entry JTLB
 544                  */
 545                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 546                 break;
 547         case PRID_IMP_R8000:
 548                 c->cputype = CPU_R8000;
 549                 __cpu_name[cpu] = "RM8000";
 550                 c->isa_level = MIPS_CPU_ISA_IV;
 551                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 552                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 553                              MIPS_CPU_LLSC;
 554                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 555                 break;
 556         case PRID_IMP_R10000:
 557                 c->cputype = CPU_R10000;
 558                 __cpu_name[cpu] = "R10000";
 559                 c->isa_level = MIPS_CPU_ISA_IV;
 560                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 561                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 562                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 563                              MIPS_CPU_LLSC;
 564                 c->tlbsize = 64;
 565                 break;
 566         case PRID_IMP_R12000:
 567                 c->cputype = CPU_R12000;
 568                 __cpu_name[cpu] = "R12000";
 569                 c->isa_level = MIPS_CPU_ISA_IV;
 570                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 571                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 572                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 573                              MIPS_CPU_LLSC;
 574                 c->tlbsize = 64;
 575                 break;
 576         case PRID_IMP_R14000:
 577                 c->cputype = CPU_R14000;
 578                 __cpu_name[cpu] = "R14000";
 579                 c->isa_level = MIPS_CPU_ISA_IV;
 580                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 581                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 582                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 583                              MIPS_CPU_LLSC;
 584                 c->tlbsize = 64;
 585                 break;
 586         case PRID_IMP_LOONGSON2:
 587                 c->cputype = CPU_LOONGSON2;
 588                 __cpu_name[cpu] = "ICT Loongson-2";
 589                 c->isa_level = MIPS_CPU_ISA_III;
 590                 c->options = R4K_OPTS |
 591                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 592                              MIPS_CPU_32FPR;
 593                 c->tlbsize = 64;
 594                 break;
 595         }
 596 }
 597
 598 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 599         "Unsupported ISA type, c0.config0: %d.";
 600
 601 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 602 {
 603         unsigned int config0;
 604         int isa;
 605
 606         config0 = read_c0_config();
 607
 608         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 609                 c->options |= MIPS_CPU_TLB;
 610         isa = (config0 & MIPS_CONF_AT) >> 13;
 611         switch (isa) {
 612         case 0:
 613                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 614                 case 0:
 615                         c->isa_level = MIPS_CPU_ISA_M32R1;
 616                         break;
 617                 case 1:
 618                         c->isa_level = MIPS_CPU_ISA_M32R2;
 619                         break;
 620                 default:
 621                         goto unknown;
 622                 }
 623                 break;
 624         case 2:
 625                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 626                 case 0:
 627                         c->isa_level = MIPS_CPU_ISA_M64R1;
 628                         break;
 629                 case 1:
 630                         c->isa_level = MIPS_CPU_ISA_M64R2;
 631                         break;
 632                 default:
 633                         goto unknown;
 634                 }
 635                 break;
 636         default:
 637                 goto unknown;
 638         }
 639
 640         return config0 & MIPS_CONF_M;
 641
 642 unknown:
 643         panic(unknown_isa, config0);
 644 }
 645
 646 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 647 {
 648         unsigned int config1;
 649
 650         config1 = read_c0_config1();
 651
 652         if (config1 & MIPS_CONF1_MD)
 653                 c->ases |= MIPS_ASE_MDMX;
 654         if (config1 & MIPS_CONF1_WR)
 655                 c->options |= MIPS_CPU_WATCH;
 656         if (config1 & MIPS_CONF1_CA)
 657                 c->ases |= MIPS_ASE_MIPS16;
 658         if (config1 & MIPS_CONF1_EP)
 659                 c->options |= MIPS_CPU_EJTAG;
 660         if (config1 & MIPS_CONF1_FP) {
 661                 c->options |= MIPS_CPU_FPU;
 662                 c->options |= MIPS_CPU_32FPR;
 663         }
 664         if (cpu_has_tlb)
 665                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 666
 667         return config1 & MIPS_CONF_M;
 668 }
 669
 670 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 671 {
 672         unsigned int config2;
 673
 674         config2 = read_c0_config2();
 675
 676         if (config2 & MIPS_CONF2_SL)
 677                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 678
 679         return config2 & MIPS_CONF_M;
 680 }
 681
 682 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 683 {
 684         unsigned int config3;
 685
 686         config3 = read_c0_config3();
 687
 688         if (config3 & MIPS_CONF3_SM)
 689                 c->ases |= MIPS_ASE_SMARTMIPS;
 690         if (config3 & MIPS_CONF3_DSP)
 691                 c->ases |= MIPS_ASE_DSP;
 692         if (config3 & MIPS_CONF3_VINT)
 693                 c->options |= MIPS_CPU_VINT;
 694         if (config3 & MIPS_CONF3_VEIC)
 695                 c->options |= MIPS_CPU_VEIC;
 696         if (config3 & MIPS_CONF3_MT)
 697                 c->ases |= MIPS_ASE_MIPSMT;
 698         if (config3 & MIPS_CONF3_ULRI)
 699                 c->options |= MIPS_CPU_ULRI;
 700
 701         return config3 & MIPS_CONF_M;
 702 }
 703
 704 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 705 {
 706         unsigned int config4;
 707
 708         config4 = read_c0_config4();
 709
 710         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 711             && cpu_has_tlb)
 712                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 713
 714         return config4 & MIPS_CONF_M;
 715 }
 716
 717 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 718 {
 719         int ok;
 720
 721         /* MIPS32 or MIPS64 compliant CPU.  */
 722         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 723                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 724
 725         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 726
 727         ok = decode_config0(c);                 /* Read Config registers.  */
 728         BUG_ON(!ok);                            /* Arch spec violation!  */
 729         if (ok)
 730                 ok = decode_config1(c);
 731         if (ok)
 732                 ok = decode_config2(c);
 733         if (ok)
 734                 ok = decode_config3(c);
 735         if (ok)
 736                 ok = decode_config4(c);
 737
 738         mips_probe_watch_registers(c);
 739 }
 740
 741 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 742 {
 743         decode_configs(c);
 744         switch (c->processor_id & 0xff00) {
 745         case PRID_IMP_4KC:
 746                 c->cputype = CPU_4KC;
 747                 __cpu_name[cpu] = "MIPS 4Kc";
 748                 break;
 749         case PRID_IMP_4KEC:
 750         case PRID_IMP_4KECR2:
 751                 c->cputype = CPU_4KEC;
 752                 __cpu_name[cpu] = "MIPS 4KEc";
 753                 break;
 754         case PRID_IMP_4KSC:
 755         case PRID_IMP_4KSD:
 756                 c->cputype = CPU_4KSC;
 757                 __cpu_name[cpu] = "MIPS 4KSc";
 758                 break;
 759         case PRID_IMP_5KC:
 760                 c->cputype = CPU_5KC;
 761                 __cpu_name[cpu] = "MIPS 5Kc";
 762                 break;
 763         case PRID_IMP_20KC:
 764                 c->cputype = CPU_20KC;
 765                 __cpu_name[cpu] = "MIPS 20Kc";
 766                 break;
 767         case PRID_IMP_24K:
 768         case PRID_IMP_24KE:
 769                 c->cputype = CPU_24K;
 770                 __cpu_name[cpu] = "MIPS 24Kc";
 771                 break;
 772         case PRID_IMP_25KF:
 773                 c->cputype = CPU_25KF;
 774                 __cpu_name[cpu] = "MIPS 25Kc";
 775                 break;
 776         case PRID_IMP_34K:
 777                 c->cputype = CPU_34K;
 778                 __cpu_name[cpu] = "MIPS 34Kc";
 779                 break;
 780         case PRID_IMP_74K:
 781                 c->cputype = CPU_74K;
 782                 __cpu_name[cpu] = "MIPS 74Kc";
 783                 break;
 784         case PRID_IMP_1004K:
 785                 c->cputype = CPU_1004K;
 786                 __cpu_name[cpu] = "MIPS 1004Kc";
 787                 break;
 788         }
 789
 790         spram_config();
 791 }
 792
 793 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 794 {
 795         decode_configs(c);
 796         switch (c->processor_id & 0xff00) {
 797         case PRID_IMP_AU1_REV1:
 798         case PRID_IMP_AU1_REV2:
 799                 c->cputype = CPU_ALCHEMY;
 800                 switch ((c->processor_id >> 24) & 0xff) {
 801                 case 0:
 802                         __cpu_name[cpu] = "Au1000";
 803                         break;
 804                 case 1:
 805                         __cpu_name[cpu] = "Au1500";
 806                         break;
 807                 case 2:
 808                         __cpu_name[cpu] = "Au1100";
 809                         break;
 810                 case 3:
 811                         __cpu_name[cpu] = "Au1550";
 812                         break;
 813                 case 4:
 814                         __cpu_name[cpu] = "Au1200";
 815                         if ((c->processor_id & 0xff) == 2)
 816                                 __cpu_name[cpu] = "Au1250";
 817                         break;
 818                 case 5:
 819                         __cpu_name[cpu] = "Au1210";
 820                         break;
 821                 default:
 822                         __cpu_name[cpu] = "Au1xxx";
 823                         break;
 824                 }
 825                 break;
 826         }
 827 }
 828
 829 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 830 {
 831         decode_configs(c);
 832
 833         switch (c->processor_id & 0xff00) {
 834         case PRID_IMP_SB1:
 835                 c->cputype = CPU_SB1;
 836                 __cpu_name[cpu] = "SiByte SB1";
 837                 /* FPU in pass1 is known to have issues. */
 838                 if ((c->processor_id & 0xff) < 0x02)
 839                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 840                 break;
 841         case PRID_IMP_SB1A:
 842                 c->cputype = CPU_SB1A;
 843                 __cpu_name[cpu] = "SiByte SB1A";
 844                 break;
 845         }
 846 }
 847
 848 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 849 {
 850         decode_configs(c);
 851         switch (c->processor_id & 0xff00) {
 852         case PRID_IMP_SR71000:
 853                 c->cputype = CPU_SR71000;
 854                 __cpu_name[cpu] = "Sandcraft SR71000";
 855                 c->scache.ways = 8;
 856                 c->tlbsize = 64;
 857                 break;
 858         }
 859 }
 860
 861 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 862 {
 863         decode_configs(c);
 864         switch (c->processor_id & 0xff00) {
 865         case PRID_IMP_PR4450:
 866                 c->cputype = CPU_PR4450;
 867                 __cpu_name[cpu] = "Philips PR4450";
 868                 c->isa_level = MIPS_CPU_ISA_M32R1;
 869                 break;
 870         }
 871 }
 872
 873 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 874 {
 875         decode_configs(c);
 876         switch (c->processor_id & 0xff00) {
 877         case PRID_IMP_BCM3302:
 878          /* same as PRID_IMP_BCM6338 */
 879                 c->cputype = CPU_BCM3302;
 880                 __cpu_name[cpu] = "Broadcom BCM3302";
 881                 break;
 882         case PRID_IMP_BCM4710:
 883                 c->cputype = CPU_BCM4710;
 884                 __cpu_name[cpu] = "Broadcom BCM4710";
 885                 break;
 886         case PRID_IMP_BCM6345:
 887                 c->cputype = CPU_BCM6345;
 888                 __cpu_name[cpu] = "Broadcom BCM6345";
 889                 break;
 890         case PRID_IMP_BCM6348:
 891                 c->cputype = CPU_BCM6348;
 892                 __cpu_name[cpu] = "Broadcom BCM6348";
 893                 break;
 894         case PRID_IMP_BCM4350:
 895                 switch (c->processor_id & 0xf0) {
 896                 case PRID_REV_BCM6358:
 897                         c->cputype = CPU_BCM6358;
 898                         __cpu_name[cpu] = "Broadcom BCM6358";
 899                         break;
 900                 default:
 901                         c->cputype = CPU_UNKNOWN;
 902                         break;
 903                 }
 904                 break;
 905         }
 906 }
 907
 908 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 909 {
 910         decode_configs(c);
 911         switch (c->processor_id & 0xff00) {
 912         case PRID_IMP_CAVIUM_CN38XX:
 913         case PRID_IMP_CAVIUM_CN31XX:
 914         case PRID_IMP_CAVIUM_CN30XX:
 915                 c->cputype = CPU_CAVIUM_OCTEON;
 916                 __cpu_name[cpu] = "Cavium Octeon";
 917                 goto platform;
 918         case PRID_IMP_CAVIUM_CN58XX:
 919         case PRID_IMP_CAVIUM_CN56XX:
 920         case PRID_IMP_CAVIUM_CN50XX:
 921         case PRID_IMP_CAVIUM_CN52XX:
 922                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 923                 __cpu_name[cpu] = "Cavium Octeon+";
 924 platform:
 925                 if (cpu == 0)
 926                         __elf_platform = "octeon";
 927                 break;
 928         default:
 929                 printk(KERN_INFO "Unknown Octeon chip!\n");
 930                 c->cputype = CPU_UNKNOWN;
 931                 break;
 932         }
 933 }
 934
 935 const char *__cpu_name[NR_CPUS];
 936 const char *__elf_platform;
 937
 938 __cpuinit void cpu_probe(void)
 939 {
 940         struct cpuinfo_mips *c = &current_cpu_data;
 941         unsigned int cpu = smp_processor_id();
 942
 943         c->processor_id = PRID_IMP_UNKNOWN;
 944         c->fpu_id       = FPIR_IMP_NONE;
 945         c->cputype      = CPU_UNKNOWN;
 946
 947         c->processor_id = read_c0_prid();
 948         switch (c->processor_id & 0xff0000) {
 949         case PRID_COMP_LEGACY:
 950                 cpu_probe_legacy(c, cpu);
 951                 break;
 952         case PRID_COMP_MIPS:
 953                 cpu_probe_mips(c, cpu);
 954                 break;
 955         case PRID_COMP_ALCHEMY:
 956                 cpu_probe_alchemy(c, cpu);
 957                 break;
 958         case PRID_COMP_SIBYTE:
 959                 cpu_probe_sibyte(c, cpu);
 960                 break;
 961         case PRID_COMP_BROADCOM:
 962                 cpu_probe_broadcom(c, cpu);
 963                 break;
 964         case PRID_COMP_SANDCRAFT:
 965                 cpu_probe_sandcraft(c, cpu);
 966                 break;
 967         case PRID_COMP_NXP:
 968                 cpu_probe_nxp(c, cpu);
 969                 break;
 970         case PRID_COMP_CAVIUM:
 971                 cpu_probe_cavium(c, cpu);
 972                 break;
 973         }
 974
 975         BUG_ON(!__cpu_name[cpu]);
 976         BUG_ON(c->cputype == CPU_UNKNOWN);
 977
 978         /*
 979          * Platform code can force the cpu type to optimize code
 980          * generation. In that case be sure the cpu type is correctly
 981          * manually setup otherwise it could trigger some nasty bugs.
 982          */
 983         BUG_ON(current_cpu_type() != c->cputype);
 984
 985         if (c->options & MIPS_CPU_FPU) {
 986                 c->fpu_id = cpu_get_fpu_id();
 987
 988                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 989                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 990                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 991                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 992                         if (c->fpu_id & MIPS_FPIR_3D)
 993                                 c->ases |= MIPS_ASE_MIPS3D;
 994                 }
 995         }
 996
 997         if (cpu_has_mips_r2)
 998                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
 999         else
1000                 c->srsets = 1;
1001
1002         cpu_probe_vmbits(c);
1003 }
1004
1005 __cpuinit void cpu_report(void)
1006 {
1007         struct cpuinfo_mips *c = &current_cpu_data;
1008
1009         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1010                c->processor_id, cpu_name_string());
1011         if (c->options & MIPS_CPU_FPU)
1012                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1013 }