arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/module.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/fpu.h>
  24 #include <asm/mipsregs.h>
  25 #include <asm/system.h>
  26 #include <asm/watch.h>
  27 #include <asm/spram.h>
  28 /*
  29  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  30  * the implementation of the "wait" feature differs between CPU families. This
  31  * points to the function that implements CPU specific wait.
  32  * The wait instruction stops the pipeline and reduces the power consumption of
  33  * the CPU very much.
  34  */
  35 void (*cpu_wait)(void);
  36 EXPORT_SYMBOL(cpu_wait);
  37
  38 static void r3081_wait(void)
  39 {
  40         unsigned long cfg = read_c0_conf();
  41         write_c0_conf(cfg | R30XX_CONF_HALT);
  42 }
  43
  44 static void r39xx_wait(void)
  45 {
  46         local_irq_disable();
  47         if (!need_resched())
  48                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  49         local_irq_enable();
  50 }
  51
  52 extern void r4k_wait(void);
  53
  54 /*
  55  * This variant is preferable as it allows testing need_resched and going to
  56  * sleep depending on the outcome atomically.  Unfortunately the "It is
  57  * implementation-dependent whether the pipeline restarts when a non-enabled
  58  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  59  * using this version a gamble.
  60  */
  61 void r4k_wait_irqoff(void)
  62 {
  63         local_irq_disable();
  64         if (!need_resched())
  65                 __asm__("       .set    push            \n"
  66                         "       .set    mips3           \n"
  67                         "       wait                    \n"
  68                         "       .set    pop             \n");
  69         local_irq_enable();
  70         __asm__("       .globl __pastwait       \n"
  71                 "__pastwait:                    \n");
  72         return;
  73 }
  74
  75 /*
  76  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  77  * have any pending stores when the WAIT instruction is executed.
  78  */
  79 static void rm7k_wait_irqoff(void)
  80 {
  81         local_irq_disable();
  82         if (!need_resched())
  83                 __asm__(
  84                 "       .set    push                                    \n"
  85                 "       .set    mips3                                   \n"
  86                 "       .set    noat                                    \n"
  87                 "       mfc0    $1, $12                                 \n"
  88                 "       sync                                            \n"
  89                 "       mtc0    $1, $12         # stalls until W stage  \n"
  90                 "       wait                                            \n"
  91                 "       mtc0    $1, $12         # stalls until W stage  \n"
  92                 "       .set    pop                                     \n");
  93         local_irq_enable();
  94 }
  95
  96 /*
  97  * The Au1xxx wait is available only if using 32khz counter or
  98  * external timer source, but specifically not CP0 Counter.
  99  * alchemy/common/time.c may override cpu_wait!
 100  */
 101 static void au1k_wait(void)
 102 {
 103         __asm__("       .set    mips3                   \n"
 104                 "       cache   0x14, 0(%0)             \n"
 105                 "       cache   0x14, 32(%0)            \n"
 106                 "       sync                            \n"
 107                 "       nop                             \n"
 108                 "       wait                            \n"
 109                 "       nop                             \n"
 110                 "       nop                             \n"
 111                 "       nop                             \n"
 112                 "       nop                             \n"
 113                 "       .set    mips0                   \n"
 114                 : : "r" (au1k_wait));
 115 }
 116
 117 static int __initdata nowait;
 118
 119 static int __init wait_disable(char *s)
 120 {
 121         nowait = 1;
 122
 123         return 1;
 124 }
 125
 126 __setup("nowait", wait_disable);
 127
 128 static int __cpuinitdata mips_fpu_disabled;
 129
 130 static int __init fpu_disable(char *s)
 131 {
 132         cpu_data[0].options &= ~MIPS_CPU_FPU;
 133         mips_fpu_disabled = 1;
 134
 135         return 1;
 136 }
 137
 138 __setup("nofpu", fpu_disable);
 139
 140 int __cpuinitdata mips_dsp_disabled;
 141
 142 static int __init dsp_disable(char *s)
 143 {
 144         cpu_data[0].ases &= ~MIPS_ASE_DSP;
 145         mips_dsp_disabled = 1;
 146
 147         return 1;
 148 }
 149
 150 __setup("nodsp", dsp_disable);
 151
 152 void __init check_wait(void)
 153 {
 154         struct cpuinfo_mips *c = &current_cpu_data;
 155
 156         if (nowait) {
 157                 printk("Wait instruction disabled.\n");
 158                 return;
 159         }
 160
 161         switch (c->cputype) {
 162         case CPU_R3081:
 163         case CPU_R3081E:
 164                 cpu_wait = r3081_wait;
 165                 break;
 166         case CPU_TX3927:
 167                 cpu_wait = r39xx_wait;
 168                 break;
 169         case CPU_R4200:
 170 /*      case CPU_R4300: */
 171         case CPU_R4600:
 172         case CPU_R4640:
 173         case CPU_R4650:
 174         case CPU_R4700:
 175         case CPU_R5000:
 176         case CPU_R5500:
 177         case CPU_NEVADA:
 178         case CPU_4KC:
 179         case CPU_4KEC:
 180         case CPU_4KSC:
 181         case CPU_5KC:
 182         case CPU_25KF:
 183         case CPU_PR4450:
 184         case CPU_BCM3302:
 185         case CPU_BCM6338:
 186         case CPU_BCM6348:
 187         case CPU_BCM6358:
 188         case CPU_CAVIUM_OCTEON:
 189         case CPU_CAVIUM_OCTEON_PLUS:
 190                 cpu_wait = r4k_wait;
 191                 break;
 192
 193         case CPU_RM7000:
 194                 cpu_wait = rm7k_wait_irqoff;
 195                 break;
 196
 197         case CPU_24K:
 198         case CPU_34K:
 199         case CPU_1004K:
 200                 cpu_wait = r4k_wait;
 201                 if (read_c0_config7() & MIPS_CONF7_WII)
 202                         cpu_wait = r4k_wait_irqoff;
 203                 break;
 204
 205         case CPU_74K:
 206                 cpu_wait = r4k_wait;
 207                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 208                         cpu_wait = r4k_wait_irqoff;
 209                 break;
 210
 211         case CPU_TX49XX:
 212                 cpu_wait = r4k_wait_irqoff;
 213                 break;
 214         case CPU_ALCHEMY:
 215                 cpu_wait = au1k_wait;
 216                 break;
 217         case CPU_20KC:
 218                 /*
 219                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 220                  * WAIT on Rev2.0 and Rev3.0 has E16.
 221                  * Rev3.1 WAIT is nop, why bother
 222                  */
 223                 if ((c->processor_id & 0xff) <= 0x64)
 224                         break;
 225
 226                 /*
 227                  * Another rev is incremeting c0_count at a reduced clock
 228                  * rate while in WAIT mode.  So we basically have the choice
 229                  * between using the cp0 timer as clocksource or avoiding
 230                  * the WAIT instruction.  Until more details are known,
 231                  * disable the use of WAIT for 20Kc entirely.
 232                    cpu_wait = r4k_wait;
 233                  */
 234                 break;
 235         case CPU_RM9000:
 236                 if ((c->processor_id & 0x00ff) >= 0x40)
 237                         cpu_wait = r4k_wait;
 238                 break;
 239         default:
 240                 break;
 241         }
 242 }
 243
 244 static inline void check_errata(void)
 245 {
 246         struct cpuinfo_mips *c = &current_cpu_data;
 247
 248         switch (c->cputype) {
 249         case CPU_34K:
 250                 /*
 251                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 252                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 253                  * making use of VPE1 will be responsable for that VPE.
 254                  */
 255                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 256                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 257                 break;
 258         default:
 259                 break;
 260         }
 261 }
 262
 263 void __init check_bugs32(void)
 264 {
 265         check_errata();
 266 }
 267
 268 /*
 269  * Probe whether cpu has config register by trying to play with
 270  * alternate cache bit and see whether it matters.
 271  * It's used by cpu_probe to distinguish between R3000A and R3081.
 272  */
 273 static inline int cpu_has_confreg(void)
 274 {
 275 #ifdef CONFIG_CPU_R3000
 276         extern unsigned long r3k_cache_size(unsigned long);
 277         unsigned long size1, size2;
 278         unsigned long cfg = read_c0_conf();
 279
 280         size1 = r3k_cache_size(ST0_ISC);
 281         write_c0_conf(cfg ^ R30XX_CONF_AC);
 282         size2 = r3k_cache_size(ST0_ISC);
 283         write_c0_conf(cfg);
 284         return size1 != size2;
 285 #else
 286         return 0;
 287 #endif
 288 }
 289
 290 /*
 291  * Get the FPU Implementation/Revision.
 292  */
 293 static inline unsigned long cpu_get_fpu_id(void)
 294 {
 295         unsigned long tmp, fpu_id;
 296
 297         tmp = read_c0_status();
 298         __enable_fpu();
 299         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 300         write_c0_status(tmp);
 301         return fpu_id;
 302 }
 303
 304 /*
 305  * Check the CPU has an FPU the official way.
 306  */
 307 static inline int __cpu_has_fpu(void)
 308 {
 309         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 310 }
 311
 312 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 313 {
 314 #ifdef __NEED_VMBITS_PROBE
 315         write_c0_entryhi(0x3fffffffffffe000ULL);
 316         back_to_back_c0_hazard();
 317         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 318 #endif
 319 }
 320
 321 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 322                 | MIPS_CPU_COUNTER)
 323
 324 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 325 {
 326         switch (c->processor_id & 0xff00) {
 327         case PRID_IMP_R2000:
 328                 c->cputype = CPU_R2000;
 329                 __cpu_name[cpu] = "R2000";
 330                 c->isa_level = MIPS_CPU_ISA_I;
 331                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 332                              MIPS_CPU_NOFPUEX;
 333                 if (__cpu_has_fpu())
 334                         c->options |= MIPS_CPU_FPU;
 335                 c->tlbsize = 64;
 336                 break;
 337         case PRID_IMP_R3000:
 338                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 339                         if (cpu_has_confreg()) {
 340                                 c->cputype = CPU_R3081E;
 341                                 __cpu_name[cpu] = "R3081";
 342                         } else {
 343                                 c->cputype = CPU_R3000A;
 344                                 __cpu_name[cpu] = "R3000A";
 345                         }
 346                         break;
 347                 } else {
 348                         c->cputype = CPU_R3000;
 349                         __cpu_name[cpu] = "R3000";
 350                 }
 351                 c->isa_level = MIPS_CPU_ISA_I;
 352                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 353                              MIPS_CPU_NOFPUEX;
 354                 if (__cpu_has_fpu())
 355                         c->options |= MIPS_CPU_FPU;
 356                 c->tlbsize = 64;
 357                 break;
 358         case PRID_IMP_R4000:
 359                 if (read_c0_config() & CONF_SC) {
 360                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 361                                 c->cputype = CPU_R4400PC;
 362                                 __cpu_name[cpu] = "R4400PC";
 363                         } else {
 364                                 c->cputype = CPU_R4000PC;
 365                                 __cpu_name[cpu] = "R4000PC";
 366                         }
 367                 } else {
 368                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 369                                 c->cputype = CPU_R4400SC;
 370                                 __cpu_name[cpu] = "R4400SC";
 371                         } else {
 372                                 c->cputype = CPU_R4000SC;
 373                                 __cpu_name[cpu] = "R4000SC";
 374                         }
 375                 }
 376
 377                 c->isa_level = MIPS_CPU_ISA_III;
 378                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 379                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 380                              MIPS_CPU_LLSC;
 381                 c->tlbsize = 48;
 382                 break;
 383         case PRID_IMP_VR41XX:
 384                 switch (c->processor_id & 0xf0) {
 385                 case PRID_REV_VR4111:
 386                         c->cputype = CPU_VR4111;
 387                         __cpu_name[cpu] = "NEC VR4111";
 388                         break;
 389                 case PRID_REV_VR4121:
 390                         c->cputype = CPU_VR4121;
 391                         __cpu_name[cpu] = "NEC VR4121";
 392                         break;
 393                 case PRID_REV_VR4122:
 394                         if ((c->processor_id & 0xf) < 0x3) {
 395                                 c->cputype = CPU_VR4122;
 396                                 __cpu_name[cpu] = "NEC VR4122";
 397                         } else {
 398                                 c->cputype = CPU_VR4181A;
 399                                 __cpu_name[cpu] = "NEC VR4181A";
 400                         }
 401                         break;
 402                 case PRID_REV_VR4130:
 403                         if ((c->processor_id & 0xf) < 0x4) {
 404                                 c->cputype = CPU_VR4131;
 405                                 __cpu_name[cpu] = "NEC VR4131";
 406                         } else {
 407                                 c->cputype = CPU_VR4133;
 408                                 __cpu_name[cpu] = "NEC VR4133";
 409                         }
 410                         break;
 411                 default:
 412                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 413                         c->cputype = CPU_VR41XX;
 414                         __cpu_name[cpu] = "NEC Vr41xx";
 415                         break;
 416                 }
 417                 c->isa_level = MIPS_CPU_ISA_III;
 418                 c->options = R4K_OPTS;
 419                 c->tlbsize = 32;
 420                 break;
 421         case PRID_IMP_R4300:
 422                 c->cputype = CPU_R4300;
 423                 __cpu_name[cpu] = "R4300";
 424                 c->isa_level = MIPS_CPU_ISA_III;
 425                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 426                              MIPS_CPU_LLSC;
 427                 c->tlbsize = 32;
 428                 break;
 429         case PRID_IMP_R4600:
 430                 c->cputype = CPU_R4600;
 431                 __cpu_name[cpu] = "R4600";
 432                 c->isa_level = MIPS_CPU_ISA_III;
 433                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 434                              MIPS_CPU_LLSC;
 435                 c->tlbsize = 48;
 436                 break;
 437         #if 0
 438         case PRID_IMP_R4650:
 439                 /*
 440                  * This processor doesn't have an MMU, so it's not
 441                  * "real easy" to run Linux on it. It is left purely
 442                  * for documentation.  Commented out because it shares
 443                  * it's c0_prid id number with the TX3900.
 444                  */
 445                 c->cputype = CPU_R4650;
 446                 __cpu_name[cpu] = "R4650";
 447                 c->isa_level = MIPS_CPU_ISA_III;
 448                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 449                 c->tlbsize = 48;
 450                 break;
 451         #endif
 452         case PRID_IMP_TX39:
 453                 c->isa_level = MIPS_CPU_ISA_I;
 454                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 455
 456                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 457                         c->cputype = CPU_TX3927;
 458                         __cpu_name[cpu] = "TX3927";
 459                         c->tlbsize = 64;
 460                 } else {
 461                         switch (c->processor_id & 0xff) {
 462                         case PRID_REV_TX3912:
 463                                 c->cputype = CPU_TX3912;
 464                                 __cpu_name[cpu] = "TX3912";
 465                                 c->tlbsize = 32;
 466                                 break;
 467                         case PRID_REV_TX3922:
 468                                 c->cputype = CPU_TX3922;
 469                                 __cpu_name[cpu] = "TX3922";
 470                                 c->tlbsize = 64;
 471                                 break;
 472                         }
 473                 }
 474                 break;
 475         case PRID_IMP_R4700:
 476                 c->cputype = CPU_R4700;
 477                 __cpu_name[cpu] = "R4700";
 478                 c->isa_level = MIPS_CPU_ISA_III;
 479                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 480                              MIPS_CPU_LLSC;
 481                 c->tlbsize = 48;
 482                 break;
 483         case PRID_IMP_TX49:
 484                 c->cputype = CPU_TX49XX;
 485                 __cpu_name[cpu] = "R49XX";
 486                 c->isa_level = MIPS_CPU_ISA_III;
 487                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 488                 if (!(c->processor_id & 0x08))
 489                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 490                 c->tlbsize = 48;
 491                 break;
 492         case PRID_IMP_R5000:
 493                 c->cputype = CPU_R5000;
 494                 __cpu_name[cpu] = "R5000";
 495                 c->isa_level = MIPS_CPU_ISA_IV;
 496                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 497                              MIPS_CPU_LLSC;
 498                 c->tlbsize = 48;
 499                 break;
 500         case PRID_IMP_R5432:
 501                 c->cputype = CPU_R5432;
 502                 __cpu_name[cpu] = "R5432";
 503                 c->isa_level = MIPS_CPU_ISA_IV;
 504                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 505                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 506                 c->tlbsize = 48;
 507                 break;
 508         case PRID_IMP_R5500:
 509                 c->cputype = CPU_R5500;
 510                 __cpu_name[cpu] = "R5500";
 511                 c->isa_level = MIPS_CPU_ISA_IV;
 512                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 513                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 514                 c->tlbsize = 48;
 515                 break;
 516         case PRID_IMP_NEVADA:
 517                 c->cputype = CPU_NEVADA;
 518                 __cpu_name[cpu] = "Nevada";
 519                 c->isa_level = MIPS_CPU_ISA_IV;
 520                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 521                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 522                 c->tlbsize = 48;
 523                 break;
 524         case PRID_IMP_R6000:
 525                 c->cputype = CPU_R6000;
 526                 __cpu_name[cpu] = "R6000";
 527                 c->isa_level = MIPS_CPU_ISA_II;
 528                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 529                              MIPS_CPU_LLSC;
 530                 c->tlbsize = 32;
 531                 break;
 532         case PRID_IMP_R6000A:
 533                 c->cputype = CPU_R6000A;
 534                 __cpu_name[cpu] = "R6000A";
 535                 c->isa_level = MIPS_CPU_ISA_II;
 536                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 537                              MIPS_CPU_LLSC;
 538                 c->tlbsize = 32;
 539                 break;
 540         case PRID_IMP_RM7000:
 541                 c->cputype = CPU_RM7000;
 542                 __cpu_name[cpu] = "RM7000";
 543                 c->isa_level = MIPS_CPU_ISA_IV;
 544                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 545                              MIPS_CPU_LLSC;
 546                 /*
 547                  * Undocumented RM7000:  Bit 29 in the info register of
 548                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 549                  * entries.
 550                  *
 551                  * 29      1 =>    64 entry JTLB
 552                  *         0 =>    48 entry JTLB
 553                  */
 554                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 555                 break;
 556         case PRID_IMP_RM9000:
 557                 c->cputype = CPU_RM9000;
 558                 __cpu_name[cpu] = "RM9000";
 559                 c->isa_level = MIPS_CPU_ISA_IV;
 560                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 561                              MIPS_CPU_LLSC;
 562                 /*
 563                  * Bit 29 in the info register of the RM9000
 564                  * indicates if the TLB has 48 or 64 entries.
 565                  *
 566                  * 29      1 =>    64 entry JTLB
 567                  *         0 =>    48 entry JTLB
 568                  */
 569                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 570                 break;
 571         case PRID_IMP_R8000:
 572                 c->cputype = CPU_R8000;
 573                 __cpu_name[cpu] = "RM8000";
 574                 c->isa_level = MIPS_CPU_ISA_IV;
 575                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 576                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 577                              MIPS_CPU_LLSC;
 578                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 579                 break;
 580         case PRID_IMP_R10000:
 581                 c->cputype = CPU_R10000;
 582                 __cpu_name[cpu] = "R10000";
 583                 c->isa_level = MIPS_CPU_ISA_IV;
 584                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 585                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 586                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 587                              MIPS_CPU_LLSC;
 588                 c->tlbsize = 64;
 589                 break;
 590         case PRID_IMP_R12000:
 591                 c->cputype = CPU_R12000;
 592                 __cpu_name[cpu] = "R12000";
 593                 c->isa_level = MIPS_CPU_ISA_IV;
 594                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 595                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 596                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 597                              MIPS_CPU_LLSC;
 598                 c->tlbsize = 64;
 599                 break;
 600         case PRID_IMP_R14000:
 601                 c->cputype = CPU_R14000;
 602                 __cpu_name[cpu] = "R14000";
 603                 c->isa_level = MIPS_CPU_ISA_IV;
 604                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 605                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 606                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 607                              MIPS_CPU_LLSC;
 608                 c->tlbsize = 64;
 609                 break;
 610         case PRID_IMP_LOONGSON2:
 611                 c->cputype = CPU_LOONGSON2;
 612                 __cpu_name[cpu] = "ICT Loongson-2";
 613                 c->isa_level = MIPS_CPU_ISA_III;
 614                 c->options = R4K_OPTS |
 615                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 616                              MIPS_CPU_32FPR;
 617                 c->tlbsize = 64;
 618                 break;
 619         }
 620 }
 621
 622 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 623         "Unsupported ISA type, c0.config0: %d.";
 624
 625 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 626 {
 627         unsigned int config0;
 628         int isa;
 629
 630         config0 = read_c0_config();
 631
 632         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 633                 c->options |= MIPS_CPU_TLB;
 634         isa = (config0 & MIPS_CONF_AT) >> 13;
 635         switch (isa) {
 636         case 0:
 637                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 638                 case 0:
 639                         c->isa_level = MIPS_CPU_ISA_M32R1;
 640                         break;
 641                 case 1:
 642                         c->isa_level = MIPS_CPU_ISA_M32R2;
 643                         break;
 644                 default:
 645                         goto unknown;
 646                 }
 647                 break;
 648         case 2:
 649                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 650                 case 0:
 651                         c->isa_level = MIPS_CPU_ISA_M64R1;
 652                         break;
 653                 case 1:
 654                         c->isa_level = MIPS_CPU_ISA_M64R2;
 655                         break;
 656                 default:
 657                         goto unknown;
 658                 }
 659                 break;
 660         default:
 661                 goto unknown;
 662         }
 663
 664         return config0 & MIPS_CONF_M;
 665
 666 unknown:
 667         panic(unknown_isa, config0);
 668 }
 669
 670 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 671 {
 672         unsigned int config1;
 673
 674         config1 = read_c0_config1();
 675
 676         if (config1 & MIPS_CONF1_MD)
 677                 c->ases |= MIPS_ASE_MDMX;
 678         if (config1 & MIPS_CONF1_WR)
 679                 c->options |= MIPS_CPU_WATCH;
 680         if (config1 & MIPS_CONF1_CA)
 681                 c->ases |= MIPS_ASE_MIPS16;
 682         if (config1 & MIPS_CONF1_EP)
 683                 c->options |= MIPS_CPU_EJTAG;
 684         if (config1 & MIPS_CONF1_FP) {
 685                 c->options |= MIPS_CPU_FPU;
 686                 c->options |= MIPS_CPU_32FPR;
 687         }
 688         if (cpu_has_tlb)
 689                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 690
 691         return config1 & MIPS_CONF_M;
 692 }
 693
 694 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 695 {
 696         unsigned int config2;
 697
 698         config2 = read_c0_config2();
 699
 700         if (config2 & MIPS_CONF2_SL)
 701                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 702
 703         return config2 & MIPS_CONF_M;
 704 }
 705
 706 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 707 {
 708         unsigned int config3;
 709
 710         config3 = read_c0_config3();
 711
 712         if (config3 & MIPS_CONF3_SM)
 713                 c->ases |= MIPS_ASE_SMARTMIPS;
 714         if (config3 & MIPS_CONF3_DSP)
 715                 c->ases |= MIPS_ASE_DSP;
 716         if (config3 & MIPS_CONF3_VINT)
 717                 c->options |= MIPS_CPU_VINT;
 718         if (config3 & MIPS_CONF3_VEIC)
 719                 c->options |= MIPS_CPU_VEIC;
 720         if (config3 & MIPS_CONF3_MT)
 721                 c->ases |= MIPS_ASE_MIPSMT;
 722         if (config3 & MIPS_CONF3_ULRI)
 723                 c->options |= MIPS_CPU_ULRI;
 724
 725         return config3 & MIPS_CONF_M;
 726 }
 727
 728 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 729 {
 730         unsigned int config4;
 731
 732         config4 = read_c0_config4();
 733
 734         if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
 735             && cpu_has_tlb)
 736                 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 737
 738         return config4 & MIPS_CONF_M;
 739 }
 740
 741 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 742 {
 743         int ok;
 744
 745         /* MIPS32 or MIPS64 compliant CPU.  */
 746         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 747                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 748
 749         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 750
 751         ok = decode_config0(c);                 /* Read Config registers.  */
 752         BUG_ON(!ok);                            /* Arch spec violation!  */
 753         if (ok)
 754                 ok = decode_config1(c);
 755         if (ok)
 756                 ok = decode_config2(c);
 757         if (ok)
 758                 ok = decode_config3(c);
 759         if (ok)
 760                 ok = decode_config4(c);
 761
 762         mips_probe_watch_registers(c);
 763 }
 764
 765 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 766 {
 767         decode_configs(c);
 768         switch (c->processor_id & 0xff00) {
 769         case PRID_IMP_4KC:
 770                 c->cputype = CPU_4KC;
 771                 __cpu_name[cpu] = "MIPS 4Kc";
 772                 break;
 773         case PRID_IMP_4KEC:
 774         case PRID_IMP_4KECR2:
 775                 c->cputype = CPU_4KEC;
 776                 __cpu_name[cpu] = "MIPS 4KEc";
 777                 break;
 778         case PRID_IMP_4KSC:
 779         case PRID_IMP_4KSD:
 780                 c->cputype = CPU_4KSC;
 781                 __cpu_name[cpu] = "MIPS 4KSc";
 782                 break;
 783         case PRID_IMP_5KC:
 784                 c->cputype = CPU_5KC;
 785                 __cpu_name[cpu] = "MIPS 5Kc";
 786                 break;
 787         case PRID_IMP_20KC:
 788                 c->cputype = CPU_20KC;
 789                 __cpu_name[cpu] = "MIPS 20Kc";
 790                 break;
 791         case PRID_IMP_24K:
 792         case PRID_IMP_24KE:
 793                 c->cputype = CPU_24K;
 794                 __cpu_name[cpu] = "MIPS 24Kc";
 795                 break;
 796         case PRID_IMP_25KF:
 797                 c->cputype = CPU_25KF;
 798                 __cpu_name[cpu] = "MIPS 25Kc";
 799                 break;
 800         case PRID_IMP_34K:
 801                 c->cputype = CPU_34K;
 802                 __cpu_name[cpu] = "MIPS 34Kc";
 803                 break;
 804         case PRID_IMP_74K:
 805                 c->cputype = CPU_74K;
 806                 __cpu_name[cpu] = "MIPS 74Kc";
 807                 break;
 808         case PRID_IMP_1004K:
 809                 c->cputype = CPU_1004K;
 810                 __cpu_name[cpu] = "MIPS 1004Kc";
 811                 break;
 812         }
 813
 814         spram_config();
 815 }
 816
 817 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 818 {
 819         decode_configs(c);
 820         switch (c->processor_id & 0xff00) {
 821         case PRID_IMP_AU1_REV1:
 822         case PRID_IMP_AU1_REV2:
 823                 c->cputype = CPU_ALCHEMY;
 824                 switch ((c->processor_id >> 24) & 0xff) {
 825                 case 0:
 826                         __cpu_name[cpu] = "Au1000";
 827                         break;
 828                 case 1:
 829                         __cpu_name[cpu] = "Au1500";
 830                         break;
 831                 case 2:
 832                         __cpu_name[cpu] = "Au1100";
 833                         break;
 834                 case 3:
 835                         __cpu_name[cpu] = "Au1550";
 836                         break;
 837                 case 4:
 838                         __cpu_name[cpu] = "Au1200";
 839                         if ((c->processor_id & 0xff) == 2)
 840                                 __cpu_name[cpu] = "Au1250";
 841                         break;
 842                 case 5:
 843                         __cpu_name[cpu] = "Au1210";
 844                         break;
 845                 default:
 846                         __cpu_name[cpu] = "Au1xxx";
 847                         break;
 848                 }
 849                 break;
 850         }
 851 }
 852
 853 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 854 {
 855         decode_configs(c);
 856
 857         switch (c->processor_id & 0xff00) {
 858         case PRID_IMP_SB1:
 859                 c->cputype = CPU_SB1;
 860                 __cpu_name[cpu] = "SiByte SB1";
 861                 /* FPU in pass1 is known to have issues. */
 862                 if ((c->processor_id & 0xff) < 0x02)
 863                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 864                 break;
 865         case PRID_IMP_SB1A:
 866                 c->cputype = CPU_SB1A;
 867                 __cpu_name[cpu] = "SiByte SB1A";
 868                 break;
 869         }
 870 }
 871
 872 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 873 {
 874         decode_configs(c);
 875         switch (c->processor_id & 0xff00) {
 876         case PRID_IMP_SR71000:
 877                 c->cputype = CPU_SR71000;
 878                 __cpu_name[cpu] = "Sandcraft SR71000";
 879                 c->scache.ways = 8;
 880                 c->tlbsize = 64;
 881                 break;
 882         }
 883 }
 884
 885 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 886 {
 887         decode_configs(c);
 888         switch (c->processor_id & 0xff00) {
 889         case PRID_IMP_PR4450:
 890                 c->cputype = CPU_PR4450;
 891                 __cpu_name[cpu] = "Philips PR4450";
 892                 c->isa_level = MIPS_CPU_ISA_M32R1;
 893                 break;
 894         }
 895 }
 896
 897 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 898 {
 899         decode_configs(c);
 900         switch (c->processor_id & 0xff00) {
 901         case PRID_IMP_BCM3302:
 902          /* same as PRID_IMP_BCM6338 */
 903                 c->cputype = CPU_BCM3302;
 904                 __cpu_name[cpu] = "Broadcom BCM3302";
 905                 break;
 906         case PRID_IMP_BCM4710:
 907                 c->cputype = CPU_BCM4710;
 908                 __cpu_name[cpu] = "Broadcom BCM4710";
 909                 break;
 910         case PRID_IMP_BCM6345:
 911                 c->cputype = CPU_BCM6345;
 912                 __cpu_name[cpu] = "Broadcom BCM6345";
 913                 break;
 914         case PRID_IMP_BCM6348:
 915                 c->cputype = CPU_BCM6348;
 916                 __cpu_name[cpu] = "Broadcom BCM6348";
 917                 break;
 918         case PRID_IMP_BCM4350:
 919                 switch (c->processor_id & 0xf0) {
 920                 case PRID_REV_BCM6358:
 921                         c->cputype = CPU_BCM6358;
 922                         __cpu_name[cpu] = "Broadcom BCM6358";
 923                         break;
 924                 default:
 925                         c->cputype = CPU_UNKNOWN;
 926                         break;
 927                 }
 928                 break;
 929         }
 930 }
 931
 932 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
 933 {
 934         decode_configs(c);
 935         switch (c->processor_id & 0xff00) {
 936         case PRID_IMP_CAVIUM_CN38XX:
 937         case PRID_IMP_CAVIUM_CN31XX:
 938         case PRID_IMP_CAVIUM_CN30XX:
 939                 c->cputype = CPU_CAVIUM_OCTEON;
 940                 __cpu_name[cpu] = "Cavium Octeon";
 941                 goto platform;
 942         case PRID_IMP_CAVIUM_CN58XX:
 943         case PRID_IMP_CAVIUM_CN56XX:
 944         case PRID_IMP_CAVIUM_CN50XX:
 945         case PRID_IMP_CAVIUM_CN52XX:
 946                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
 947                 __cpu_name[cpu] = "Cavium Octeon+";
 948 platform:
 949                 if (cpu == 0)
 950                         __elf_platform = "octeon";
 951                 break;
 952         default:
 953                 printk(KERN_INFO "Unknown Octeon chip!\n");
 954                 c->cputype = CPU_UNKNOWN;
 955                 break;
 956         }
 957 }
 958
 959 const char *__cpu_name[NR_CPUS];
 960 const char *__elf_platform;
 961
 962 __cpuinit void cpu_probe(void)
 963 {
 964         struct cpuinfo_mips *c = &current_cpu_data;
 965         unsigned int cpu = smp_processor_id();
 966
 967         c->processor_id = PRID_IMP_UNKNOWN;
 968         c->fpu_id       = FPIR_IMP_NONE;
 969         c->cputype      = CPU_UNKNOWN;
 970
 971         c->processor_id = read_c0_prid();
 972         switch (c->processor_id & 0xff0000) {
 973         case PRID_COMP_LEGACY:
 974                 cpu_probe_legacy(c, cpu);
 975                 break;
 976         case PRID_COMP_MIPS:
 977                 cpu_probe_mips(c, cpu);
 978                 break;
 979         case PRID_COMP_ALCHEMY:
 980                 cpu_probe_alchemy(c, cpu);
 981                 break;
 982         case PRID_COMP_SIBYTE:
 983                 cpu_probe_sibyte(c, cpu);
 984                 break;
 985         case PRID_COMP_BROADCOM:
 986                 cpu_probe_broadcom(c, cpu);
 987                 break;
 988         case PRID_COMP_SANDCRAFT:
 989                 cpu_probe_sandcraft(c, cpu);
 990                 break;
 991         case PRID_COMP_NXP:
 992                 cpu_probe_nxp(c, cpu);
 993                 break;
 994         case PRID_COMP_CAVIUM:
 995                 cpu_probe_cavium(c, cpu);
 996                 break;
 997         }
 998
 999         BUG_ON(!__cpu_name[cpu]);
1000         BUG_ON(c->cputype == CPU_UNKNOWN);
1001
1002         /*
1003          * Platform code can force the cpu type to optimize code
1004          * generation. In that case be sure the cpu type is correctly
1005          * manually setup otherwise it could trigger some nasty bugs.
1006          */
1007         BUG_ON(current_cpu_type() != c->cputype);
1008
1009         if (mips_fpu_disabled)
1010                 c->options &= ~MIPS_CPU_FPU;
1011
1012         if (mips_dsp_disabled)
1013                 c->ases &= ~MIPS_ASE_DSP;
1014
1015         if (c->options & MIPS_CPU_FPU) {
1016                 c->fpu_id = cpu_get_fpu_id();
1017
1018                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
1019                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
1020                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
1021                     c->isa_level == MIPS_CPU_ISA_M64R2) {
1022                         if (c->fpu_id & MIPS_FPIR_3D)
1023                                 c->ases |= MIPS_ASE_MIPS3D;
1024                 }
1025         }
1026
1027         if (cpu_has_mips_r2)
1028                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1029         else
1030                 c->srsets = 1;
1031
1032         cpu_probe_vmbits(c);
1033 }
1034
1035 __cpuinit void cpu_report(void)
1036 {
1037         struct cpuinfo_mips *c = &current_cpu_data;
1038
1039         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1040                c->processor_id, cpu_name_string());
1041         if (c->options & MIPS_CPU_FPU)
1042                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
1043 }