arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004  MIPS Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/stddef.h>
  18
  19 #include <asm/bugs.h>
  20 #include <asm/cpu.h>
  21 #include <asm/fpu.h>
  22 #include <asm/mipsregs.h>
  23 #include <asm/system.h>
  24 #include <asm/watch.h>
  25
  26 /*
  27  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
  28  * the implementation of the "wait" feature differs between CPU families. This
  29  * points to the function that implements CPU specific wait.
  30  * The wait instruction stops the pipeline and reduces the power consumption of
  31  * the CPU very much.
  32  */
  33 void (*cpu_wait)(void) = NULL;
  34
  35 static void r3081_wait(void)
  36 {
  37         unsigned long cfg = read_c0_conf();
  38         write_c0_conf(cfg | R30XX_CONF_HALT);
  39 }
  40
  41 static void r39xx_wait(void)
  42 {
  43         local_irq_disable();
  44         if (!need_resched())
  45                 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
  46         local_irq_enable();
  47 }
  48
  49 extern void r4k_wait(void);
  50
  51 /*
  52  * This variant is preferable as it allows testing need_resched and going to
  53  * sleep depending on the outcome atomically.  Unfortunately the "It is
  54  * implementation-dependent whether the pipeline restarts when a non-enabled
  55  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  56  * using this version a gamble.
  57  */
  58 void r4k_wait_irqoff(void)
  59 {
  60         local_irq_disable();
  61         if (!need_resched())
  62                 __asm__("       .set    push            \n"
  63                         "       .set    mips3           \n"
  64                         "       wait                    \n"
  65                         "       .set    pop             \n");
  66         local_irq_enable();
  67         __asm__("       .globl __pastwait       \n"
  68                 "__pastwait:                    \n");
  69         return;
  70 }
  71
  72 /*
  73  * The RM7000 variant has to handle erratum 38.  The workaround is to not
  74  * have any pending stores when the WAIT instruction is executed.
  75  */
  76 static void rm7k_wait_irqoff(void)
  77 {
  78         local_irq_disable();
  79         if (!need_resched())
  80                 __asm__(
  81                 "       .set    push                                    \n"
  82                 "       .set    mips3                                   \n"
  83                 "       .set    noat                                    \n"
  84                 "       mfc0    $1, $12                                 \n"
  85                 "       sync                                            \n"
  86                 "       mtc0    $1, $12         # stalls until W stage  \n"
  87                 "       wait                                            \n"
  88                 "       mtc0    $1, $12         # stalls until W stage  \n"
  89                 "       .set    pop                                     \n");
  90         local_irq_enable();
  91 }
  92
  93 /* The Au1xxx wait is available only if using 32khz counter or
  94  * external timer source, but specifically not CP0 Counter. */
  95 int allow_au1k_wait;
  96
  97 static void au1k_wait(void)
  98 {
  99         /* using the wait instruction makes CP0 counter unusable */
 100         __asm__("       .set    mips3                   \n"
 101                 "       cache   0x14, 0(%0)             \n"
 102                 "       cache   0x14, 32(%0)            \n"
 103                 "       sync                            \n"
 104                 "       nop                             \n"
 105                 "       wait                            \n"
 106                 "       nop                             \n"
 107                 "       nop                             \n"
 108                 "       nop                             \n"
 109                 "       nop                             \n"
 110                 "       .set    mips0                   \n"
 111                 : : "r" (au1k_wait));
 112 }
 113
 114 static int __initdata nowait = 0;
 115
 116 static int __init wait_disable(char *s)
 117 {
 118         nowait = 1;
 119
 120         return 1;
 121 }
 122
 123 __setup("nowait", wait_disable);
 124
 125 void __init check_wait(void)
 126 {
 127         struct cpuinfo_mips *c = &current_cpu_data;
 128
 129         if (nowait) {
 130                 printk("Wait instruction disabled.\n");
 131                 return;
 132         }
 133
 134         switch (c->cputype) {
 135         case CPU_R3081:
 136         case CPU_R3081E:
 137                 cpu_wait = r3081_wait;
 138                 break;
 139         case CPU_TX3927:
 140                 cpu_wait = r39xx_wait;
 141                 break;
 142         case CPU_R4200:
 143 /*      case CPU_R4300: */
 144         case CPU_R4600:
 145         case CPU_R4640:
 146         case CPU_R4650:
 147         case CPU_R4700:
 148         case CPU_R5000:
 149         case CPU_NEVADA:
 150         case CPU_4KC:
 151         case CPU_4KEC:
 152         case CPU_4KSC:
 153         case CPU_5KC:
 154         case CPU_25KF:
 155         case CPU_PR4450:
 156         case CPU_BCM3302:
 157                 cpu_wait = r4k_wait;
 158                 break;
 159
 160         case CPU_RM7000:
 161                 cpu_wait = rm7k_wait_irqoff;
 162                 break;
 163
 164         case CPU_24K:
 165         case CPU_34K:
 166         case CPU_1004K:
 167                 cpu_wait = r4k_wait;
 168                 if (read_c0_config7() & MIPS_CONF7_WII)
 169                         cpu_wait = r4k_wait_irqoff;
 170                 break;
 171
 172         case CPU_74K:
 173                 cpu_wait = r4k_wait;
 174                 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
 175                         cpu_wait = r4k_wait_irqoff;
 176                 break;
 177
 178         case CPU_TX49XX:
 179                 cpu_wait = r4k_wait_irqoff;
 180                 break;
 181         case CPU_AU1000:
 182         case CPU_AU1100:
 183         case CPU_AU1500:
 184         case CPU_AU1550:
 185         case CPU_AU1200:
 186         case CPU_AU1210:
 187         case CPU_AU1250:
 188                 if (allow_au1k_wait)
 189                         cpu_wait = au1k_wait;
 190                 break;
 191         case CPU_20KC:
 192                 /*
 193                  * WAIT on Rev1.0 has E1, E2, E3 and E16.
 194                  * WAIT on Rev2.0 and Rev3.0 has E16.
 195                  * Rev3.1 WAIT is nop, why bother
 196                  */
 197                 if ((c->processor_id & 0xff) <= 0x64)
 198                         break;
 199
 200                 /*
 201                  * Another rev is incremeting c0_count at a reduced clock
 202                  * rate while in WAIT mode.  So we basically have the choice
 203                  * between using the cp0 timer as clocksource or avoiding
 204                  * the WAIT instruction.  Until more details are known,
 205                  * disable the use of WAIT for 20Kc entirely.
 206                    cpu_wait = r4k_wait;
 207                  */
 208                 break;
 209         case CPU_RM9000:
 210                 if ((c->processor_id & 0x00ff) >= 0x40)
 211                         cpu_wait = r4k_wait;
 212                 break;
 213         default:
 214                 break;
 215         }
 216 }
 217
 218 static inline void check_errata(void)
 219 {
 220         struct cpuinfo_mips *c = &current_cpu_data;
 221
 222         switch (c->cputype) {
 223         case CPU_34K:
 224                 /*
 225                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 226                  * This code only handles VPE0, any SMP/SMTC/RTOS code
 227                  * making use of VPE1 will be responsable for that VPE.
 228                  */
 229                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 230                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 231                 break;
 232         default:
 233                 break;
 234         }
 235 }
 236
 237 void __init check_bugs32(void)
 238 {
 239         check_errata();
 240 }
 241
 242 /*
 243  * Probe whether cpu has config register by trying to play with
 244  * alternate cache bit and see whether it matters.
 245  * It's used by cpu_probe to distinguish between R3000A and R3081.
 246  */
 247 static inline int cpu_has_confreg(void)
 248 {
 249 #ifdef CONFIG_CPU_R3000
 250         extern unsigned long r3k_cache_size(unsigned long);
 251         unsigned long size1, size2;
 252         unsigned long cfg = read_c0_conf();
 253
 254         size1 = r3k_cache_size(ST0_ISC);
 255         write_c0_conf(cfg ^ R30XX_CONF_AC);
 256         size2 = r3k_cache_size(ST0_ISC);
 257         write_c0_conf(cfg);
 258         return size1 != size2;
 259 #else
 260         return 0;
 261 #endif
 262 }
 263
 264 /*
 265  * Get the FPU Implementation/Revision.
 266  */
 267 static inline unsigned long cpu_get_fpu_id(void)
 268 {
 269         unsigned long tmp, fpu_id;
 270
 271         tmp = read_c0_status();
 272         __enable_fpu();
 273         fpu_id = read_32bit_cp1_register(CP1_REVISION);
 274         write_c0_status(tmp);
 275         return fpu_id;
 276 }
 277
 278 /*
 279  * Check the CPU has an FPU the official way.
 280  */
 281 static inline int __cpu_has_fpu(void)
 282 {
 283         return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 284 }
 285
 286 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
 287                 | MIPS_CPU_COUNTER)
 288
 289 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
 290 {
 291         switch (c->processor_id & 0xff00) {
 292         case PRID_IMP_R2000:
 293                 c->cputype = CPU_R2000;
 294                 __cpu_name[cpu] = "R2000";
 295                 c->isa_level = MIPS_CPU_ISA_I;
 296                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 297                              MIPS_CPU_NOFPUEX;
 298                 if (__cpu_has_fpu())
 299                         c->options |= MIPS_CPU_FPU;
 300                 c->tlbsize = 64;
 301                 break;
 302         case PRID_IMP_R3000:
 303                 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
 304                         if (cpu_has_confreg()) {
 305                                 c->cputype = CPU_R3081E;
 306                                 __cpu_name[cpu] = "R3081";
 307                         } else {
 308                                 c->cputype = CPU_R3000A;
 309                                 __cpu_name[cpu] = "R3000A";
 310                         }
 311                         break;
 312                 } else {
 313                         c->cputype = CPU_R3000;
 314                         __cpu_name[cpu] = "R3000";
 315                 }
 316                 c->isa_level = MIPS_CPU_ISA_I;
 317                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
 318                              MIPS_CPU_NOFPUEX;
 319                 if (__cpu_has_fpu())
 320                         c->options |= MIPS_CPU_FPU;
 321                 c->tlbsize = 64;
 322                 break;
 323         case PRID_IMP_R4000:
 324                 if (read_c0_config() & CONF_SC) {
 325                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 326                                 c->cputype = CPU_R4400PC;
 327                                 __cpu_name[cpu] = "R4400PC";
 328                         } else {
 329                                 c->cputype = CPU_R4000PC;
 330                                 __cpu_name[cpu] = "R4000PC";
 331                         }
 332                 } else {
 333                         if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
 334                                 c->cputype = CPU_R4400SC;
 335                                 __cpu_name[cpu] = "R4400SC";
 336                         } else {
 337                                 c->cputype = CPU_R4000SC;
 338                                 __cpu_name[cpu] = "R4000SC";
 339                         }
 340                 }
 341
 342                 c->isa_level = MIPS_CPU_ISA_III;
 343                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 344                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
 345                              MIPS_CPU_LLSC;
 346                 c->tlbsize = 48;
 347                 break;
 348         case PRID_IMP_VR41XX:
 349                 switch (c->processor_id & 0xf0) {
 350                 case PRID_REV_VR4111:
 351                         c->cputype = CPU_VR4111;
 352                         __cpu_name[cpu] = "NEC VR4111";
 353                         break;
 354                 case PRID_REV_VR4121:
 355                         c->cputype = CPU_VR4121;
 356                         __cpu_name[cpu] = "NEC VR4121";
 357                         break;
 358                 case PRID_REV_VR4122:
 359                         if ((c->processor_id & 0xf) < 0x3) {
 360                                 c->cputype = CPU_VR4122;
 361                                 __cpu_name[cpu] = "NEC VR4122";
 362                         } else {
 363                                 c->cputype = CPU_VR4181A;
 364                                 __cpu_name[cpu] = "NEC VR4181A";
 365                         }
 366                         break;
 367                 case PRID_REV_VR4130:
 368                         if ((c->processor_id & 0xf) < 0x4) {
 369                                 c->cputype = CPU_VR4131;
 370                                 __cpu_name[cpu] = "NEC VR4131";
 371                         } else {
 372                                 c->cputype = CPU_VR4133;
 373                                 __cpu_name[cpu] = "NEC VR4133";
 374                         }
 375                         break;
 376                 default:
 377                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
 378                         c->cputype = CPU_VR41XX;
 379                         __cpu_name[cpu] = "NEC Vr41xx";
 380                         break;
 381                 }
 382                 c->isa_level = MIPS_CPU_ISA_III;
 383                 c->options = R4K_OPTS;
 384                 c->tlbsize = 32;
 385                 break;
 386         case PRID_IMP_R4300:
 387                 c->cputype = CPU_R4300;
 388                 __cpu_name[cpu] = "R4300";
 389                 c->isa_level = MIPS_CPU_ISA_III;
 390                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 391                              MIPS_CPU_LLSC;
 392                 c->tlbsize = 32;
 393                 break;
 394         case PRID_IMP_R4600:
 395                 c->cputype = CPU_R4600;
 396                 __cpu_name[cpu] = "R4600";
 397                 c->isa_level = MIPS_CPU_ISA_III;
 398                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 399                              MIPS_CPU_LLSC;
 400                 c->tlbsize = 48;
 401                 break;
 402         #if 0
 403         case PRID_IMP_R4650:
 404                 /*
 405                  * This processor doesn't have an MMU, so it's not
 406                  * "real easy" to run Linux on it. It is left purely
 407                  * for documentation.  Commented out because it shares
 408                  * it's c0_prid id number with the TX3900.
 409                  */
 410                 c->cputype = CPU_R4650;
 411                 __cpu_name[cpu] = "R4650";
 412                 c->isa_level = MIPS_CPU_ISA_III;
 413                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
 414                 c->tlbsize = 48;
 415                 break;
 416         #endif
 417         case PRID_IMP_TX39:
 418                 c->isa_level = MIPS_CPU_ISA_I;
 419                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 420
 421                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
 422                         c->cputype = CPU_TX3927;
 423                         __cpu_name[cpu] = "TX3927";
 424                         c->tlbsize = 64;
 425                 } else {
 426                         switch (c->processor_id & 0xff) {
 427                         case PRID_REV_TX3912:
 428                                 c->cputype = CPU_TX3912;
 429                                 __cpu_name[cpu] = "TX3912";
 430                                 c->tlbsize = 32;
 431                                 break;
 432                         case PRID_REV_TX3922:
 433                                 c->cputype = CPU_TX3922;
 434                                 __cpu_name[cpu] = "TX3922";
 435                                 c->tlbsize = 64;
 436                                 break;
 437                         }
 438                 }
 439                 break;
 440         case PRID_IMP_R4700:
 441                 c->cputype = CPU_R4700;
 442                 __cpu_name[cpu] = "R4700";
 443                 c->isa_level = MIPS_CPU_ISA_III;
 444                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 445                              MIPS_CPU_LLSC;
 446                 c->tlbsize = 48;
 447                 break;
 448         case PRID_IMP_TX49:
 449                 c->cputype = CPU_TX49XX;
 450                 __cpu_name[cpu] = "R49XX";
 451                 c->isa_level = MIPS_CPU_ISA_III;
 452                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
 453                 if (!(c->processor_id & 0x08))
 454                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
 455                 c->tlbsize = 48;
 456                 break;
 457         case PRID_IMP_R5000:
 458                 c->cputype = CPU_R5000;
 459                 __cpu_name[cpu] = "R5000";
 460                 c->isa_level = MIPS_CPU_ISA_IV;
 461                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 462                              MIPS_CPU_LLSC;
 463                 c->tlbsize = 48;
 464                 break;
 465         case PRID_IMP_R5432:
 466                 c->cputype = CPU_R5432;
 467                 __cpu_name[cpu] = "R5432";
 468                 c->isa_level = MIPS_CPU_ISA_IV;
 469                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 470                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 471                 c->tlbsize = 48;
 472                 break;
 473         case PRID_IMP_R5500:
 474                 c->cputype = CPU_R5500;
 475                 __cpu_name[cpu] = "R5500";
 476                 c->isa_level = MIPS_CPU_ISA_IV;
 477                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 478                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
 479                 c->tlbsize = 48;
 480                 break;
 481         case PRID_IMP_NEVADA:
 482                 c->cputype = CPU_NEVADA;
 483                 __cpu_name[cpu] = "Nevada";
 484                 c->isa_level = MIPS_CPU_ISA_IV;
 485                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 486                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
 487                 c->tlbsize = 48;
 488                 break;
 489         case PRID_IMP_R6000:
 490                 c->cputype = CPU_R6000;
 491                 __cpu_name[cpu] = "R6000";
 492                 c->isa_level = MIPS_CPU_ISA_II;
 493                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 494                              MIPS_CPU_LLSC;
 495                 c->tlbsize = 32;
 496                 break;
 497         case PRID_IMP_R6000A:
 498                 c->cputype = CPU_R6000A;
 499                 __cpu_name[cpu] = "R6000A";
 500                 c->isa_level = MIPS_CPU_ISA_II;
 501                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
 502                              MIPS_CPU_LLSC;
 503                 c->tlbsize = 32;
 504                 break;
 505         case PRID_IMP_RM7000:
 506                 c->cputype = CPU_RM7000;
 507                 __cpu_name[cpu] = "RM7000";
 508                 c->isa_level = MIPS_CPU_ISA_IV;
 509                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 510                              MIPS_CPU_LLSC;
 511                 /*
 512                  * Undocumented RM7000:  Bit 29 in the info register of
 513                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
 514                  * entries.
 515                  *
 516                  * 29      1 =>    64 entry JTLB
 517                  *         0 =>    48 entry JTLB
 518                  */
 519                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 520                 break;
 521         case PRID_IMP_RM9000:
 522                 c->cputype = CPU_RM9000;
 523                 __cpu_name[cpu] = "RM9000";
 524                 c->isa_level = MIPS_CPU_ISA_IV;
 525                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
 526                              MIPS_CPU_LLSC;
 527                 /*
 528                  * Bit 29 in the info register of the RM9000
 529                  * indicates if the TLB has 48 or 64 entries.
 530                  *
 531                  * 29      1 =>    64 entry JTLB
 532                  *         0 =>    48 entry JTLB
 533                  */
 534                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
 535                 break;
 536         case PRID_IMP_R8000:
 537                 c->cputype = CPU_R8000;
 538                 __cpu_name[cpu] = "RM8000";
 539                 c->isa_level = MIPS_CPU_ISA_IV;
 540                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
 541                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 542                              MIPS_CPU_LLSC;
 543                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
 544                 break;
 545         case PRID_IMP_R10000:
 546                 c->cputype = CPU_R10000;
 547                 __cpu_name[cpu] = "R10000";
 548                 c->isa_level = MIPS_CPU_ISA_IV;
 549                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 550                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 551                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 552                              MIPS_CPU_LLSC;
 553                 c->tlbsize = 64;
 554                 break;
 555         case PRID_IMP_R12000:
 556                 c->cputype = CPU_R12000;
 557                 __cpu_name[cpu] = "R12000";
 558                 c->isa_level = MIPS_CPU_ISA_IV;
 559                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 560                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 561                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 562                              MIPS_CPU_LLSC;
 563                 c->tlbsize = 64;
 564                 break;
 565         case PRID_IMP_R14000:
 566                 c->cputype = CPU_R14000;
 567                 __cpu_name[cpu] = "R14000";
 568                 c->isa_level = MIPS_CPU_ISA_IV;
 569                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
 570                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
 571                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
 572                              MIPS_CPU_LLSC;
 573                 c->tlbsize = 64;
 574                 break;
 575         case PRID_IMP_LOONGSON2:
 576                 c->cputype = CPU_LOONGSON2;
 577                 __cpu_name[cpu] = "ICT Loongson-2";
 578                 c->isa_level = MIPS_CPU_ISA_III;
 579                 c->options = R4K_OPTS |
 580                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
 581                              MIPS_CPU_32FPR;
 582                 c->tlbsize = 64;
 583                 break;
 584         }
 585 }
 586
 587 static char unknown_isa[] __cpuinitdata = KERN_ERR \
 588         "Unsupported ISA type, c0.config0: %d.";
 589
 590 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 591 {
 592         unsigned int config0;
 593         int isa;
 594
 595         config0 = read_c0_config();
 596
 597         if (((config0 & MIPS_CONF_MT) >> 7) == 1)
 598                 c->options |= MIPS_CPU_TLB;
 599         isa = (config0 & MIPS_CONF_AT) >> 13;
 600         switch (isa) {
 601         case 0:
 602                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 603                 case 0:
 604                         c->isa_level = MIPS_CPU_ISA_M32R1;
 605                         break;
 606                 case 1:
 607                         c->isa_level = MIPS_CPU_ISA_M32R2;
 608                         break;
 609                 default:
 610                         goto unknown;
 611                 }
 612                 break;
 613         case 2:
 614                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 615                 case 0:
 616                         c->isa_level = MIPS_CPU_ISA_M64R1;
 617                         break;
 618                 case 1:
 619                         c->isa_level = MIPS_CPU_ISA_M64R2;
 620                         break;
 621                 default:
 622                         goto unknown;
 623                 }
 624                 break;
 625         default:
 626                 goto unknown;
 627         }
 628
 629         return config0 & MIPS_CONF_M;
 630
 631 unknown:
 632         panic(unknown_isa, config0);
 633 }
 634
 635 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 636 {
 637         unsigned int config1;
 638
 639         config1 = read_c0_config1();
 640
 641         if (config1 & MIPS_CONF1_MD)
 642                 c->ases |= MIPS_ASE_MDMX;
 643         if (config1 & MIPS_CONF1_WR)
 644                 c->options |= MIPS_CPU_WATCH;
 645         if (config1 & MIPS_CONF1_CA)
 646                 c->ases |= MIPS_ASE_MIPS16;
 647         if (config1 & MIPS_CONF1_EP)
 648                 c->options |= MIPS_CPU_EJTAG;
 649         if (config1 & MIPS_CONF1_FP) {
 650                 c->options |= MIPS_CPU_FPU;
 651                 c->options |= MIPS_CPU_32FPR;
 652         }
 653         if (cpu_has_tlb)
 654                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 655
 656         return config1 & MIPS_CONF_M;
 657 }
 658
 659 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 660 {
 661         unsigned int config2;
 662
 663         config2 = read_c0_config2();
 664
 665         if (config2 & MIPS_CONF2_SL)
 666                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 667
 668         return config2 & MIPS_CONF_M;
 669 }
 670
 671 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 672 {
 673         unsigned int config3;
 674
 675         config3 = read_c0_config3();
 676
 677         if (config3 & MIPS_CONF3_SM)
 678                 c->ases |= MIPS_ASE_SMARTMIPS;
 679         if (config3 & MIPS_CONF3_DSP)
 680                 c->ases |= MIPS_ASE_DSP;
 681         if (config3 & MIPS_CONF3_VINT)
 682                 c->options |= MIPS_CPU_VINT;
 683         if (config3 & MIPS_CONF3_VEIC)
 684                 c->options |= MIPS_CPU_VEIC;
 685         if (config3 & MIPS_CONF3_MT)
 686                 c->ases |= MIPS_ASE_MIPSMT;
 687         if (config3 & MIPS_CONF3_ULRI)
 688                 c->options |= MIPS_CPU_ULRI;
 689
 690         return config3 & MIPS_CONF_M;
 691 }
 692
 693 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
 694 {
 695         int ok;
 696
 697         /* MIPS32 or MIPS64 compliant CPU.  */
 698         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 699                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 700
 701         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 702
 703         ok = decode_config0(c);                 /* Read Config registers.  */
 704         BUG_ON(!ok);                            /* Arch spec violation!  */
 705         if (ok)
 706                 ok = decode_config1(c);
 707         if (ok)
 708                 ok = decode_config2(c);
 709         if (ok)
 710                 ok = decode_config3(c);
 711
 712         mips_probe_watch_registers(c);
 713 }
 714
 715 #ifdef CONFIG_CPU_MIPSR2
 716 extern void spram_config(void);
 717 #else
 718 static inline void spram_config(void) {}
 719 #endif
 720
 721 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
 722 {
 723         decode_configs(c);
 724         switch (c->processor_id & 0xff00) {
 725         case PRID_IMP_4KC:
 726                 c->cputype = CPU_4KC;
 727                 __cpu_name[cpu] = "MIPS 4Kc";
 728                 break;
 729         case PRID_IMP_4KEC:
 730                 c->cputype = CPU_4KEC;
 731                 __cpu_name[cpu] = "MIPS 4KEc";
 732                 break;
 733         case PRID_IMP_4KECR2:
 734                 c->cputype = CPU_4KEC;
 735                 __cpu_name[cpu] = "MIPS 4KEc";
 736                 break;
 737         case PRID_IMP_4KSC:
 738         case PRID_IMP_4KSD:
 739                 c->cputype = CPU_4KSC;
 740                 __cpu_name[cpu] = "MIPS 4KSc";
 741                 break;
 742         case PRID_IMP_5KC:
 743                 c->cputype = CPU_5KC;
 744                 __cpu_name[cpu] = "MIPS 5Kc";
 745                 break;
 746         case PRID_IMP_20KC:
 747                 c->cputype = CPU_20KC;
 748                 __cpu_name[cpu] = "MIPS 20Kc";
 749                 break;
 750         case PRID_IMP_24K:
 751         case PRID_IMP_24KE:
 752                 c->cputype = CPU_24K;
 753                 __cpu_name[cpu] = "MIPS 24Kc";
 754                 break;
 755         case PRID_IMP_25KF:
 756                 c->cputype = CPU_25KF;
 757                 __cpu_name[cpu] = "MIPS 25Kc";
 758                 break;
 759         case PRID_IMP_34K:
 760                 c->cputype = CPU_34K;
 761                 __cpu_name[cpu] = "MIPS 34Kc";
 762                 break;
 763         case PRID_IMP_74K:
 764                 c->cputype = CPU_74K;
 765                 __cpu_name[cpu] = "MIPS 74Kc";
 766                 break;
 767         case PRID_IMP_1004K:
 768                 c->cputype = CPU_1004K;
 769                 __cpu_name[cpu] = "MIPS 1004Kc";
 770                 break;
 771         }
 772
 773         spram_config();
 774 }
 775
 776 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
 777 {
 778         decode_configs(c);
 779         switch (c->processor_id & 0xff00) {
 780         case PRID_IMP_AU1_REV1:
 781         case PRID_IMP_AU1_REV2:
 782                 switch ((c->processor_id >> 24) & 0xff) {
 783                 case 0:
 784                         c->cputype = CPU_AU1000;
 785                         __cpu_name[cpu] = "Au1000";
 786                         break;
 787                 case 1:
 788                         c->cputype = CPU_AU1500;
 789                         __cpu_name[cpu] = "Au1500";
 790                         break;
 791                 case 2:
 792                         c->cputype = CPU_AU1100;
 793                         __cpu_name[cpu] = "Au1100";
 794                         break;
 795                 case 3:
 796                         c->cputype = CPU_AU1550;
 797                         __cpu_name[cpu] = "Au1550";
 798                         break;
 799                 case 4:
 800                         c->cputype = CPU_AU1200;
 801                         __cpu_name[cpu] = "Au1200";
 802                         if ((c->processor_id & 0xff) == 2) {
 803                                 c->cputype = CPU_AU1250;
 804                                 __cpu_name[cpu] = "Au1250";
 805                         }
 806                         break;
 807                 case 5:
 808                         c->cputype = CPU_AU1210;
 809                         __cpu_name[cpu] = "Au1210";
 810                         break;
 811                 default:
 812                         panic("Unknown Au Core!");
 813                         break;
 814                 }
 815                 break;
 816         }
 817 }
 818
 819 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
 820 {
 821         decode_configs(c);
 822
 823         switch (c->processor_id & 0xff00) {
 824         case PRID_IMP_SB1:
 825                 c->cputype = CPU_SB1;
 826                 __cpu_name[cpu] = "SiByte SB1";
 827                 /* FPU in pass1 is known to have issues. */
 828                 if ((c->processor_id & 0xff) < 0x02)
 829                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 830                 break;
 831         case PRID_IMP_SB1A:
 832                 c->cputype = CPU_SB1A;
 833                 __cpu_name[cpu] = "SiByte SB1A";
 834                 break;
 835         }
 836 }
 837
 838 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
 839 {
 840         decode_configs(c);
 841         switch (c->processor_id & 0xff00) {
 842         case PRID_IMP_SR71000:
 843                 c->cputype = CPU_SR71000;
 844                 __cpu_name[cpu] = "Sandcraft SR71000";
 845                 c->scache.ways = 8;
 846                 c->tlbsize = 64;
 847                 break;
 848         }
 849 }
 850
 851 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
 852 {
 853         decode_configs(c);
 854         switch (c->processor_id & 0xff00) {
 855         case PRID_IMP_PR4450:
 856                 c->cputype = CPU_PR4450;
 857                 __cpu_name[cpu] = "Philips PR4450";
 858                 c->isa_level = MIPS_CPU_ISA_M32R1;
 859                 break;
 860         }
 861 }
 862
 863 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
 864 {
 865         decode_configs(c);
 866         switch (c->processor_id & 0xff00) {
 867         case PRID_IMP_BCM3302:
 868                 c->cputype = CPU_BCM3302;
 869                 __cpu_name[cpu] = "Broadcom BCM3302";
 870                 break;
 871         case PRID_IMP_BCM4710:
 872                 c->cputype = CPU_BCM4710;
 873                 __cpu_name[cpu] = "Broadcom BCM4710";
 874                 break;
 875         }
 876 }
 877
 878 const char *__cpu_name[NR_CPUS];
 879
 880 __cpuinit void cpu_probe(void)
 881 {
 882         struct cpuinfo_mips *c = &current_cpu_data;
 883         unsigned int cpu = smp_processor_id();
 884
 885         c->processor_id = PRID_IMP_UNKNOWN;
 886         c->fpu_id       = FPIR_IMP_NONE;
 887         c->cputype      = CPU_UNKNOWN;
 888
 889         c->processor_id = read_c0_prid();
 890         switch (c->processor_id & 0xff0000) {
 891         case PRID_COMP_LEGACY:
 892                 cpu_probe_legacy(c, cpu);
 893                 break;
 894         case PRID_COMP_MIPS:
 895                 cpu_probe_mips(c, cpu);
 896                 break;
 897         case PRID_COMP_ALCHEMY:
 898                 cpu_probe_alchemy(c, cpu);
 899                 break;
 900         case PRID_COMP_SIBYTE:
 901                 cpu_probe_sibyte(c, cpu);
 902                 break;
 903         case PRID_COMP_BROADCOM:
 904                 cpu_probe_broadcom(c, cpu);
 905                 break;
 906         case PRID_COMP_SANDCRAFT:
 907                 cpu_probe_sandcraft(c, cpu);
 908                 break;
 909         case PRID_COMP_NXP:
 910                 cpu_probe_nxp(c, cpu);
 911                 break;
 912         }
 913
 914         BUG_ON(!__cpu_name[cpu]);
 915         BUG_ON(c->cputype == CPU_UNKNOWN);
 916
 917         /*
 918          * Platform code can force the cpu type to optimize code
 919          * generation. In that case be sure the cpu type is correctly
 920          * manually setup otherwise it could trigger some nasty bugs.
 921          */
 922         BUG_ON(current_cpu_type() != c->cputype);
 923
 924         if (c->options & MIPS_CPU_FPU) {
 925                 c->fpu_id = cpu_get_fpu_id();
 926
 927                 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
 928                     c->isa_level == MIPS_CPU_ISA_M32R2 ||
 929                     c->isa_level == MIPS_CPU_ISA_M64R1 ||
 930                     c->isa_level == MIPS_CPU_ISA_M64R2) {
 931                         if (c->fpu_id & MIPS_FPIR_3D)
 932                                 c->ases |= MIPS_ASE_MIPS3D;
 933                 }
 934         }
 935
 936         if (cpu_has_mips_r2)
 937                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
 938         else
 939                 c->srsets = 1;
 940 }
 941
 942 __cpuinit void cpu_report(void)
 943 {
 944         struct cpuinfo_mips *c = &current_cpu_data;
 945
 946         printk(KERN_INFO "CPU revision is: %08x (%s)\n",
 947                c->processor_id, cpu_name_string());
 948         if (c->options & MIPS_CPU_FPU)
 949                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
 950 }