1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Processor capabilities determination functions.
5 * Copyright (C) xxxx the Anonymous
6 * Copyright (C) 1994 - 2006 Ralf Baechle
7 * Copyright (C) 2003, 2004 Maciej W. Rozycki
8 * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
10 #include <linux/init.h>
11 #include <linux/kernel.h>
12 #include <linux/ptrace.h>
13 #include <linux/smp.h>
14 #include <linux/stddef.h>
15 #include <linux/export.h>
19 #include <asm/cpu-features.h>
20 #include <asm/cpu-type.h>
22 #include <asm/mipsregs.h>
23 #include <asm/mipsmtregs.h>
25 #include <asm/watch.h>
27 #include <asm/pgtable-bits.h>
28 #include <asm/spram.h>
29 #include <linux/uaccess.h>
31 /* Hardware capabilities */
32 unsigned int elf_hwcap __read_mostly;
33 EXPORT_SYMBOL_GPL(elf_hwcap);
35 #ifdef CONFIG_MIPS_FP_SUPPORT
38 * Get the FPU Implementation/Revision.
40 static inline unsigned long cpu_get_fpu_id(void)
42 unsigned long tmp, fpu_id;
44 tmp = read_c0_status();
45 __enable_fpu(FPU_AS_IS);
46 fpu_id = read_32bit_cp1_register(CP1_REVISION);
52 * Check if the CPU has an external FPU.
54 static inline int __cpu_has_fpu(void)
56 return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
60 * Determine the FCSR mask for FPU hardware.
62 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
64 unsigned long sr, mask, fcsr, fcsr0, fcsr1;
67 mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
69 sr = read_c0_status();
70 __enable_fpu(FPU_AS_IS);
73 write_32bit_cp1_register(CP1_STATUS, fcsr0);
74 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
77 write_32bit_cp1_register(CP1_STATUS, fcsr1);
78 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
80 write_32bit_cp1_register(CP1_STATUS, fcsr);
84 c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
88 * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
89 * supported by FPU hardware.
91 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
93 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
94 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
95 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
96 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
98 sr = read_c0_status();
99 __enable_fpu(FPU_AS_IS);
101 fir = read_32bit_cp1_register(CP1_REVISION);
102 if (fir & MIPS_FPIR_HAS2008) {
103 fcsr = read_32bit_cp1_register(CP1_STATUS);
105 fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
106 write_32bit_cp1_register(CP1_STATUS, fcsr0);
107 fcsr0 = read_32bit_cp1_register(CP1_STATUS);
109 fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
110 write_32bit_cp1_register(CP1_STATUS, fcsr1);
111 fcsr1 = read_32bit_cp1_register(CP1_STATUS);
113 write_32bit_cp1_register(CP1_STATUS, fcsr);
115 if (!(fcsr0 & FPU_CSR_NAN2008))
116 c->options |= MIPS_CPU_NAN_LEGACY;
117 if (fcsr1 & FPU_CSR_NAN2008)
118 c->options |= MIPS_CPU_NAN_2008;
120 if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
121 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
123 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
125 if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
126 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
128 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
130 c->options |= MIPS_CPU_NAN_LEGACY;
135 c->options |= MIPS_CPU_NAN_LEGACY;
140 * IEEE 754 conformance mode to use. Affects the NaN encoding and the
141 * ABS.fmt/NEG.fmt execution mode.
143 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
146 * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
147 * to support by the FPU emulator according to the IEEE 754 conformance
148 * mode selected. Note that "relaxed" straps the emulator so that it
149 * allows 2008-NaN binaries even for legacy processors.
151 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
153 c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
154 c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
155 c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
159 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
160 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
161 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
162 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
164 c->options |= MIPS_CPU_NAN_LEGACY;
165 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
169 c->options |= MIPS_CPU_NAN_LEGACY;
170 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
173 c->options |= MIPS_CPU_NAN_2008;
174 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
175 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
178 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
184 * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
185 * according to the "ieee754=" parameter.
187 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
191 mips_use_nan_legacy = !!cpu_has_nan_legacy;
192 mips_use_nan_2008 = !!cpu_has_nan_2008;
195 mips_use_nan_legacy = !!cpu_has_nan_legacy;
196 mips_use_nan_2008 = !cpu_has_nan_legacy;
199 mips_use_nan_legacy = !cpu_has_nan_2008;
200 mips_use_nan_2008 = !!cpu_has_nan_2008;
203 mips_use_nan_legacy = true;
204 mips_use_nan_2008 = true;
210 * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
213 * strict: accept binaries that request a NaN encoding supported by the FPU
214 * legacy: only accept legacy-NaN binaries
215 * 2008: only accept 2008-NaN binaries
216 * relaxed: accept any binaries regardless of whether supported by the FPU
218 static int __init ieee754_setup(char *s)
222 else if (!strcmp(s, "strict"))
224 else if (!strcmp(s, "legacy"))
226 else if (!strcmp(s, "2008"))
228 else if (!strcmp(s, "relaxed"))
233 if (!(boot_cpu_data.options & MIPS_CPU_FPU))
234 cpu_set_nofpu_2008(&boot_cpu_data);
235 cpu_set_nan_2008(&boot_cpu_data);
240 early_param("ieee754", ieee754_setup);
243 * Set the FIR feature flags for the FPU emulator.
245 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
250 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
251 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
252 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
253 value |= MIPS_FPIR_D | MIPS_FPIR_S;
254 if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
255 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
256 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
257 if (c->options & MIPS_CPU_NAN_2008)
258 value |= MIPS_FPIR_HAS2008;
262 /* Determined FPU emulator mask to use for the boot CPU with "nofpu". */
263 static unsigned int mips_nofpu_msk31;
266 * Set options for FPU hardware.
268 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
270 c->fpu_id = cpu_get_fpu_id();
271 mips_nofpu_msk31 = c->fpu_msk31;
273 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
274 MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
275 MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
276 if (c->fpu_id & MIPS_FPIR_3D)
277 c->ases |= MIPS_ASE_MIPS3D;
278 if (c->fpu_id & MIPS_FPIR_UFRP)
279 c->options |= MIPS_CPU_UFR;
280 if (c->fpu_id & MIPS_FPIR_FREP)
281 c->options |= MIPS_CPU_FRE;
284 cpu_set_fpu_fcsr_mask(c);
290 * Set options for the FPU emulator.
292 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
294 c->options &= ~MIPS_CPU_FPU;
295 c->fpu_msk31 = mips_nofpu_msk31;
297 cpu_set_nofpu_2008(c);
302 static int mips_fpu_disabled;
304 static int __init fpu_disable(char *s)
306 cpu_set_nofpu_opts(&boot_cpu_data);
307 mips_fpu_disabled = 1;
312 __setup("nofpu", fpu_disable);
314 #else /* !CONFIG_MIPS_FP_SUPPORT */
316 #define mips_fpu_disabled 1
318 static inline unsigned long cpu_get_fpu_id(void)
320 return FPIR_IMP_NONE;
323 static inline int __cpu_has_fpu(void)
328 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
333 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
338 #endif /* CONFIG_MIPS_FP_SUPPORT */
340 static inline unsigned long cpu_get_msa_id(void)
342 unsigned long status, msa_id;
344 status = read_c0_status();
345 __enable_fpu(FPU_64BIT);
347 msa_id = read_msa_ir();
349 write_c0_status(status);
353 static int mips_dsp_disabled;
355 static int __init dsp_disable(char *s)
357 cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
358 mips_dsp_disabled = 1;
363 __setup("nodsp", dsp_disable);
365 static int mips_htw_disabled;
367 static int __init htw_disable(char *s)
369 mips_htw_disabled = 1;
370 cpu_data[0].options &= ~MIPS_CPU_HTW;
371 write_c0_pwctl(read_c0_pwctl() &
372 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
377 __setup("nohtw", htw_disable);
379 static int mips_ftlb_disabled;
380 static int mips_has_ftlb_configured;
384 FTLB_SET_PROB = 1 << 1,
387 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
389 static int __init ftlb_disable(char *s)
391 unsigned int config4, mmuextdef;
394 * If the core hasn't done any FTLB configuration, there is nothing
397 if (!mips_has_ftlb_configured)
400 /* Disable it in the boot cpu */
401 if (set_ftlb_enable(&cpu_data[0], 0)) {
402 pr_warn("Can't turn FTLB off\n");
406 config4 = read_c0_config4();
408 /* Check that FTLB has been disabled */
409 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
410 /* MMUSIZEEXT == VTLB ON, FTLB OFF */
411 if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
412 /* This should never happen */
413 pr_warn("FTLB could not be disabled!\n");
417 mips_ftlb_disabled = 1;
418 mips_has_ftlb_configured = 0;
421 * noftlb is mainly used for debug purposes so print
422 * an informative message instead of using pr_debug()
424 pr_info("FTLB has been disabled\n");
427 * Some of these bits are duplicated in the decode_config4.
428 * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
429 * once FTLB has been disabled so undo what decode_config4 did.
431 cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
432 cpu_data[0].tlbsizeftlbsets;
433 cpu_data[0].tlbsizeftlbsets = 0;
434 cpu_data[0].tlbsizeftlbways = 0;
439 __setup("noftlb", ftlb_disable);
442 * Check if the CPU has per tc perf counters
444 static inline void cpu_set_mt_per_tc_perf(struct cpuinfo_mips *c)
446 if (read_c0_config7() & MTI_CONF7_PTC)
447 c->options |= MIPS_CPU_MT_PER_TC_PERF_COUNTERS;
450 static inline void check_errata(void)
452 struct cpuinfo_mips *c = ¤t_cpu_data;
454 switch (current_cpu_type()) {
457 * Erratum "RPS May Cause Incorrect Instruction Execution"
458 * This code only handles VPE0, any SMP/RTOS code
459 * making use of VPE1 will be responsable for that VPE.
461 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
462 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
469 void __init check_bugs32(void)
475 * Probe whether cpu has config register by trying to play with
476 * alternate cache bit and see whether it matters.
477 * It's used by cpu_probe to distinguish between R3000A and R3081.
479 static inline int cpu_has_confreg(void)
481 #ifdef CONFIG_CPU_R3000
482 extern unsigned long r3k_cache_size(unsigned long);
483 unsigned long size1, size2;
484 unsigned long cfg = read_c0_conf();
486 size1 = r3k_cache_size(ST0_ISC);
487 write_c0_conf(cfg ^ R30XX_CONF_AC);
488 size2 = r3k_cache_size(ST0_ISC);
490 return size1 != size2;
496 static inline void set_elf_platform(int cpu, const char *plat)
499 __elf_platform = plat;
502 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
504 #ifdef __NEED_VMBITS_PROBE
505 write_c0_entryhi(0x3fffffffffffe000ULL);
506 back_to_back_c0_hazard();
507 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
511 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
514 case MIPS_CPU_ISA_M64R2:
515 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
517 case MIPS_CPU_ISA_M64R1:
518 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
521 c->isa_level |= MIPS_CPU_ISA_V;
523 case MIPS_CPU_ISA_IV:
524 c->isa_level |= MIPS_CPU_ISA_IV;
526 case MIPS_CPU_ISA_III:
527 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
530 /* R6 incompatible with everything else */
531 case MIPS_CPU_ISA_M64R6:
532 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
534 case MIPS_CPU_ISA_M32R6:
535 c->isa_level |= MIPS_CPU_ISA_M32R6;
536 /* Break here so we don't add incompatible ISAs */
538 case MIPS_CPU_ISA_M32R2:
539 c->isa_level |= MIPS_CPU_ISA_M32R2;
541 case MIPS_CPU_ISA_M32R1:
542 c->isa_level |= MIPS_CPU_ISA_M32R1;
544 case MIPS_CPU_ISA_II:
545 c->isa_level |= MIPS_CPU_ISA_II;
550 static char unknown_isa[] = KERN_ERR \
551 "Unsupported ISA type, c0.config0: %d.";
553 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
556 unsigned int probability = c->tlbsize / c->tlbsizevtlb;
559 * 0 = All TLBWR instructions go to FTLB
560 * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
561 * FTLB and 1 goes to the VTLB.
562 * 2 = 7:1: As above with 7:1 ratio.
563 * 3 = 3:1: As above with 3:1 ratio.
565 * Use the linear midpoint as the probability threshold.
567 if (probability >= 12)
569 else if (probability >= 6)
573 * So FTLB is less than 4 times bigger than VTLB.
574 * A 3:1 ratio can still be useful though.
579 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
583 /* It's implementation dependent how the FTLB can be enabled */
584 switch (c->cputype) {
588 /* proAptiv & related cores use Config6 to enable the FTLB */
589 config = read_c0_config6();
592 config |= MIPS_CONF6_FTLBEN;
594 config &= ~MIPS_CONF6_FTLBEN;
596 if (flags & FTLB_SET_PROB) {
597 config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
598 config |= calculate_ftlb_probability(c)
599 << MIPS_CONF6_FTLBP_SHIFT;
602 write_c0_config6(config);
603 back_to_back_c0_hazard();
607 /* There's no way to disable the FTLB */
608 if (!(flags & FTLB_EN))
612 /* Flush ITLB, DTLB, VTLB and FTLB */
613 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
614 LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
615 /* Loongson-3 cores use Config6 to enable the FTLB */
616 config = read_c0_config6();
619 write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
622 write_c0_config6(config | MIPS_CONF6_FTLBDIS);
631 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
633 unsigned int config0;
636 config0 = read_c0_config();
639 * Look for Standard TLB or Dual VTLB and FTLB
641 mt = config0 & MIPS_CONF_MT;
642 if (mt == MIPS_CONF_MT_TLB)
643 c->options |= MIPS_CPU_TLB;
644 else if (mt == MIPS_CONF_MT_FTLB)
645 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
647 isa = (config0 & MIPS_CONF_AT) >> 13;
650 switch ((config0 & MIPS_CONF_AR) >> 10) {
652 set_isa(c, MIPS_CPU_ISA_M32R1);
655 set_isa(c, MIPS_CPU_ISA_M32R2);
658 set_isa(c, MIPS_CPU_ISA_M32R6);
665 switch ((config0 & MIPS_CONF_AR) >> 10) {
667 set_isa(c, MIPS_CPU_ISA_M64R1);
670 set_isa(c, MIPS_CPU_ISA_M64R2);
673 set_isa(c, MIPS_CPU_ISA_M64R6);
683 return config0 & MIPS_CONF_M;
686 panic(unknown_isa, config0);
689 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
691 unsigned int config1;
693 config1 = read_c0_config1();
695 if (config1 & MIPS_CONF1_MD)
696 c->ases |= MIPS_ASE_MDMX;
697 if (config1 & MIPS_CONF1_PC)
698 c->options |= MIPS_CPU_PERF;
699 if (config1 & MIPS_CONF1_WR)
700 c->options |= MIPS_CPU_WATCH;
701 if (config1 & MIPS_CONF1_CA)
702 c->ases |= MIPS_ASE_MIPS16;
703 if (config1 & MIPS_CONF1_EP)
704 c->options |= MIPS_CPU_EJTAG;
705 if (config1 & MIPS_CONF1_FP) {
706 c->options |= MIPS_CPU_FPU;
707 c->options |= MIPS_CPU_32FPR;
710 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
711 c->tlbsizevtlb = c->tlbsize;
712 c->tlbsizeftlbsets = 0;
715 return config1 & MIPS_CONF_M;
718 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
720 unsigned int config2;
722 config2 = read_c0_config2();
724 if (config2 & MIPS_CONF2_SL)
725 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
727 return config2 & MIPS_CONF_M;
730 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
732 unsigned int config3;
734 config3 = read_c0_config3();
736 if (config3 & MIPS_CONF3_SM) {
737 c->ases |= MIPS_ASE_SMARTMIPS;
738 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
740 if (config3 & MIPS_CONF3_RXI)
741 c->options |= MIPS_CPU_RIXI;
742 if (config3 & MIPS_CONF3_CTXTC)
743 c->options |= MIPS_CPU_CTXTC;
744 if (config3 & MIPS_CONF3_DSP)
745 c->ases |= MIPS_ASE_DSP;
746 if (config3 & MIPS_CONF3_DSP2P) {
747 c->ases |= MIPS_ASE_DSP2P;
749 c->ases |= MIPS_ASE_DSP3;
751 if (config3 & MIPS_CONF3_VINT)
752 c->options |= MIPS_CPU_VINT;
753 if (config3 & MIPS_CONF3_VEIC)
754 c->options |= MIPS_CPU_VEIC;
755 if (config3 & MIPS_CONF3_LPA)
756 c->options |= MIPS_CPU_LPA;
757 if (config3 & MIPS_CONF3_MT)
758 c->ases |= MIPS_ASE_MIPSMT;
759 if (config3 & MIPS_CONF3_ULRI)
760 c->options |= MIPS_CPU_ULRI;
761 if (config3 & MIPS_CONF3_ISA)
762 c->options |= MIPS_CPU_MICROMIPS;
763 if (config3 & MIPS_CONF3_VZ)
764 c->ases |= MIPS_ASE_VZ;
765 if (config3 & MIPS_CONF3_SC)
766 c->options |= MIPS_CPU_SEGMENTS;
767 if (config3 & MIPS_CONF3_BI)
768 c->options |= MIPS_CPU_BADINSTR;
769 if (config3 & MIPS_CONF3_BP)
770 c->options |= MIPS_CPU_BADINSTRP;
771 if (config3 & MIPS_CONF3_MSA)
772 c->ases |= MIPS_ASE_MSA;
773 if (config3 & MIPS_CONF3_PW) {
775 c->options |= MIPS_CPU_HTW;
777 if (config3 & MIPS_CONF3_CDMM)
778 c->options |= MIPS_CPU_CDMM;
779 if (config3 & MIPS_CONF3_SP)
780 c->options |= MIPS_CPU_SP;
782 return config3 & MIPS_CONF_M;
785 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
787 unsigned int config4;
789 unsigned int mmuextdef;
790 unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
791 unsigned long asid_mask;
793 config4 = read_c0_config4();
796 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
797 c->options |= MIPS_CPU_TLBINV;
800 * R6 has dropped the MMUExtDef field from config4.
801 * On R6 the fields always describe the FTLB, and only if it is
802 * present according to Config.MT.
804 if (!cpu_has_mips_r6)
805 mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
806 else if (cpu_has_ftlb)
807 mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
812 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
813 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
814 c->tlbsizevtlb = c->tlbsize;
816 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
818 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
819 MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
820 c->tlbsize = c->tlbsizevtlb;
821 ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
823 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
824 if (mips_ftlb_disabled)
826 newcf4 = (config4 & ~ftlb_page) |
827 (page_size_ftlb(mmuextdef) <<
828 MIPS_CONF4_FTLBPAGESIZE_SHIFT);
829 write_c0_config4(newcf4);
830 back_to_back_c0_hazard();
831 config4 = read_c0_config4();
832 if (config4 != newcf4) {
833 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
835 /* Switch FTLB off */
836 set_ftlb_enable(c, 0);
837 mips_ftlb_disabled = 1;
840 c->tlbsizeftlbsets = 1 <<
841 ((config4 & MIPS_CONF4_FTLBSETS) >>
842 MIPS_CONF4_FTLBSETS_SHIFT);
843 c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
844 MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
845 c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
846 mips_has_ftlb_configured = 1;
851 c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
852 >> MIPS_CONF4_KSCREXIST_SHIFT;
854 asid_mask = MIPS_ENTRYHI_ASID;
855 if (config4 & MIPS_CONF4_AE)
856 asid_mask |= MIPS_ENTRYHI_ASIDX;
857 set_cpu_asid_mask(c, asid_mask);
860 * Warn if the computed ASID mask doesn't match the mask the kernel
861 * is built for. This may indicate either a serious problem or an
862 * easy optimisation opportunity, but either way should be addressed.
864 WARN_ON(asid_mask != cpu_asid_mask(c));
866 return config4 & MIPS_CONF_M;
869 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
871 unsigned int config5, max_mmid_width;
872 unsigned long asid_mask;
874 config5 = read_c0_config5();
875 config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
877 if (cpu_has_mips_r6) {
878 if (!__builtin_constant_p(cpu_has_mmid) || cpu_has_mmid)
879 config5 |= MIPS_CONF5_MI;
881 config5 &= ~MIPS_CONF5_MI;
884 write_c0_config5(config5);
886 if (config5 & MIPS_CONF5_EVA)
887 c->options |= MIPS_CPU_EVA;
888 if (config5 & MIPS_CONF5_MRP)
889 c->options |= MIPS_CPU_MAAR;
890 if (config5 & MIPS_CONF5_LLB)
891 c->options |= MIPS_CPU_RW_LLB;
892 if (config5 & MIPS_CONF5_MVH)
893 c->options |= MIPS_CPU_MVH;
894 if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
895 c->options |= MIPS_CPU_VP;
896 if (config5 & MIPS_CONF5_CA2)
897 c->ases |= MIPS_ASE_MIPS16E2;
899 if (config5 & MIPS_CONF5_CRCP)
900 elf_hwcap |= HWCAP_MIPS_CRC32;
902 if (cpu_has_mips_r6) {
903 /* Ensure the write to config5 above takes effect */
904 back_to_back_c0_hazard();
906 /* Check whether we successfully enabled MMID support */
907 config5 = read_c0_config5();
908 if (config5 & MIPS_CONF5_MI)
909 c->options |= MIPS_CPU_MMID;
912 * Warn if we've hardcoded cpu_has_mmid to a value unsuitable
913 * for the CPU we're running on, or if CPUs in an SMP system
914 * have inconsistent MMID support.
916 WARN_ON(!!cpu_has_mmid != !!(config5 & MIPS_CONF5_MI));
919 write_c0_memorymapid(~0ul);
920 back_to_back_c0_hazard();
921 asid_mask = read_c0_memorymapid();
924 * We maintain a bitmap to track MMID allocation, and
925 * need a sensible upper bound on the size of that
926 * bitmap. The initial CPU with MMID support (I6500)
927 * supports 16 bit MMIDs, which gives us an 8KiB
928 * bitmap. The architecture recommends that hardware
929 * support 32 bit MMIDs, which would give us a 512MiB
930 * bitmap - that's too big in most cases.
932 * Cap MMID width at 16 bits for now & we can revisit
933 * this if & when hardware supports anything wider.
936 if (asid_mask > GENMASK(max_mmid_width - 1, 0)) {
937 pr_info("Capping MMID width at %d bits",
939 asid_mask = GENMASK(max_mmid_width - 1, 0);
942 set_cpu_asid_mask(c, asid_mask);
946 return config5 & MIPS_CONF_M;
949 static void decode_configs(struct cpuinfo_mips *c)
953 /* MIPS32 or MIPS64 compliant CPU. */
954 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
955 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
957 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
959 /* Enable FTLB if present and not disabled */
960 set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
962 ok = decode_config0(c); /* Read Config registers. */
963 BUG_ON(!ok); /* Arch spec violation! */
965 ok = decode_config1(c);
967 ok = decode_config2(c);
969 ok = decode_config3(c);
971 ok = decode_config4(c);
973 ok = decode_config5(c);
975 /* Probe the EBase.WG bit */
976 if (cpu_has_mips_r2_r6) {
980 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
981 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
982 : (s32)read_c0_ebase();
983 if (ebase & MIPS_EBASE_WG) {
984 /* WG bit already set, we can avoid the clumsy probe */
985 c->options |= MIPS_CPU_EBASE_WG;
987 /* Its UNDEFINED to change EBase while BEV=0 */
988 status = read_c0_status();
989 write_c0_status(status | ST0_BEV);
992 * On pre-r6 cores, this may well clobber the upper bits
993 * of EBase. This is hard to avoid without potentially
994 * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
996 if (cpu_has_mips64r6)
997 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
999 write_c0_ebase(ebase | MIPS_EBASE_WG);
1000 back_to_back_c0_hazard();
1002 write_c0_status(status);
1003 if (read_c0_ebase() & MIPS_EBASE_WG) {
1004 c->options |= MIPS_CPU_EBASE_WG;
1005 write_c0_ebase(ebase);
1010 /* configure the FTLB write probability */
1011 set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
1013 mips_probe_watch_registers(c);
1015 #ifndef CONFIG_MIPS_CPS
1016 if (cpu_has_mips_r2_r6) {
1019 core = get_ebase_cpunum();
1021 core >>= fls(core_nvpes()) - 1;
1022 cpu_set_core(c, core);
1028 * Probe for certain guest capabilities by writing config bits and reading back.
1029 * Finally write back the original value.
1031 #define probe_gc0_config(name, maxconf, bits) \
1034 tmp = read_gc0_##name(); \
1035 write_gc0_##name(tmp | (bits)); \
1036 back_to_back_c0_hazard(); \
1037 maxconf = read_gc0_##name(); \
1038 write_gc0_##name(tmp); \
1042 * Probe for dynamic guest capabilities by changing certain config bits and
1043 * reading back to see if they change. Finally write back the original value.
1045 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits) \
1047 maxconf = read_gc0_##name(); \
1048 write_gc0_##name(maxconf ^ (bits)); \
1049 back_to_back_c0_hazard(); \
1050 dynconf = maxconf ^ read_gc0_##name(); \
1051 write_gc0_##name(maxconf); \
1052 maxconf |= dynconf; \
1055 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
1057 unsigned int config0;
1059 probe_gc0_config(config, config0, MIPS_CONF_M);
1061 if (config0 & MIPS_CONF_M)
1062 c->guest.conf |= BIT(1);
1063 return config0 & MIPS_CONF_M;
1066 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
1068 unsigned int config1, config1_dyn;
1070 probe_gc0_config_dyn(config1, config1, config1_dyn,
1071 MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
1074 if (config1 & MIPS_CONF1_FP)
1075 c->guest.options |= MIPS_CPU_FPU;
1076 if (config1_dyn & MIPS_CONF1_FP)
1077 c->guest.options_dyn |= MIPS_CPU_FPU;
1079 if (config1 & MIPS_CONF1_WR)
1080 c->guest.options |= MIPS_CPU_WATCH;
1081 if (config1_dyn & MIPS_CONF1_WR)
1082 c->guest.options_dyn |= MIPS_CPU_WATCH;
1084 if (config1 & MIPS_CONF1_PC)
1085 c->guest.options |= MIPS_CPU_PERF;
1086 if (config1_dyn & MIPS_CONF1_PC)
1087 c->guest.options_dyn |= MIPS_CPU_PERF;
1089 if (config1 & MIPS_CONF_M)
1090 c->guest.conf |= BIT(2);
1091 return config1 & MIPS_CONF_M;
1094 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
1096 unsigned int config2;
1098 probe_gc0_config(config2, config2, MIPS_CONF_M);
1100 if (config2 & MIPS_CONF_M)
1101 c->guest.conf |= BIT(3);
1102 return config2 & MIPS_CONF_M;
1105 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1107 unsigned int config3, config3_dyn;
1109 probe_gc0_config_dyn(config3, config3, config3_dyn,
1110 MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1113 if (config3 & MIPS_CONF3_CTXTC)
1114 c->guest.options |= MIPS_CPU_CTXTC;
1115 if (config3_dyn & MIPS_CONF3_CTXTC)
1116 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1118 if (config3 & MIPS_CONF3_PW)
1119 c->guest.options |= MIPS_CPU_HTW;
1121 if (config3 & MIPS_CONF3_ULRI)
1122 c->guest.options |= MIPS_CPU_ULRI;
1124 if (config3 & MIPS_CONF3_SC)
1125 c->guest.options |= MIPS_CPU_SEGMENTS;
1127 if (config3 & MIPS_CONF3_BI)
1128 c->guest.options |= MIPS_CPU_BADINSTR;
1129 if (config3 & MIPS_CONF3_BP)
1130 c->guest.options |= MIPS_CPU_BADINSTRP;
1132 if (config3 & MIPS_CONF3_MSA)
1133 c->guest.ases |= MIPS_ASE_MSA;
1134 if (config3_dyn & MIPS_CONF3_MSA)
1135 c->guest.ases_dyn |= MIPS_ASE_MSA;
1137 if (config3 & MIPS_CONF_M)
1138 c->guest.conf |= BIT(4);
1139 return config3 & MIPS_CONF_M;
1142 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1144 unsigned int config4;
1146 probe_gc0_config(config4, config4,
1147 MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1149 c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1150 >> MIPS_CONF4_KSCREXIST_SHIFT;
1152 if (config4 & MIPS_CONF_M)
1153 c->guest.conf |= BIT(5);
1154 return config4 & MIPS_CONF_M;
1157 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1159 unsigned int config5, config5_dyn;
1161 probe_gc0_config_dyn(config5, config5, config5_dyn,
1162 MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1164 if (config5 & MIPS_CONF5_MRP)
1165 c->guest.options |= MIPS_CPU_MAAR;
1166 if (config5_dyn & MIPS_CONF5_MRP)
1167 c->guest.options_dyn |= MIPS_CPU_MAAR;
1169 if (config5 & MIPS_CONF5_LLB)
1170 c->guest.options |= MIPS_CPU_RW_LLB;
1172 if (config5 & MIPS_CONF5_MVH)
1173 c->guest.options |= MIPS_CPU_MVH;
1175 if (config5 & MIPS_CONF_M)
1176 c->guest.conf |= BIT(6);
1177 return config5 & MIPS_CONF_M;
1180 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1184 ok = decode_guest_config0(c);
1186 ok = decode_guest_config1(c);
1188 ok = decode_guest_config2(c);
1190 ok = decode_guest_config3(c);
1192 ok = decode_guest_config4(c);
1194 decode_guest_config5(c);
1197 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1199 unsigned int guestctl0, temp;
1201 guestctl0 = read_c0_guestctl0();
1203 if (guestctl0 & MIPS_GCTL0_G0E)
1204 c->options |= MIPS_CPU_GUESTCTL0EXT;
1205 if (guestctl0 & MIPS_GCTL0_G1)
1206 c->options |= MIPS_CPU_GUESTCTL1;
1207 if (guestctl0 & MIPS_GCTL0_G2)
1208 c->options |= MIPS_CPU_GUESTCTL2;
1209 if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1210 c->options |= MIPS_CPU_GUESTID;
1213 * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1214 * first, otherwise all data accesses will be fully virtualised
1215 * as if they were performed by guest mode.
1217 write_c0_guestctl1(0);
1220 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1221 back_to_back_c0_hazard();
1222 temp = read_c0_guestctl0();
1224 if (temp & MIPS_GCTL0_DRG) {
1225 write_c0_guestctl0(guestctl0);
1226 c->options |= MIPS_CPU_DRG;
1231 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1233 if (cpu_has_guestid) {
1234 /* determine the number of bits of GuestID available */
1235 write_c0_guestctl1(MIPS_GCTL1_ID);
1236 back_to_back_c0_hazard();
1237 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1238 >> MIPS_GCTL1_ID_SHIFT;
1239 write_c0_guestctl1(0);
1243 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1245 /* determine the number of bits of GTOffset available */
1246 write_c0_gtoffset(0xffffffff);
1247 back_to_back_c0_hazard();
1248 c->gtoffset_mask = read_c0_gtoffset();
1249 write_c0_gtoffset(0);
1252 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1254 cpu_probe_guestctl0(c);
1255 if (cpu_has_guestctl1)
1256 cpu_probe_guestctl1(c);
1258 cpu_probe_gtoffset(c);
1260 decode_guest_configs(c);
1263 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1266 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1268 switch (c->processor_id & PRID_IMP_MASK) {
1269 case PRID_IMP_R2000:
1270 c->cputype = CPU_R2000;
1271 __cpu_name[cpu] = "R2000";
1272 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1273 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1275 if (__cpu_has_fpu())
1276 c->options |= MIPS_CPU_FPU;
1279 case PRID_IMP_R3000:
1280 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1281 if (cpu_has_confreg()) {
1282 c->cputype = CPU_R3081E;
1283 __cpu_name[cpu] = "R3081";
1285 c->cputype = CPU_R3000A;
1286 __cpu_name[cpu] = "R3000A";
1289 c->cputype = CPU_R3000;
1290 __cpu_name[cpu] = "R3000";
1292 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1293 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1295 if (__cpu_has_fpu())
1296 c->options |= MIPS_CPU_FPU;
1299 case PRID_IMP_R4000:
1300 if (read_c0_config() & CONF_SC) {
1301 if ((c->processor_id & PRID_REV_MASK) >=
1303 c->cputype = CPU_R4400PC;
1304 __cpu_name[cpu] = "R4400PC";
1306 c->cputype = CPU_R4000PC;
1307 __cpu_name[cpu] = "R4000PC";
1310 int cca = read_c0_config() & CONF_CM_CMASK;
1314 * SC and MC versions can't be reliably told apart,
1315 * but only the latter support coherent caching
1316 * modes so assume the firmware has set the KSEG0
1317 * coherency attribute reasonably (if uncached, we
1321 case CONF_CM_CACHABLE_CE:
1322 case CONF_CM_CACHABLE_COW:
1323 case CONF_CM_CACHABLE_CUW:
1330 if ((c->processor_id & PRID_REV_MASK) >=
1332 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1333 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1335 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1336 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1340 set_isa(c, MIPS_CPU_ISA_III);
1341 c->fpu_msk31 |= FPU_CSR_CONDX;
1342 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1343 MIPS_CPU_WATCH | MIPS_CPU_VCE |
1347 case PRID_IMP_VR41XX:
1348 set_isa(c, MIPS_CPU_ISA_III);
1349 c->fpu_msk31 |= FPU_CSR_CONDX;
1350 c->options = R4K_OPTS;
1352 switch (c->processor_id & 0xf0) {
1353 case PRID_REV_VR4111:
1354 c->cputype = CPU_VR4111;
1355 __cpu_name[cpu] = "NEC VR4111";
1357 case PRID_REV_VR4121:
1358 c->cputype = CPU_VR4121;
1359 __cpu_name[cpu] = "NEC VR4121";
1361 case PRID_REV_VR4122:
1362 if ((c->processor_id & 0xf) < 0x3) {
1363 c->cputype = CPU_VR4122;
1364 __cpu_name[cpu] = "NEC VR4122";
1366 c->cputype = CPU_VR4181A;
1367 __cpu_name[cpu] = "NEC VR4181A";
1370 case PRID_REV_VR4130:
1371 if ((c->processor_id & 0xf) < 0x4) {
1372 c->cputype = CPU_VR4131;
1373 __cpu_name[cpu] = "NEC VR4131";
1375 c->cputype = CPU_VR4133;
1376 c->options |= MIPS_CPU_LLSC;
1377 __cpu_name[cpu] = "NEC VR4133";
1381 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1382 c->cputype = CPU_VR41XX;
1383 __cpu_name[cpu] = "NEC Vr41xx";
1387 case PRID_IMP_R4600:
1388 c->cputype = CPU_R4600;
1389 __cpu_name[cpu] = "R4600";
1390 set_isa(c, MIPS_CPU_ISA_III);
1391 c->fpu_msk31 |= FPU_CSR_CONDX;
1392 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1397 case PRID_IMP_R4650:
1399 * This processor doesn't have an MMU, so it's not
1400 * "real easy" to run Linux on it. It is left purely
1401 * for documentation. Commented out because it shares
1402 * it's c0_prid id number with the TX3900.
1404 c->cputype = CPU_R4650;
1405 __cpu_name[cpu] = "R4650";
1406 set_isa(c, MIPS_CPU_ISA_III);
1407 c->fpu_msk31 |= FPU_CSR_CONDX;
1408 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1413 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1414 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1416 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1417 c->cputype = CPU_TX3927;
1418 __cpu_name[cpu] = "TX3927";
1421 switch (c->processor_id & PRID_REV_MASK) {
1422 case PRID_REV_TX3912:
1423 c->cputype = CPU_TX3912;
1424 __cpu_name[cpu] = "TX3912";
1427 case PRID_REV_TX3922:
1428 c->cputype = CPU_TX3922;
1429 __cpu_name[cpu] = "TX3922";
1435 case PRID_IMP_R4700:
1436 c->cputype = CPU_R4700;
1437 __cpu_name[cpu] = "R4700";
1438 set_isa(c, MIPS_CPU_ISA_III);
1439 c->fpu_msk31 |= FPU_CSR_CONDX;
1440 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1445 c->cputype = CPU_TX49XX;
1446 __cpu_name[cpu] = "R49XX";
1447 set_isa(c, MIPS_CPU_ISA_III);
1448 c->fpu_msk31 |= FPU_CSR_CONDX;
1449 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1450 if (!(c->processor_id & 0x08))
1451 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1454 case PRID_IMP_R5000:
1455 c->cputype = CPU_R5000;
1456 __cpu_name[cpu] = "R5000";
1457 set_isa(c, MIPS_CPU_ISA_IV);
1458 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1462 case PRID_IMP_R5500:
1463 c->cputype = CPU_R5500;
1464 __cpu_name[cpu] = "R5500";
1465 set_isa(c, MIPS_CPU_ISA_IV);
1466 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1467 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1470 case PRID_IMP_NEVADA:
1471 c->cputype = CPU_NEVADA;
1472 __cpu_name[cpu] = "Nevada";
1473 set_isa(c, MIPS_CPU_ISA_IV);
1474 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1475 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1478 case PRID_IMP_RM7000:
1479 c->cputype = CPU_RM7000;
1480 __cpu_name[cpu] = "RM7000";
1481 set_isa(c, MIPS_CPU_ISA_IV);
1482 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1485 * Undocumented RM7000: Bit 29 in the info register of
1486 * the RM7000 v2.0 indicates if the TLB has 48 or 64
1489 * 29 1 => 64 entry JTLB
1490 * 0 => 48 entry JTLB
1492 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1494 case PRID_IMP_R10000:
1495 c->cputype = CPU_R10000;
1496 __cpu_name[cpu] = "R10000";
1497 set_isa(c, MIPS_CPU_ISA_IV);
1498 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1499 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1500 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1504 case PRID_IMP_R12000:
1505 c->cputype = CPU_R12000;
1506 __cpu_name[cpu] = "R12000";
1507 set_isa(c, MIPS_CPU_ISA_IV);
1508 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1509 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1510 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1511 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1514 case PRID_IMP_R14000:
1515 if (((c->processor_id >> 4) & 0x0f) > 2) {
1516 c->cputype = CPU_R16000;
1517 __cpu_name[cpu] = "R16000";
1519 c->cputype = CPU_R14000;
1520 __cpu_name[cpu] = "R14000";
1522 set_isa(c, MIPS_CPU_ISA_IV);
1523 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1524 MIPS_CPU_FPU | MIPS_CPU_32FPR |
1525 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1526 MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1529 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1530 switch (c->processor_id & PRID_REV_MASK) {
1531 case PRID_REV_LOONGSON2E:
1532 c->cputype = CPU_LOONGSON2EF;
1533 __cpu_name[cpu] = "ICT Loongson-2";
1534 set_elf_platform(cpu, "loongson2e");
1535 set_isa(c, MIPS_CPU_ISA_III);
1536 c->fpu_msk31 |= FPU_CSR_CONDX;
1538 case PRID_REV_LOONGSON2F:
1539 c->cputype = CPU_LOONGSON2EF;
1540 __cpu_name[cpu] = "ICT Loongson-2";
1541 set_elf_platform(cpu, "loongson2f");
1542 set_isa(c, MIPS_CPU_ISA_III);
1543 c->fpu_msk31 |= FPU_CSR_CONDX;
1545 case PRID_REV_LOONGSON3A_R1:
1546 c->cputype = CPU_LOONGSON64;
1547 __cpu_name[cpu] = "ICT Loongson-3";
1548 set_elf_platform(cpu, "loongson3a");
1549 set_isa(c, MIPS_CPU_ISA_M64R1);
1550 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1551 MIPS_ASE_LOONGSON_EXT);
1553 case PRID_REV_LOONGSON3B_R1:
1554 case PRID_REV_LOONGSON3B_R2:
1555 c->cputype = CPU_LOONGSON64;
1556 __cpu_name[cpu] = "ICT Loongson-3";
1557 set_elf_platform(cpu, "loongson3b");
1558 set_isa(c, MIPS_CPU_ISA_M64R1);
1559 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1560 MIPS_ASE_LOONGSON_EXT);
1564 c->options = R4K_OPTS |
1565 MIPS_CPU_FPU | MIPS_CPU_LLSC |
1568 set_cpu_asid_mask(c, MIPS_ENTRYHI_ASID);
1569 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1571 case PRID_IMP_LOONGSON_32: /* Loongson-1 */
1574 c->cputype = CPU_LOONGSON32;
1576 switch (c->processor_id & PRID_REV_MASK) {
1577 case PRID_REV_LOONGSON1B:
1578 __cpu_name[cpu] = "Loongson 1B";
1586 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1588 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1589 switch (c->processor_id & PRID_IMP_MASK) {
1590 case PRID_IMP_QEMU_GENERIC:
1591 c->writecombine = _CACHE_UNCACHED;
1592 c->cputype = CPU_QEMU_GENERIC;
1593 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1596 c->cputype = CPU_4KC;
1597 c->writecombine = _CACHE_UNCACHED;
1598 __cpu_name[cpu] = "MIPS 4Kc";
1601 case PRID_IMP_4KECR2:
1602 c->cputype = CPU_4KEC;
1603 c->writecombine = _CACHE_UNCACHED;
1604 __cpu_name[cpu] = "MIPS 4KEc";
1608 c->cputype = CPU_4KSC;
1609 c->writecombine = _CACHE_UNCACHED;
1610 __cpu_name[cpu] = "MIPS 4KSc";
1613 c->cputype = CPU_5KC;
1614 c->writecombine = _CACHE_UNCACHED;
1615 __cpu_name[cpu] = "MIPS 5Kc";
1618 c->cputype = CPU_5KE;
1619 c->writecombine = _CACHE_UNCACHED;
1620 __cpu_name[cpu] = "MIPS 5KE";
1623 c->cputype = CPU_20KC;
1624 c->writecombine = _CACHE_UNCACHED;
1625 __cpu_name[cpu] = "MIPS 20Kc";
1628 c->cputype = CPU_24K;
1629 c->writecombine = _CACHE_UNCACHED;
1630 __cpu_name[cpu] = "MIPS 24Kc";
1633 c->cputype = CPU_24K;
1634 c->writecombine = _CACHE_UNCACHED;
1635 __cpu_name[cpu] = "MIPS 24KEc";
1638 c->cputype = CPU_25KF;
1639 c->writecombine = _CACHE_UNCACHED;
1640 __cpu_name[cpu] = "MIPS 25Kc";
1643 c->cputype = CPU_34K;
1644 c->writecombine = _CACHE_UNCACHED;
1645 __cpu_name[cpu] = "MIPS 34Kc";
1646 cpu_set_mt_per_tc_perf(c);
1649 c->cputype = CPU_74K;
1650 c->writecombine = _CACHE_UNCACHED;
1651 __cpu_name[cpu] = "MIPS 74Kc";
1653 case PRID_IMP_M14KC:
1654 c->cputype = CPU_M14KC;
1655 c->writecombine = _CACHE_UNCACHED;
1656 __cpu_name[cpu] = "MIPS M14Kc";
1658 case PRID_IMP_M14KEC:
1659 c->cputype = CPU_M14KEC;
1660 c->writecombine = _CACHE_UNCACHED;
1661 __cpu_name[cpu] = "MIPS M14KEc";
1663 case PRID_IMP_1004K:
1664 c->cputype = CPU_1004K;
1665 c->writecombine = _CACHE_UNCACHED;
1666 __cpu_name[cpu] = "MIPS 1004Kc";
1667 cpu_set_mt_per_tc_perf(c);
1669 case PRID_IMP_1074K:
1670 c->cputype = CPU_1074K;
1671 c->writecombine = _CACHE_UNCACHED;
1672 __cpu_name[cpu] = "MIPS 1074Kc";
1674 case PRID_IMP_INTERAPTIV_UP:
1675 c->cputype = CPU_INTERAPTIV;
1676 __cpu_name[cpu] = "MIPS interAptiv";
1677 cpu_set_mt_per_tc_perf(c);
1679 case PRID_IMP_INTERAPTIV_MP:
1680 c->cputype = CPU_INTERAPTIV;
1681 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1682 cpu_set_mt_per_tc_perf(c);
1684 case PRID_IMP_PROAPTIV_UP:
1685 c->cputype = CPU_PROAPTIV;
1686 __cpu_name[cpu] = "MIPS proAptiv";
1688 case PRID_IMP_PROAPTIV_MP:
1689 c->cputype = CPU_PROAPTIV;
1690 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1692 case PRID_IMP_P5600:
1693 c->cputype = CPU_P5600;
1694 __cpu_name[cpu] = "MIPS P5600";
1696 case PRID_IMP_P6600:
1697 c->cputype = CPU_P6600;
1698 __cpu_name[cpu] = "MIPS P6600";
1700 case PRID_IMP_I6400:
1701 c->cputype = CPU_I6400;
1702 __cpu_name[cpu] = "MIPS I6400";
1704 case PRID_IMP_I6500:
1705 c->cputype = CPU_I6500;
1706 __cpu_name[cpu] = "MIPS I6500";
1708 case PRID_IMP_M5150:
1709 c->cputype = CPU_M5150;
1710 __cpu_name[cpu] = "MIPS M5150";
1712 case PRID_IMP_M6250:
1713 c->cputype = CPU_M6250;
1714 __cpu_name[cpu] = "MIPS M6250";
1722 switch (__get_cpu_type(c->cputype)) {
1724 c->options |= MIPS_CPU_SHARED_FTLB_ENTRIES;
1727 c->options |= MIPS_CPU_SHARED_FTLB_RAM;
1734 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1737 switch (c->processor_id & PRID_IMP_MASK) {
1738 case PRID_IMP_AU1_REV1:
1739 case PRID_IMP_AU1_REV2:
1740 c->cputype = CPU_ALCHEMY;
1741 switch ((c->processor_id >> 24) & 0xff) {
1743 __cpu_name[cpu] = "Au1000";
1746 __cpu_name[cpu] = "Au1500";
1749 __cpu_name[cpu] = "Au1100";
1752 __cpu_name[cpu] = "Au1550";
1755 __cpu_name[cpu] = "Au1200";
1756 if ((c->processor_id & PRID_REV_MASK) == 2)
1757 __cpu_name[cpu] = "Au1250";
1760 __cpu_name[cpu] = "Au1210";
1763 __cpu_name[cpu] = "Au1xxx";
1770 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1774 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1775 switch (c->processor_id & PRID_IMP_MASK) {
1777 c->cputype = CPU_SB1;
1778 __cpu_name[cpu] = "SiByte SB1";
1779 /* FPU in pass1 is known to have issues. */
1780 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1781 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1784 c->cputype = CPU_SB1A;
1785 __cpu_name[cpu] = "SiByte SB1A";
1790 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1793 switch (c->processor_id & PRID_IMP_MASK) {
1794 case PRID_IMP_SR71000:
1795 c->cputype = CPU_SR71000;
1796 __cpu_name[cpu] = "Sandcraft SR71000";
1803 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1806 switch (c->processor_id & PRID_IMP_MASK) {
1807 case PRID_IMP_PR4450:
1808 c->cputype = CPU_PR4450;
1809 __cpu_name[cpu] = "Philips PR4450";
1810 set_isa(c, MIPS_CPU_ISA_M32R1);
1815 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1818 switch (c->processor_id & PRID_IMP_MASK) {
1819 case PRID_IMP_BMIPS32_REV4:
1820 case PRID_IMP_BMIPS32_REV8:
1821 c->cputype = CPU_BMIPS32;
1822 __cpu_name[cpu] = "Broadcom BMIPS32";
1823 set_elf_platform(cpu, "bmips32");
1825 case PRID_IMP_BMIPS3300:
1826 case PRID_IMP_BMIPS3300_ALT:
1827 case PRID_IMP_BMIPS3300_BUG:
1828 c->cputype = CPU_BMIPS3300;
1829 __cpu_name[cpu] = "Broadcom BMIPS3300";
1830 set_elf_platform(cpu, "bmips3300");
1832 case PRID_IMP_BMIPS43XX: {
1833 int rev = c->processor_id & PRID_REV_MASK;
1835 if (rev >= PRID_REV_BMIPS4380_LO &&
1836 rev <= PRID_REV_BMIPS4380_HI) {
1837 c->cputype = CPU_BMIPS4380;
1838 __cpu_name[cpu] = "Broadcom BMIPS4380";
1839 set_elf_platform(cpu, "bmips4380");
1840 c->options |= MIPS_CPU_RIXI;
1842 c->cputype = CPU_BMIPS4350;
1843 __cpu_name[cpu] = "Broadcom BMIPS4350";
1844 set_elf_platform(cpu, "bmips4350");
1848 case PRID_IMP_BMIPS5000:
1849 case PRID_IMP_BMIPS5200:
1850 c->cputype = CPU_BMIPS5000;
1851 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1852 __cpu_name[cpu] = "Broadcom BMIPS5200";
1854 __cpu_name[cpu] = "Broadcom BMIPS5000";
1855 set_elf_platform(cpu, "bmips5000");
1856 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1861 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1864 switch (c->processor_id & PRID_IMP_MASK) {
1865 case PRID_IMP_CAVIUM_CN38XX:
1866 case PRID_IMP_CAVIUM_CN31XX:
1867 case PRID_IMP_CAVIUM_CN30XX:
1868 c->cputype = CPU_CAVIUM_OCTEON;
1869 __cpu_name[cpu] = "Cavium Octeon";
1871 case PRID_IMP_CAVIUM_CN58XX:
1872 case PRID_IMP_CAVIUM_CN56XX:
1873 case PRID_IMP_CAVIUM_CN50XX:
1874 case PRID_IMP_CAVIUM_CN52XX:
1875 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1876 __cpu_name[cpu] = "Cavium Octeon+";
1878 set_elf_platform(cpu, "octeon");
1880 case PRID_IMP_CAVIUM_CN61XX:
1881 case PRID_IMP_CAVIUM_CN63XX:
1882 case PRID_IMP_CAVIUM_CN66XX:
1883 case PRID_IMP_CAVIUM_CN68XX:
1884 case PRID_IMP_CAVIUM_CNF71XX:
1885 c->cputype = CPU_CAVIUM_OCTEON2;
1886 __cpu_name[cpu] = "Cavium Octeon II";
1887 set_elf_platform(cpu, "octeon2");
1889 case PRID_IMP_CAVIUM_CN70XX:
1890 case PRID_IMP_CAVIUM_CN73XX:
1891 case PRID_IMP_CAVIUM_CNF75XX:
1892 case PRID_IMP_CAVIUM_CN78XX:
1893 c->cputype = CPU_CAVIUM_OCTEON3;
1894 __cpu_name[cpu] = "Cavium Octeon III";
1895 set_elf_platform(cpu, "octeon3");
1898 printk(KERN_INFO "Unknown Octeon chip!\n");
1899 c->cputype = CPU_UNKNOWN;
1904 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1906 switch (c->processor_id & PRID_IMP_MASK) {
1907 case PRID_IMP_LOONGSON_64C: /* Loongson-2/3 */
1908 switch (c->processor_id & PRID_REV_MASK) {
1909 case PRID_REV_LOONGSON3A_R2_0:
1910 case PRID_REV_LOONGSON3A_R2_1:
1911 c->cputype = CPU_LOONGSON64;
1912 __cpu_name[cpu] = "ICT Loongson-3";
1913 set_elf_platform(cpu, "loongson3a");
1914 set_isa(c, MIPS_CPU_ISA_M64R2);
1916 case PRID_REV_LOONGSON3A_R3_0:
1917 case PRID_REV_LOONGSON3A_R3_1:
1918 c->cputype = CPU_LOONGSON64;
1919 __cpu_name[cpu] = "ICT Loongson-3";
1920 set_elf_platform(cpu, "loongson3a");
1921 set_isa(c, MIPS_CPU_ISA_M64R2);
1926 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1927 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1928 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1929 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1931 case PRID_IMP_LOONGSON_64G:
1932 c->cputype = CPU_LOONGSON64;
1933 __cpu_name[cpu] = "ICT Loongson-3";
1934 set_elf_platform(cpu, "loongson3a");
1935 set_isa(c, MIPS_CPU_ISA_M64R2);
1937 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1938 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1939 c->ases |= (MIPS_ASE_LOONGSON_MMI | MIPS_ASE_LOONGSON_CAM |
1940 MIPS_ASE_LOONGSON_EXT | MIPS_ASE_LOONGSON_EXT2);
1943 panic("Unknown Loongson Processor ID!");
1948 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1953 * XBurst misses a config2 register, so config3 decode was skipped in
1958 /* XBurst does not implement the CP0 counter. */
1959 c->options &= ~MIPS_CPU_COUNTER;
1960 BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1962 switch (c->processor_id & PRID_IMP_MASK) {
1963 case PRID_IMP_XBURST:
1964 c->cputype = CPU_XBURST;
1965 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1966 __cpu_name[cpu] = "Ingenic JZRISC";
1968 * The XBurst core by default attempts to avoid branch target
1969 * buffer lookups by detecting & special casing loops. This
1970 * feature will cause BogoMIPS and lpj calculate in error.
1971 * Set cp0 config7 bit 4 to disable this feature.
1973 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN);
1976 panic("Unknown Ingenic Processor ID!");
1980 switch (c->processor_id & PRID_COMP_MASK) {
1982 * The config0 register in the XBurst CPUs with a processor ID of
1983 * PRID_COMP_INGENIC_D1 has an abandoned huge page tlb mode, this
1984 * mode is not compatible with the MIPS standard, it will cause
1985 * tlbmiss and into an infinite loop (line 21 in the tlb-funcs.S)
1986 * when starting the init process. After chip reset, the default
1987 * is HPTLB mode, Write 0xa9000000 to cp0 register 5 sel 4 to
1988 * switch back to VTLB mode to prevent getting stuck.
1990 case PRID_COMP_INGENIC_D1:
1991 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS);
1994 * The config0 register in the XBurst CPUs with a processor ID of
1995 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
1996 * but they don't actually support this ISA.
1998 case PRID_COMP_INGENIC_D0:
1999 c->isa_level &= ~MIPS_CPU_ISA_M32R2;
2006 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
2010 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
2011 c->cputype = CPU_ALCHEMY;
2012 __cpu_name[cpu] = "Au1300";
2013 /* following stuff is not for Alchemy */
2017 c->options = (MIPS_CPU_TLB |
2025 switch (c->processor_id & PRID_IMP_MASK) {
2026 case PRID_IMP_NETLOGIC_XLP2XX:
2027 case PRID_IMP_NETLOGIC_XLP9XX:
2028 case PRID_IMP_NETLOGIC_XLP5XX:
2029 c->cputype = CPU_XLP;
2030 __cpu_name[cpu] = "Broadcom XLPII";
2033 case PRID_IMP_NETLOGIC_XLP8XX:
2034 case PRID_IMP_NETLOGIC_XLP3XX:
2035 c->cputype = CPU_XLP;
2036 __cpu_name[cpu] = "Netlogic XLP";
2039 case PRID_IMP_NETLOGIC_XLR732:
2040 case PRID_IMP_NETLOGIC_XLR716:
2041 case PRID_IMP_NETLOGIC_XLR532:
2042 case PRID_IMP_NETLOGIC_XLR308:
2043 case PRID_IMP_NETLOGIC_XLR532C:
2044 case PRID_IMP_NETLOGIC_XLR516C:
2045 case PRID_IMP_NETLOGIC_XLR508C:
2046 case PRID_IMP_NETLOGIC_XLR308C:
2047 c->cputype = CPU_XLR;
2048 __cpu_name[cpu] = "Netlogic XLR";
2051 case PRID_IMP_NETLOGIC_XLS608:
2052 case PRID_IMP_NETLOGIC_XLS408:
2053 case PRID_IMP_NETLOGIC_XLS404:
2054 case PRID_IMP_NETLOGIC_XLS208:
2055 case PRID_IMP_NETLOGIC_XLS204:
2056 case PRID_IMP_NETLOGIC_XLS108:
2057 case PRID_IMP_NETLOGIC_XLS104:
2058 case PRID_IMP_NETLOGIC_XLS616B:
2059 case PRID_IMP_NETLOGIC_XLS608B:
2060 case PRID_IMP_NETLOGIC_XLS416B:
2061 case PRID_IMP_NETLOGIC_XLS412B:
2062 case PRID_IMP_NETLOGIC_XLS408B:
2063 case PRID_IMP_NETLOGIC_XLS404B:
2064 c->cputype = CPU_XLR;
2065 __cpu_name[cpu] = "Netlogic XLS";
2069 pr_info("Unknown Netlogic chip id [%02x]!\n",
2071 c->cputype = CPU_XLR;
2075 if (c->cputype == CPU_XLP) {
2076 set_isa(c, MIPS_CPU_ISA_M64R2);
2077 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
2078 /* This will be updated again after all threads are woken up */
2079 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
2081 set_isa(c, MIPS_CPU_ISA_M64R1);
2082 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
2084 c->kscratch_mask = 0xf;
2088 /* For use by uaccess.h */
2090 EXPORT_SYMBOL(__ua_limit);
2093 const char *__cpu_name[NR_CPUS];
2094 const char *__elf_platform;
2096 void cpu_probe(void)
2098 struct cpuinfo_mips *c = ¤t_cpu_data;
2099 unsigned int cpu = smp_processor_id();
2102 * Set a default elf platform, cpu probe may later
2103 * overwrite it with a more precise value
2105 set_elf_platform(cpu, "mips");
2107 c->processor_id = PRID_IMP_UNKNOWN;
2108 c->fpu_id = FPIR_IMP_NONE;
2109 c->cputype = CPU_UNKNOWN;
2110 c->writecombine = _CACHE_UNCACHED;
2112 c->fpu_csr31 = FPU_CSR_RN;
2113 c->fpu_msk31 = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
2115 c->processor_id = read_c0_prid();
2116 switch (c->processor_id & PRID_COMP_MASK) {
2117 case PRID_COMP_LEGACY:
2118 cpu_probe_legacy(c, cpu);
2120 case PRID_COMP_MIPS:
2121 cpu_probe_mips(c, cpu);
2123 case PRID_COMP_ALCHEMY:
2124 cpu_probe_alchemy(c, cpu);
2126 case PRID_COMP_SIBYTE:
2127 cpu_probe_sibyte(c, cpu);
2129 case PRID_COMP_BROADCOM:
2130 cpu_probe_broadcom(c, cpu);
2132 case PRID_COMP_SANDCRAFT:
2133 cpu_probe_sandcraft(c, cpu);
2136 cpu_probe_nxp(c, cpu);
2138 case PRID_COMP_CAVIUM:
2139 cpu_probe_cavium(c, cpu);
2141 case PRID_COMP_LOONGSON:
2142 cpu_probe_loongson(c, cpu);
2144 case PRID_COMP_INGENIC_D0:
2145 case PRID_COMP_INGENIC_D1:
2146 case PRID_COMP_INGENIC_E1:
2147 cpu_probe_ingenic(c, cpu);
2149 case PRID_COMP_NETLOGIC:
2150 cpu_probe_netlogic(c, cpu);
2154 BUG_ON(!__cpu_name[cpu]);
2155 BUG_ON(c->cputype == CPU_UNKNOWN);
2158 * Platform code can force the cpu type to optimize code
2159 * generation. In that case be sure the cpu type is correctly
2160 * manually setup otherwise it could trigger some nasty bugs.
2162 BUG_ON(current_cpu_type() != c->cputype);
2165 /* Enable the RIXI exceptions */
2166 set_c0_pagegrain(PG_IEC);
2167 back_to_back_c0_hazard();
2168 /* Verify the IEC bit is set */
2169 if (read_c0_pagegrain() & PG_IEC)
2170 c->options |= MIPS_CPU_RIXIEX;
2173 if (mips_fpu_disabled)
2174 c->options &= ~MIPS_CPU_FPU;
2176 if (mips_dsp_disabled)
2177 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2179 if (mips_htw_disabled) {
2180 c->options &= ~MIPS_CPU_HTW;
2181 write_c0_pwctl(read_c0_pwctl() &
2182 ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2185 if (c->options & MIPS_CPU_FPU)
2186 cpu_set_fpu_opts(c);
2188 cpu_set_nofpu_opts(c);
2190 if (cpu_has_bp_ghist)
2191 write_c0_r10k_diag(read_c0_r10k_diag() |
2194 if (cpu_has_mips_r2_r6) {
2195 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2196 /* R2 has Performance Counter Interrupt indicator */
2197 c->options |= MIPS_CPU_PCI;
2202 if (cpu_has_mips_r6)
2203 elf_hwcap |= HWCAP_MIPS_R6;
2206 c->msa_id = cpu_get_msa_id();
2207 WARN(c->msa_id & MSA_IR_WRPF,
2208 "Vector register partitioning unimplemented!");
2209 elf_hwcap |= HWCAP_MIPS_MSA;
2213 elf_hwcap |= HWCAP_MIPS_MIPS16;
2216 elf_hwcap |= HWCAP_MIPS_MDMX;
2219 elf_hwcap |= HWCAP_MIPS_MIPS3D;
2221 if (cpu_has_smartmips)
2222 elf_hwcap |= HWCAP_MIPS_SMARTMIPS;
2225 elf_hwcap |= HWCAP_MIPS_DSP;
2228 elf_hwcap |= HWCAP_MIPS_DSP2;
2231 elf_hwcap |= HWCAP_MIPS_DSP3;
2233 if (cpu_has_mips16e2)
2234 elf_hwcap |= HWCAP_MIPS_MIPS16E2;
2236 if (cpu_has_loongson_mmi)
2237 elf_hwcap |= HWCAP_LOONGSON_MMI;
2239 if (cpu_has_loongson_ext)
2240 elf_hwcap |= HWCAP_LOONGSON_EXT;
2242 if (cpu_has_loongson_ext2)
2243 elf_hwcap |= HWCAP_LOONGSON_EXT2;
2248 cpu_probe_vmbits(c);
2252 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2256 void cpu_report(void)
2258 struct cpuinfo_mips *c = ¤t_cpu_data;
2260 pr_info("CPU%d revision is: %08x (%s)\n",
2261 smp_processor_id(), c->processor_id, cpu_name_string());
2262 if (c->options & MIPS_CPU_FPU)
2263 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2265 pr_info("MSA revision is: %08x\n", c->msa_id);
2268 void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
2270 /* Ensure the core number fits in the field */
2271 WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
2272 MIPS_GLOBALNUMBER_CLUSTER_SHF));
2274 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
2275 cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
2278 void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
2280 /* Ensure the core number fits in the field */
2281 WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
2283 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
2284 cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
2287 void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
2289 /* Ensure the VP(E) ID fits in the field */
2290 WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
2292 /* Ensure we're not using VP(E)s without support */
2293 WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
2294 !IS_ENABLED(CONFIG_CPU_MIPSR6));
2296 cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
2297 cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;