2 * Processor capabilities determination functions.
4 * Copyright (C) xxxx the Anonymous
5 * Copyright (C) 1994 - 2006 Ralf Baechle
6 * Copyright (C) 2003, 2004 Maciej W. Rozycki
7 * Copyright (C) 2001, 2004 MIPS Inc.
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 #include <linux/init.h>
15 #include <linux/kernel.h>
16 #include <linux/ptrace.h>
17 #include <linux/smp.h>
18 #include <linux/stddef.h>
19 #include <linux/module.h>
24 #include <asm/mipsregs.h>
25 #include <asm/system.h>
26 #include <asm/watch.h>
27 #include <asm/spram.h>
29 * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
30 * the implementation of the "wait" feature differs between CPU families. This
31 * points to the function that implements CPU specific wait.
32 * The wait instruction stops the pipeline and reduces the power consumption of
35 void (*cpu_wait)(void);
36 EXPORT_SYMBOL(cpu_wait);
38 static void r3081_wait(void)
40 unsigned long cfg = read_c0_conf();
41 write_c0_conf(cfg | R30XX_CONF_HALT);
44 static void r39xx_wait(void)
48 write_c0_conf(read_c0_conf() | TX39_CONF_HALT);
52 extern void r4k_wait(void);
55 * This variant is preferable as it allows testing need_resched and going to
56 * sleep depending on the outcome atomically. Unfortunately the "It is
57 * implementation-dependent whether the pipeline restarts when a non-enabled
58 * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
59 * using this version a gamble.
61 void r4k_wait_irqoff(void)
65 __asm__(" .set push \n"
70 __asm__(" .globl __pastwait \n"
76 * The RM7000 variant has to handle erratum 38. The workaround is to not
77 * have any pending stores when the WAIT instruction is executed.
79 static void rm7k_wait_irqoff(void)
89 " mtc0 $1, $12 # stalls until W stage \n"
91 " mtc0 $1, $12 # stalls until W stage \n"
97 * The Au1xxx wait is available only if using 32khz counter or
98 * external timer source, but specifically not CP0 Counter.
99 * alchemy/common/time.c may override cpu_wait!
101 static void au1k_wait(void)
103 __asm__(" .set mips3 \n"
104 " cache 0x14, 0(%0) \n"
105 " cache 0x14, 32(%0) \n"
114 : : "r" (au1k_wait));
117 static int __initdata nowait;
119 static int __init wait_disable(char *s)
126 __setup("nowait", wait_disable);
128 void __init check_wait(void)
130 struct cpuinfo_mips *c = ¤t_cpu_data;
133 printk("Wait instruction disabled.\n");
137 switch (c->cputype) {
140 cpu_wait = r3081_wait;
143 cpu_wait = r39xx_wait;
146 /* case CPU_R4300: */
164 case CPU_CAVIUM_OCTEON:
165 case CPU_CAVIUM_OCTEON_PLUS:
170 cpu_wait = rm7k_wait_irqoff;
177 if (read_c0_config7() & MIPS_CONF7_WII)
178 cpu_wait = r4k_wait_irqoff;
183 if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0))
184 cpu_wait = r4k_wait_irqoff;
188 cpu_wait = r4k_wait_irqoff;
191 cpu_wait = au1k_wait;
195 * WAIT on Rev1.0 has E1, E2, E3 and E16.
196 * WAIT on Rev2.0 and Rev3.0 has E16.
197 * Rev3.1 WAIT is nop, why bother
199 if ((c->processor_id & 0xff) <= 0x64)
203 * Another rev is incremeting c0_count at a reduced clock
204 * rate while in WAIT mode. So we basically have the choice
205 * between using the cp0 timer as clocksource or avoiding
206 * the WAIT instruction. Until more details are known,
207 * disable the use of WAIT for 20Kc entirely.
212 if ((c->processor_id & 0x00ff) >= 0x40)
220 static inline void check_errata(void)
222 struct cpuinfo_mips *c = ¤t_cpu_data;
224 switch (c->cputype) {
227 * Erratum "RPS May Cause Incorrect Instruction Execution"
228 * This code only handles VPE0, any SMP/SMTC/RTOS code
229 * making use of VPE1 will be responsable for that VPE.
231 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
232 write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
239 void __init check_bugs32(void)
245 * Probe whether cpu has config register by trying to play with
246 * alternate cache bit and see whether it matters.
247 * It's used by cpu_probe to distinguish between R3000A and R3081.
249 static inline int cpu_has_confreg(void)
251 #ifdef CONFIG_CPU_R3000
252 extern unsigned long r3k_cache_size(unsigned long);
253 unsigned long size1, size2;
254 unsigned long cfg = read_c0_conf();
256 size1 = r3k_cache_size(ST0_ISC);
257 write_c0_conf(cfg ^ R30XX_CONF_AC);
258 size2 = r3k_cache_size(ST0_ISC);
260 return size1 != size2;
267 * Get the FPU Implementation/Revision.
269 static inline unsigned long cpu_get_fpu_id(void)
271 unsigned long tmp, fpu_id;
273 tmp = read_c0_status();
275 fpu_id = read_32bit_cp1_register(CP1_REVISION);
276 write_c0_status(tmp);
281 * Check the CPU has an FPU the official way.
283 static inline int __cpu_has_fpu(void)
285 return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
288 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
290 #ifdef __NEED_VMBITS_PROBE
291 write_c0_entryhi(0x3fffffffffffe000ULL);
292 back_to_back_c0_hazard();
293 c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
297 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
300 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
302 switch (c->processor_id & 0xff00) {
304 c->cputype = CPU_R2000;
305 __cpu_name[cpu] = "R2000";
306 c->isa_level = MIPS_CPU_ISA_I;
307 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
310 c->options |= MIPS_CPU_FPU;
314 if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
315 if (cpu_has_confreg()) {
316 c->cputype = CPU_R3081E;
317 __cpu_name[cpu] = "R3081";
319 c->cputype = CPU_R3000A;
320 __cpu_name[cpu] = "R3000A";
324 c->cputype = CPU_R3000;
325 __cpu_name[cpu] = "R3000";
327 c->isa_level = MIPS_CPU_ISA_I;
328 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
331 c->options |= MIPS_CPU_FPU;
335 if (read_c0_config() & CONF_SC) {
336 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
337 c->cputype = CPU_R4400PC;
338 __cpu_name[cpu] = "R4400PC";
340 c->cputype = CPU_R4000PC;
341 __cpu_name[cpu] = "R4000PC";
344 if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
345 c->cputype = CPU_R4400SC;
346 __cpu_name[cpu] = "R4400SC";
348 c->cputype = CPU_R4000SC;
349 __cpu_name[cpu] = "R4000SC";
353 c->isa_level = MIPS_CPU_ISA_III;
354 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
355 MIPS_CPU_WATCH | MIPS_CPU_VCE |
359 case PRID_IMP_VR41XX:
360 switch (c->processor_id & 0xf0) {
361 case PRID_REV_VR4111:
362 c->cputype = CPU_VR4111;
363 __cpu_name[cpu] = "NEC VR4111";
365 case PRID_REV_VR4121:
366 c->cputype = CPU_VR4121;
367 __cpu_name[cpu] = "NEC VR4121";
369 case PRID_REV_VR4122:
370 if ((c->processor_id & 0xf) < 0x3) {
371 c->cputype = CPU_VR4122;
372 __cpu_name[cpu] = "NEC VR4122";
374 c->cputype = CPU_VR4181A;
375 __cpu_name[cpu] = "NEC VR4181A";
378 case PRID_REV_VR4130:
379 if ((c->processor_id & 0xf) < 0x4) {
380 c->cputype = CPU_VR4131;
381 __cpu_name[cpu] = "NEC VR4131";
383 c->cputype = CPU_VR4133;
384 __cpu_name[cpu] = "NEC VR4133";
388 printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
389 c->cputype = CPU_VR41XX;
390 __cpu_name[cpu] = "NEC Vr41xx";
393 c->isa_level = MIPS_CPU_ISA_III;
394 c->options = R4K_OPTS;
398 c->cputype = CPU_R4300;
399 __cpu_name[cpu] = "R4300";
400 c->isa_level = MIPS_CPU_ISA_III;
401 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
406 c->cputype = CPU_R4600;
407 __cpu_name[cpu] = "R4600";
408 c->isa_level = MIPS_CPU_ISA_III;
409 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
416 * This processor doesn't have an MMU, so it's not
417 * "real easy" to run Linux on it. It is left purely
418 * for documentation. Commented out because it shares
419 * it's c0_prid id number with the TX3900.
421 c->cputype = CPU_R4650;
422 __cpu_name[cpu] = "R4650";
423 c->isa_level = MIPS_CPU_ISA_III;
424 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
429 c->isa_level = MIPS_CPU_ISA_I;
430 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
432 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
433 c->cputype = CPU_TX3927;
434 __cpu_name[cpu] = "TX3927";
437 switch (c->processor_id & 0xff) {
438 case PRID_REV_TX3912:
439 c->cputype = CPU_TX3912;
440 __cpu_name[cpu] = "TX3912";
443 case PRID_REV_TX3922:
444 c->cputype = CPU_TX3922;
445 __cpu_name[cpu] = "TX3922";
452 c->cputype = CPU_R4700;
453 __cpu_name[cpu] = "R4700";
454 c->isa_level = MIPS_CPU_ISA_III;
455 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
460 c->cputype = CPU_TX49XX;
461 __cpu_name[cpu] = "R49XX";
462 c->isa_level = MIPS_CPU_ISA_III;
463 c->options = R4K_OPTS | MIPS_CPU_LLSC;
464 if (!(c->processor_id & 0x08))
465 c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
469 c->cputype = CPU_R5000;
470 __cpu_name[cpu] = "R5000";
471 c->isa_level = MIPS_CPU_ISA_IV;
472 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
477 c->cputype = CPU_R5432;
478 __cpu_name[cpu] = "R5432";
479 c->isa_level = MIPS_CPU_ISA_IV;
480 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
481 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
485 c->cputype = CPU_R5500;
486 __cpu_name[cpu] = "R5500";
487 c->isa_level = MIPS_CPU_ISA_IV;
488 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
489 MIPS_CPU_WATCH | MIPS_CPU_LLSC;
492 case PRID_IMP_NEVADA:
493 c->cputype = CPU_NEVADA;
494 __cpu_name[cpu] = "Nevada";
495 c->isa_level = MIPS_CPU_ISA_IV;
496 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
497 MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
501 c->cputype = CPU_R6000;
502 __cpu_name[cpu] = "R6000";
503 c->isa_level = MIPS_CPU_ISA_II;
504 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
508 case PRID_IMP_R6000A:
509 c->cputype = CPU_R6000A;
510 __cpu_name[cpu] = "R6000A";
511 c->isa_level = MIPS_CPU_ISA_II;
512 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
516 case PRID_IMP_RM7000:
517 c->cputype = CPU_RM7000;
518 __cpu_name[cpu] = "RM7000";
519 c->isa_level = MIPS_CPU_ISA_IV;
520 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
523 * Undocumented RM7000: Bit 29 in the info register of
524 * the RM7000 v2.0 indicates if the TLB has 48 or 64
527 * 29 1 => 64 entry JTLB
530 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
532 case PRID_IMP_RM9000:
533 c->cputype = CPU_RM9000;
534 __cpu_name[cpu] = "RM9000";
535 c->isa_level = MIPS_CPU_ISA_IV;
536 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
539 * Bit 29 in the info register of the RM9000
540 * indicates if the TLB has 48 or 64 entries.
542 * 29 1 => 64 entry JTLB
545 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
548 c->cputype = CPU_R8000;
549 __cpu_name[cpu] = "RM8000";
550 c->isa_level = MIPS_CPU_ISA_IV;
551 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
552 MIPS_CPU_FPU | MIPS_CPU_32FPR |
554 c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
556 case PRID_IMP_R10000:
557 c->cputype = CPU_R10000;
558 __cpu_name[cpu] = "R10000";
559 c->isa_level = MIPS_CPU_ISA_IV;
560 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
561 MIPS_CPU_FPU | MIPS_CPU_32FPR |
562 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
566 case PRID_IMP_R12000:
567 c->cputype = CPU_R12000;
568 __cpu_name[cpu] = "R12000";
569 c->isa_level = MIPS_CPU_ISA_IV;
570 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
571 MIPS_CPU_FPU | MIPS_CPU_32FPR |
572 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
576 case PRID_IMP_R14000:
577 c->cputype = CPU_R14000;
578 __cpu_name[cpu] = "R14000";
579 c->isa_level = MIPS_CPU_ISA_IV;
580 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
581 MIPS_CPU_FPU | MIPS_CPU_32FPR |
582 MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
586 case PRID_IMP_LOONGSON2:
587 c->cputype = CPU_LOONGSON2;
588 __cpu_name[cpu] = "ICT Loongson-2";
589 c->isa_level = MIPS_CPU_ISA_III;
590 c->options = R4K_OPTS |
591 MIPS_CPU_FPU | MIPS_CPU_LLSC |
598 static char unknown_isa[] __cpuinitdata = KERN_ERR \
599 "Unsupported ISA type, c0.config0: %d.";
601 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
603 unsigned int config0;
606 config0 = read_c0_config();
608 if (((config0 & MIPS_CONF_MT) >> 7) == 1)
609 c->options |= MIPS_CPU_TLB;
610 isa = (config0 & MIPS_CONF_AT) >> 13;
613 switch ((config0 & MIPS_CONF_AR) >> 10) {
615 c->isa_level = MIPS_CPU_ISA_M32R1;
618 c->isa_level = MIPS_CPU_ISA_M32R2;
625 switch ((config0 & MIPS_CONF_AR) >> 10) {
627 c->isa_level = MIPS_CPU_ISA_M64R1;
630 c->isa_level = MIPS_CPU_ISA_M64R2;
640 return config0 & MIPS_CONF_M;
643 panic(unknown_isa, config0);
646 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
648 unsigned int config1;
650 config1 = read_c0_config1();
652 if (config1 & MIPS_CONF1_MD)
653 c->ases |= MIPS_ASE_MDMX;
654 if (config1 & MIPS_CONF1_WR)
655 c->options |= MIPS_CPU_WATCH;
656 if (config1 & MIPS_CONF1_CA)
657 c->ases |= MIPS_ASE_MIPS16;
658 if (config1 & MIPS_CONF1_EP)
659 c->options |= MIPS_CPU_EJTAG;
660 if (config1 & MIPS_CONF1_FP) {
661 c->options |= MIPS_CPU_FPU;
662 c->options |= MIPS_CPU_32FPR;
665 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
667 return config1 & MIPS_CONF_M;
670 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
672 unsigned int config2;
674 config2 = read_c0_config2();
676 if (config2 & MIPS_CONF2_SL)
677 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
679 return config2 & MIPS_CONF_M;
682 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
684 unsigned int config3;
686 config3 = read_c0_config3();
688 if (config3 & MIPS_CONF3_SM)
689 c->ases |= MIPS_ASE_SMARTMIPS;
690 if (config3 & MIPS_CONF3_DSP)
691 c->ases |= MIPS_ASE_DSP;
692 if (config3 & MIPS_CONF3_VINT)
693 c->options |= MIPS_CPU_VINT;
694 if (config3 & MIPS_CONF3_VEIC)
695 c->options |= MIPS_CPU_VEIC;
696 if (config3 & MIPS_CONF3_MT)
697 c->ases |= MIPS_ASE_MIPSMT;
698 if (config3 & MIPS_CONF3_ULRI)
699 c->options |= MIPS_CPU_ULRI;
701 return config3 & MIPS_CONF_M;
704 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
706 unsigned int config4;
708 config4 = read_c0_config4();
710 if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
712 c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
714 return config4 & MIPS_CONF_M;
717 static void __cpuinit decode_configs(struct cpuinfo_mips *c)
721 /* MIPS32 or MIPS64 compliant CPU. */
722 c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
723 MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
725 c->scache.flags = MIPS_CACHE_NOT_PRESENT;
727 ok = decode_config0(c); /* Read Config registers. */
728 BUG_ON(!ok); /* Arch spec violation! */
730 ok = decode_config1(c);
732 ok = decode_config2(c);
734 ok = decode_config3(c);
736 ok = decode_config4(c);
738 mips_probe_watch_registers(c);
741 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
744 switch (c->processor_id & 0xff00) {
746 c->cputype = CPU_4KC;
747 __cpu_name[cpu] = "MIPS 4Kc";
750 case PRID_IMP_4KECR2:
751 c->cputype = CPU_4KEC;
752 __cpu_name[cpu] = "MIPS 4KEc";
756 c->cputype = CPU_4KSC;
757 __cpu_name[cpu] = "MIPS 4KSc";
760 c->cputype = CPU_5KC;
761 __cpu_name[cpu] = "MIPS 5Kc";
764 c->cputype = CPU_20KC;
765 __cpu_name[cpu] = "MIPS 20Kc";
769 c->cputype = CPU_24K;
770 __cpu_name[cpu] = "MIPS 24Kc";
773 c->cputype = CPU_25KF;
774 __cpu_name[cpu] = "MIPS 25Kc";
777 c->cputype = CPU_34K;
778 __cpu_name[cpu] = "MIPS 34Kc";
781 c->cputype = CPU_74K;
782 __cpu_name[cpu] = "MIPS 74Kc";
785 c->cputype = CPU_1004K;
786 __cpu_name[cpu] = "MIPS 1004Kc";
793 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
796 switch (c->processor_id & 0xff00) {
797 case PRID_IMP_AU1_REV1:
798 case PRID_IMP_AU1_REV2:
799 c->cputype = CPU_ALCHEMY;
800 switch ((c->processor_id >> 24) & 0xff) {
802 __cpu_name[cpu] = "Au1000";
805 __cpu_name[cpu] = "Au1500";
808 __cpu_name[cpu] = "Au1100";
811 __cpu_name[cpu] = "Au1550";
814 __cpu_name[cpu] = "Au1200";
815 if ((c->processor_id & 0xff) == 2)
816 __cpu_name[cpu] = "Au1250";
819 __cpu_name[cpu] = "Au1210";
822 __cpu_name[cpu] = "Au1xxx";
829 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
833 switch (c->processor_id & 0xff00) {
835 c->cputype = CPU_SB1;
836 __cpu_name[cpu] = "SiByte SB1";
837 /* FPU in pass1 is known to have issues. */
838 if ((c->processor_id & 0xff) < 0x02)
839 c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
842 c->cputype = CPU_SB1A;
843 __cpu_name[cpu] = "SiByte SB1A";
848 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
851 switch (c->processor_id & 0xff00) {
852 case PRID_IMP_SR71000:
853 c->cputype = CPU_SR71000;
854 __cpu_name[cpu] = "Sandcraft SR71000";
861 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
864 switch (c->processor_id & 0xff00) {
865 case PRID_IMP_PR4450:
866 c->cputype = CPU_PR4450;
867 __cpu_name[cpu] = "Philips PR4450";
868 c->isa_level = MIPS_CPU_ISA_M32R1;
873 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
876 switch (c->processor_id & 0xff00) {
877 case PRID_IMP_BCM3302:
878 /* same as PRID_IMP_BCM6338 */
879 c->cputype = CPU_BCM3302;
880 __cpu_name[cpu] = "Broadcom BCM3302";
882 case PRID_IMP_BCM4710:
883 c->cputype = CPU_BCM4710;
884 __cpu_name[cpu] = "Broadcom BCM4710";
886 case PRID_IMP_BCM6345:
887 c->cputype = CPU_BCM6345;
888 __cpu_name[cpu] = "Broadcom BCM6345";
890 case PRID_IMP_BCM6348:
891 c->cputype = CPU_BCM6348;
892 __cpu_name[cpu] = "Broadcom BCM6348";
894 case PRID_IMP_BCM4350:
895 switch (c->processor_id & 0xf0) {
896 case PRID_REV_BCM6358:
897 c->cputype = CPU_BCM6358;
898 __cpu_name[cpu] = "Broadcom BCM6358";
901 c->cputype = CPU_UNKNOWN;
908 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
911 switch (c->processor_id & 0xff00) {
912 case PRID_IMP_CAVIUM_CN38XX:
913 case PRID_IMP_CAVIUM_CN31XX:
914 case PRID_IMP_CAVIUM_CN30XX:
915 c->cputype = CPU_CAVIUM_OCTEON;
916 __cpu_name[cpu] = "Cavium Octeon";
918 case PRID_IMP_CAVIUM_CN58XX:
919 case PRID_IMP_CAVIUM_CN56XX:
920 case PRID_IMP_CAVIUM_CN50XX:
921 case PRID_IMP_CAVIUM_CN52XX:
922 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
923 __cpu_name[cpu] = "Cavium Octeon+";
926 __elf_platform = "octeon";
929 printk(KERN_INFO "Unknown Octeon chip!\n");
930 c->cputype = CPU_UNKNOWN;
935 const char *__cpu_name[NR_CPUS];
936 const char *__elf_platform;
938 __cpuinit void cpu_probe(void)
940 struct cpuinfo_mips *c = ¤t_cpu_data;
941 unsigned int cpu = smp_processor_id();
943 c->processor_id = PRID_IMP_UNKNOWN;
944 c->fpu_id = FPIR_IMP_NONE;
945 c->cputype = CPU_UNKNOWN;
947 c->processor_id = read_c0_prid();
948 switch (c->processor_id & 0xff0000) {
949 case PRID_COMP_LEGACY:
950 cpu_probe_legacy(c, cpu);
953 cpu_probe_mips(c, cpu);
955 case PRID_COMP_ALCHEMY:
956 cpu_probe_alchemy(c, cpu);
958 case PRID_COMP_SIBYTE:
959 cpu_probe_sibyte(c, cpu);
961 case PRID_COMP_BROADCOM:
962 cpu_probe_broadcom(c, cpu);
964 case PRID_COMP_SANDCRAFT:
965 cpu_probe_sandcraft(c, cpu);
968 cpu_probe_nxp(c, cpu);
970 case PRID_COMP_CAVIUM:
971 cpu_probe_cavium(c, cpu);
975 BUG_ON(!__cpu_name[cpu]);
976 BUG_ON(c->cputype == CPU_UNKNOWN);
979 * Platform code can force the cpu type to optimize code
980 * generation. In that case be sure the cpu type is correctly
981 * manually setup otherwise it could trigger some nasty bugs.
983 BUG_ON(current_cpu_type() != c->cputype);
985 if (c->options & MIPS_CPU_FPU) {
986 c->fpu_id = cpu_get_fpu_id();
988 if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
989 c->isa_level == MIPS_CPU_ISA_M32R2 ||
990 c->isa_level == MIPS_CPU_ISA_M64R1 ||
991 c->isa_level == MIPS_CPU_ISA_M64R2) {
992 if (c->fpu_id & MIPS_FPIR_3D)
993 c->ases |= MIPS_ASE_MIPS3D;
998 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
1002 cpu_probe_vmbits(c);
1005 __cpuinit void cpu_report(void)
1007 struct cpuinfo_mips *c = ¤t_cpu_data;
1009 printk(KERN_INFO "CPU revision is: %08x (%s)\n",
1010 c->processor_id, cpu_name_string());
1011 if (c->options & MIPS_CPU_FPU)
1012 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);