arch/mips/kernel/cpu-probe.c

   1 /*
   2  * Processor capabilities determination functions.
   3  *
   4  * Copyright (C) xxxx  the Anonymous
   5  * Copyright (C) 1994 - 2006 Ralf Baechle
   6  * Copyright (C) 2003, 2004  Maciej W. Rozycki
   7  * Copyright (C) 2001, 2004, 2011, 2012  MIPS Technologies, Inc.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/ptrace.h>
  17 #include <linux/smp.h>
  18 #include <linux/stddef.h>
  19 #include <linux/export.h>
  20
  21 #include <asm/bugs.h>
  22 #include <asm/cpu.h>
  23 #include <asm/cpu-features.h>
  24 #include <asm/cpu-type.h>
  25 #include <asm/fpu.h>
  26 #include <asm/mipsregs.h>
  27 #include <asm/mipsmtregs.h>
  28 #include <asm/msa.h>
  29 #include <asm/watch.h>
  30 #include <asm/elf.h>
  31 #include <asm/pgtable-bits.h>
  32 #include <asm/spram.h>
  33 #include <linux/uaccess.h>
  34
  35 /* Hardware capabilities */
  36 unsigned int elf_hwcap __read_mostly;
  37
  38 /*
  39  * Get the FPU Implementation/Revision.
  40  */
  41 static inline unsigned long cpu_get_fpu_id(void)
  42 {
  43         unsigned long tmp, fpu_id;
  44
  45         tmp = read_c0_status();
  46         __enable_fpu(FPU_AS_IS);
  47         fpu_id = read_32bit_cp1_register(CP1_REVISION);
  48         write_c0_status(tmp);
  49         return fpu_id;
  50 }
  51
  52 /*
  53  * Check if the CPU has an external FPU.
  54  */
  55 static inline int __cpu_has_fpu(void)
  56 {
  57         return (cpu_get_fpu_id() & FPIR_IMP_MASK) != FPIR_IMP_NONE;
  58 }
  59
  60 static inline unsigned long cpu_get_msa_id(void)
  61 {
  62         unsigned long status, msa_id;
  63
  64         status = read_c0_status();
  65         __enable_fpu(FPU_64BIT);
  66         enable_msa();
  67         msa_id = read_msa_ir();
  68         disable_msa();
  69         write_c0_status(status);
  70         return msa_id;
  71 }
  72
  73 /*
  74  * Determine the FCSR mask for FPU hardware.
  75  */
  76 static inline void cpu_set_fpu_fcsr_mask(struct cpuinfo_mips *c)
  77 {
  78         unsigned long sr, mask, fcsr, fcsr0, fcsr1;
  79
  80         fcsr = c->fpu_csr31;
  81         mask = FPU_CSR_ALL_X | FPU_CSR_ALL_E | FPU_CSR_ALL_S | FPU_CSR_RM;
  82
  83         sr = read_c0_status();
  84         __enable_fpu(FPU_AS_IS);
  85
  86         fcsr0 = fcsr & mask;
  87         write_32bit_cp1_register(CP1_STATUS, fcsr0);
  88         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
  89
  90         fcsr1 = fcsr | ~mask;
  91         write_32bit_cp1_register(CP1_STATUS, fcsr1);
  92         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
  93
  94         write_32bit_cp1_register(CP1_STATUS, fcsr);
  95
  96         write_c0_status(sr);
  97
  98         c->fpu_msk31 = ~(fcsr0 ^ fcsr1) & ~mask;
  99 }
 100
 101 /*
 102  * Determine the IEEE 754 NaN encodings and ABS.fmt/NEG.fmt execution modes
 103  * supported by FPU hardware.
 104  */
 105 static void cpu_set_fpu_2008(struct cpuinfo_mips *c)
 106 {
 107         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 108                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 109                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 110                 unsigned long sr, fir, fcsr, fcsr0, fcsr1;
 111
 112                 sr = read_c0_status();
 113                 __enable_fpu(FPU_AS_IS);
 114
 115                 fir = read_32bit_cp1_register(CP1_REVISION);
 116                 if (fir & MIPS_FPIR_HAS2008) {
 117                         fcsr = read_32bit_cp1_register(CP1_STATUS);
 118
 119                         fcsr0 = fcsr & ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 120                         write_32bit_cp1_register(CP1_STATUS, fcsr0);
 121                         fcsr0 = read_32bit_cp1_register(CP1_STATUS);
 122
 123                         fcsr1 = fcsr | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 124                         write_32bit_cp1_register(CP1_STATUS, fcsr1);
 125                         fcsr1 = read_32bit_cp1_register(CP1_STATUS);
 126
 127                         write_32bit_cp1_register(CP1_STATUS, fcsr);
 128
 129                         if (!(fcsr0 & FPU_CSR_NAN2008))
 130                                 c->options |= MIPS_CPU_NAN_LEGACY;
 131                         if (fcsr1 & FPU_CSR_NAN2008)
 132                                 c->options |= MIPS_CPU_NAN_2008;
 133
 134                         if ((fcsr0 ^ fcsr1) & FPU_CSR_ABS2008)
 135                                 c->fpu_msk31 &= ~FPU_CSR_ABS2008;
 136                         else
 137                                 c->fpu_csr31 |= fcsr & FPU_CSR_ABS2008;
 138
 139                         if ((fcsr0 ^ fcsr1) & FPU_CSR_NAN2008)
 140                                 c->fpu_msk31 &= ~FPU_CSR_NAN2008;
 141                         else
 142                                 c->fpu_csr31 |= fcsr & FPU_CSR_NAN2008;
 143                 } else {
 144                         c->options |= MIPS_CPU_NAN_LEGACY;
 145                 }
 146
 147                 write_c0_status(sr);
 148         } else {
 149                 c->options |= MIPS_CPU_NAN_LEGACY;
 150         }
 151 }
 152
 153 /*
 154  * IEEE 754 conformance mode to use.  Affects the NaN encoding and the
 155  * ABS.fmt/NEG.fmt execution mode.
 156  */
 157 static enum { STRICT, LEGACY, STD2008, RELAXED } ieee754 = STRICT;
 158
 159 /*
 160  * Set the IEEE 754 NaN encodings and the ABS.fmt/NEG.fmt execution modes
 161  * to support by the FPU emulator according to the IEEE 754 conformance
 162  * mode selected.  Note that "relaxed" straps the emulator so that it
 163  * allows 2008-NaN binaries even for legacy processors.
 164  */
 165 static void cpu_set_nofpu_2008(struct cpuinfo_mips *c)
 166 {
 167         c->options &= ~(MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY);
 168         c->fpu_csr31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 169         c->fpu_msk31 &= ~(FPU_CSR_ABS2008 | FPU_CSR_NAN2008);
 170
 171         switch (ieee754) {
 172         case STRICT:
 173                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 174                                     MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 175                                     MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 176                         c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 177                 } else {
 178                         c->options |= MIPS_CPU_NAN_LEGACY;
 179                         c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 180                 }
 181                 break;
 182         case LEGACY:
 183                 c->options |= MIPS_CPU_NAN_LEGACY;
 184                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 185                 break;
 186         case STD2008:
 187                 c->options |= MIPS_CPU_NAN_2008;
 188                 c->fpu_csr31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 189                 c->fpu_msk31 |= FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
 190                 break;
 191         case RELAXED:
 192                 c->options |= MIPS_CPU_NAN_2008 | MIPS_CPU_NAN_LEGACY;
 193                 break;
 194         }
 195 }
 196
 197 /*
 198  * Override the IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode
 199  * according to the "ieee754=" parameter.
 200  */
 201 static void cpu_set_nan_2008(struct cpuinfo_mips *c)
 202 {
 203         switch (ieee754) {
 204         case STRICT:
 205                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 206                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 207                 break;
 208         case LEGACY:
 209                 mips_use_nan_legacy = !!cpu_has_nan_legacy;
 210                 mips_use_nan_2008 = !cpu_has_nan_legacy;
 211                 break;
 212         case STD2008:
 213                 mips_use_nan_legacy = !cpu_has_nan_2008;
 214                 mips_use_nan_2008 = !!cpu_has_nan_2008;
 215                 break;
 216         case RELAXED:
 217                 mips_use_nan_legacy = true;
 218                 mips_use_nan_2008 = true;
 219                 break;
 220         }
 221 }
 222
 223 /*
 224  * IEEE 754 NaN encoding and ABS.fmt/NEG.fmt execution mode override
 225  * settings:
 226  *
 227  * strict:  accept binaries that request a NaN encoding supported by the FPU
 228  * legacy:  only accept legacy-NaN binaries
 229  * 2008:    only accept 2008-NaN binaries
 230  * relaxed: accept any binaries regardless of whether supported by the FPU
 231  */
 232 static int __init ieee754_setup(char *s)
 233 {
 234         if (!s)
 235                 return -1;
 236         else if (!strcmp(s, "strict"))
 237                 ieee754 = STRICT;
 238         else if (!strcmp(s, "legacy"))
 239                 ieee754 = LEGACY;
 240         else if (!strcmp(s, "2008"))
 241                 ieee754 = STD2008;
 242         else if (!strcmp(s, "relaxed"))
 243                 ieee754 = RELAXED;
 244         else
 245                 return -1;
 246
 247         if (!(boot_cpu_data.options & MIPS_CPU_FPU))
 248                 cpu_set_nofpu_2008(&boot_cpu_data);
 249         cpu_set_nan_2008(&boot_cpu_data);
 250
 251         return 0;
 252 }
 253
 254 early_param("ieee754", ieee754_setup);
 255
 256 /*
 257  * Set the FIR feature flags for the FPU emulator.
 258  */
 259 static void cpu_set_nofpu_id(struct cpuinfo_mips *c)
 260 {
 261         u32 value;
 262
 263         value = 0;
 264         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 265                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 266                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 267                 value |= MIPS_FPIR_D | MIPS_FPIR_S;
 268         if (c->isa_level & (MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 269                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6))
 270                 value |= MIPS_FPIR_F64 | MIPS_FPIR_L | MIPS_FPIR_W;
 271         if (c->options & MIPS_CPU_NAN_2008)
 272                 value |= MIPS_FPIR_HAS2008;
 273         c->fpu_id = value;
 274 }
 275
 276 /* Determined FPU emulator mask to use for the boot CPU with "nofpu".  */
 277 static unsigned int mips_nofpu_msk31;
 278
 279 /*
 280  * Set options for FPU hardware.
 281  */
 282 static void cpu_set_fpu_opts(struct cpuinfo_mips *c)
 283 {
 284         c->fpu_id = cpu_get_fpu_id();
 285         mips_nofpu_msk31 = c->fpu_msk31;
 286
 287         if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1 |
 288                             MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2 |
 289                             MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6)) {
 290                 if (c->fpu_id & MIPS_FPIR_3D)
 291                         c->ases |= MIPS_ASE_MIPS3D;
 292                 if (c->fpu_id & MIPS_FPIR_UFRP)
 293                         c->options |= MIPS_CPU_UFR;
 294                 if (c->fpu_id & MIPS_FPIR_FREP)
 295                         c->options |= MIPS_CPU_FRE;
 296         }
 297
 298         cpu_set_fpu_fcsr_mask(c);
 299         cpu_set_fpu_2008(c);
 300         cpu_set_nan_2008(c);
 301 }
 302
 303 /*
 304  * Set options for the FPU emulator.
 305  */
 306 static void cpu_set_nofpu_opts(struct cpuinfo_mips *c)
 307 {
 308         c->options &= ~MIPS_CPU_FPU;
 309         c->fpu_msk31 = mips_nofpu_msk31;
 310
 311         cpu_set_nofpu_2008(c);
 312         cpu_set_nan_2008(c);
 313         cpu_set_nofpu_id(c);
 314 }
 315
 316 static int mips_fpu_disabled;
 317
 318 static int __init fpu_disable(char *s)
 319 {
 320         cpu_set_nofpu_opts(&boot_cpu_data);
 321         mips_fpu_disabled = 1;
 322
 323         return 1;
 324 }
 325
 326 __setup("nofpu", fpu_disable);
 327
 328 int mips_dsp_disabled;
 329
 330 static int __init dsp_disable(char *s)
 331 {
 332         cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
 333         mips_dsp_disabled = 1;
 334
 335         return 1;
 336 }
 337
 338 __setup("nodsp", dsp_disable);
 339
 340 static int mips_htw_disabled;
 341
 342 static int __init htw_disable(char *s)
 343 {
 344         mips_htw_disabled = 1;
 345         cpu_data[0].options &= ~MIPS_CPU_HTW;
 346         write_c0_pwctl(read_c0_pwctl() &
 347                        ~(1 << MIPS_PWCTL_PWEN_SHIFT));
 348
 349         return 1;
 350 }
 351
 352 __setup("nohtw", htw_disable);
 353
 354 static int mips_ftlb_disabled;
 355 static int mips_has_ftlb_configured;
 356
 357 enum ftlb_flags {
 358         FTLB_EN         = 1 << 0,
 359         FTLB_SET_PROB   = 1 << 1,
 360 };
 361
 362 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags);
 363
 364 static int __init ftlb_disable(char *s)
 365 {
 366         unsigned int config4, mmuextdef;
 367
 368         /*
 369          * If the core hasn't done any FTLB configuration, there is nothing
 370          * for us to do here.
 371          */
 372         if (!mips_has_ftlb_configured)
 373                 return 1;
 374
 375         /* Disable it in the boot cpu */
 376         if (set_ftlb_enable(&cpu_data[0], 0)) {
 377                 pr_warn("Can't turn FTLB off\n");
 378                 return 1;
 379         }
 380
 381         config4 = read_c0_config4();
 382
 383         /* Check that FTLB has been disabled */
 384         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 385         /* MMUSIZEEXT == VTLB ON, FTLB OFF */
 386         if (mmuextdef == MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT) {
 387                 /* This should never happen */
 388                 pr_warn("FTLB could not be disabled!\n");
 389                 return 1;
 390         }
 391
 392         mips_ftlb_disabled = 1;
 393         mips_has_ftlb_configured = 0;
 394
 395         /*
 396          * noftlb is mainly used for debug purposes so print
 397          * an informative message instead of using pr_debug()
 398          */
 399         pr_info("FTLB has been disabled\n");
 400
 401         /*
 402          * Some of these bits are duplicated in the decode_config4.
 403          * MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT is the only possible case
 404          * once FTLB has been disabled so undo what decode_config4 did.
 405          */
 406         cpu_data[0].tlbsize -= cpu_data[0].tlbsizeftlbways *
 407                                cpu_data[0].tlbsizeftlbsets;
 408         cpu_data[0].tlbsizeftlbsets = 0;
 409         cpu_data[0].tlbsizeftlbways = 0;
 410
 411         return 1;
 412 }
 413
 414 __setup("noftlb", ftlb_disable);
 415
 416
 417 static inline void check_errata(void)
 418 {
 419         struct cpuinfo_mips *c = &current_cpu_data;
 420
 421         switch (current_cpu_type()) {
 422         case CPU_34K:
 423                 /*
 424                  * Erratum "RPS May Cause Incorrect Instruction Execution"
 425                  * This code only handles VPE0, any SMP/RTOS code
 426                  * making use of VPE1 will be responsable for that VPE.
 427                  */
 428                 if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
 429                         write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
 430                 break;
 431         default:
 432                 break;
 433         }
 434 }
 435
 436 void __init check_bugs32(void)
 437 {
 438         check_errata();
 439 }
 440
 441 /*
 442  * Probe whether cpu has config register by trying to play with
 443  * alternate cache bit and see whether it matters.
 444  * It's used by cpu_probe to distinguish between R3000A and R3081.
 445  */
 446 static inline int cpu_has_confreg(void)
 447 {
 448 #ifdef CONFIG_CPU_R3000
 449         extern unsigned long r3k_cache_size(unsigned long);
 450         unsigned long size1, size2;
 451         unsigned long cfg = read_c0_conf();
 452
 453         size1 = r3k_cache_size(ST0_ISC);
 454         write_c0_conf(cfg ^ R30XX_CONF_AC);
 455         size2 = r3k_cache_size(ST0_ISC);
 456         write_c0_conf(cfg);
 457         return size1 != size2;
 458 #else
 459         return 0;
 460 #endif
 461 }
 462
 463 static inline void set_elf_platform(int cpu, const char *plat)
 464 {
 465         if (cpu == 0)
 466                 __elf_platform = plat;
 467 }
 468
 469 static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
 470 {
 471 #ifdef __NEED_VMBITS_PROBE
 472         write_c0_entryhi(0x3fffffffffffe000ULL);
 473         back_to_back_c0_hazard();
 474         c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
 475 #endif
 476 }
 477
 478 static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
 479 {
 480         switch (isa) {
 481         case MIPS_CPU_ISA_M64R2:
 482                 c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
 483         case MIPS_CPU_ISA_M64R1:
 484                 c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
 485         case MIPS_CPU_ISA_V:
 486                 c->isa_level |= MIPS_CPU_ISA_V;
 487         case MIPS_CPU_ISA_IV:
 488                 c->isa_level |= MIPS_CPU_ISA_IV;
 489         case MIPS_CPU_ISA_III:
 490                 c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
 491                 break;
 492
 493         /* R6 incompatible with everything else */
 494         case MIPS_CPU_ISA_M64R6:
 495                 c->isa_level |= MIPS_CPU_ISA_M32R6 | MIPS_CPU_ISA_M64R6;
 496         case MIPS_CPU_ISA_M32R6:
 497                 c->isa_level |= MIPS_CPU_ISA_M32R6;
 498                 /* Break here so we don't add incompatible ISAs */
 499                 break;
 500         case MIPS_CPU_ISA_M32R2:
 501                 c->isa_level |= MIPS_CPU_ISA_M32R2;
 502         case MIPS_CPU_ISA_M32R1:
 503                 c->isa_level |= MIPS_CPU_ISA_M32R1;
 504         case MIPS_CPU_ISA_II:
 505                 c->isa_level |= MIPS_CPU_ISA_II;
 506                 break;
 507         }
 508 }
 509
 510 static char unknown_isa[] = KERN_ERR \
 511         "Unsupported ISA type, c0.config0: %d.";
 512
 513 static unsigned int calculate_ftlb_probability(struct cpuinfo_mips *c)
 514 {
 515
 516         unsigned int probability = c->tlbsize / c->tlbsizevtlb;
 517
 518         /*
 519          * 0 = All TLBWR instructions go to FTLB
 520          * 1 = 15:1: For every 16 TBLWR instructions, 15 go to the
 521          * FTLB and 1 goes to the VTLB.
 522          * 2 = 7:1: As above with 7:1 ratio.
 523          * 3 = 3:1: As above with 3:1 ratio.
 524          *
 525          * Use the linear midpoint as the probability threshold.
 526          */
 527         if (probability >= 12)
 528                 return 1;
 529         else if (probability >= 6)
 530                 return 2;
 531         else
 532                 /*
 533                  * So FTLB is less than 4 times bigger than VTLB.
 534                  * A 3:1 ratio can still be useful though.
 535                  */
 536                 return 3;
 537 }
 538
 539 static int set_ftlb_enable(struct cpuinfo_mips *c, enum ftlb_flags flags)
 540 {
 541         unsigned int config;
 542
 543         /* It's implementation dependent how the FTLB can be enabled */
 544         switch (c->cputype) {
 545         case CPU_PROAPTIV:
 546         case CPU_P5600:
 547         case CPU_P6600:
 548                 /* proAptiv & related cores use Config6 to enable the FTLB */
 549                 config = read_c0_config6();
 550
 551                 if (flags & FTLB_EN)
 552                         config |= MIPS_CONF6_FTLBEN;
 553                 else
 554                         config &= ~MIPS_CONF6_FTLBEN;
 555
 556                 if (flags & FTLB_SET_PROB) {
 557                         config &= ~(3 << MIPS_CONF6_FTLBP_SHIFT);
 558                         config |= calculate_ftlb_probability(c)
 559                                   << MIPS_CONF6_FTLBP_SHIFT;
 560                 }
 561
 562                 write_c0_config6(config);
 563                 back_to_back_c0_hazard();
 564                 break;
 565         case CPU_I6400:
 566                 /* There's no way to disable the FTLB */
 567                 if (!(flags & FTLB_EN))
 568                         return 1;
 569                 return 0;
 570         case CPU_LOONGSON3:
 571                 /* Flush ITLB, DTLB, VTLB and FTLB */
 572                 write_c0_diag(LOONGSON_DIAG_ITLB | LOONGSON_DIAG_DTLB |
 573                               LOONGSON_DIAG_VTLB | LOONGSON_DIAG_FTLB);
 574                 /* Loongson-3 cores use Config6 to enable the FTLB */
 575                 config = read_c0_config6();
 576                 if (flags & FTLB_EN)
 577                         /* Enable FTLB */
 578                         write_c0_config6(config & ~MIPS_CONF6_FTLBDIS);
 579                 else
 580                         /* Disable FTLB */
 581                         write_c0_config6(config | MIPS_CONF6_FTLBDIS);
 582                 break;
 583         default:
 584                 return 1;
 585         }
 586
 587         return 0;
 588 }
 589
 590 static inline unsigned int decode_config0(struct cpuinfo_mips *c)
 591 {
 592         unsigned int config0;
 593         int isa, mt;
 594
 595         config0 = read_c0_config();
 596
 597         /*
 598          * Look for Standard TLB or Dual VTLB and FTLB
 599          */
 600         mt = config0 & MIPS_CONF_MT;
 601         if (mt == MIPS_CONF_MT_TLB)
 602                 c->options |= MIPS_CPU_TLB;
 603         else if (mt == MIPS_CONF_MT_FTLB)
 604                 c->options |= MIPS_CPU_TLB | MIPS_CPU_FTLB;
 605
 606         isa = (config0 & MIPS_CONF_AT) >> 13;
 607         switch (isa) {
 608         case 0:
 609                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 610                 case 0:
 611                         set_isa(c, MIPS_CPU_ISA_M32R1);
 612                         break;
 613                 case 1:
 614                         set_isa(c, MIPS_CPU_ISA_M32R2);
 615                         break;
 616                 case 2:
 617                         set_isa(c, MIPS_CPU_ISA_M32R6);
 618                         break;
 619                 default:
 620                         goto unknown;
 621                 }
 622                 break;
 623         case 2:
 624                 switch ((config0 & MIPS_CONF_AR) >> 10) {
 625                 case 0:
 626                         set_isa(c, MIPS_CPU_ISA_M64R1);
 627                         break;
 628                 case 1:
 629                         set_isa(c, MIPS_CPU_ISA_M64R2);
 630                         break;
 631                 case 2:
 632                         set_isa(c, MIPS_CPU_ISA_M64R6);
 633                         break;
 634                 default:
 635                         goto unknown;
 636                 }
 637                 break;
 638         default:
 639                 goto unknown;
 640         }
 641
 642         return config0 & MIPS_CONF_M;
 643
 644 unknown:
 645         panic(unknown_isa, config0);
 646 }
 647
 648 static inline unsigned int decode_config1(struct cpuinfo_mips *c)
 649 {
 650         unsigned int config1;
 651
 652         config1 = read_c0_config1();
 653
 654         if (config1 & MIPS_CONF1_MD)
 655                 c->ases |= MIPS_ASE_MDMX;
 656         if (config1 & MIPS_CONF1_PC)
 657                 c->options |= MIPS_CPU_PERF;
 658         if (config1 & MIPS_CONF1_WR)
 659                 c->options |= MIPS_CPU_WATCH;
 660         if (config1 & MIPS_CONF1_CA)
 661                 c->ases |= MIPS_ASE_MIPS16;
 662         if (config1 & MIPS_CONF1_EP)
 663                 c->options |= MIPS_CPU_EJTAG;
 664         if (config1 & MIPS_CONF1_FP) {
 665                 c->options |= MIPS_CPU_FPU;
 666                 c->options |= MIPS_CPU_32FPR;
 667         }
 668         if (cpu_has_tlb) {
 669                 c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
 670                 c->tlbsizevtlb = c->tlbsize;
 671                 c->tlbsizeftlbsets = 0;
 672         }
 673
 674         return config1 & MIPS_CONF_M;
 675 }
 676
 677 static inline unsigned int decode_config2(struct cpuinfo_mips *c)
 678 {
 679         unsigned int config2;
 680
 681         config2 = read_c0_config2();
 682
 683         if (config2 & MIPS_CONF2_SL)
 684                 c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
 685
 686         return config2 & MIPS_CONF_M;
 687 }
 688
 689 static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 690 {
 691         unsigned int config3;
 692
 693         config3 = read_c0_config3();
 694
 695         if (config3 & MIPS_CONF3_SM) {
 696                 c->ases |= MIPS_ASE_SMARTMIPS;
 697                 c->options |= MIPS_CPU_RIXI | MIPS_CPU_CTXTC;
 698         }
 699         if (config3 & MIPS_CONF3_RXI)
 700                 c->options |= MIPS_CPU_RIXI;
 701         if (config3 & MIPS_CONF3_CTXTC)
 702                 c->options |= MIPS_CPU_CTXTC;
 703         if (config3 & MIPS_CONF3_DSP)
 704                 c->ases |= MIPS_ASE_DSP;
 705         if (config3 & MIPS_CONF3_DSP2P) {
 706                 c->ases |= MIPS_ASE_DSP2P;
 707                 if (cpu_has_mips_r6)
 708                         c->ases |= MIPS_ASE_DSP3;
 709         }
 710         if (config3 & MIPS_CONF3_VINT)
 711                 c->options |= MIPS_CPU_VINT;
 712         if (config3 & MIPS_CONF3_VEIC)
 713                 c->options |= MIPS_CPU_VEIC;
 714         if (config3 & MIPS_CONF3_LPA)
 715                 c->options |= MIPS_CPU_LPA;
 716         if (config3 & MIPS_CONF3_MT)
 717                 c->ases |= MIPS_ASE_MIPSMT;
 718         if (config3 & MIPS_CONF3_ULRI)
 719                 c->options |= MIPS_CPU_ULRI;
 720         if (config3 & MIPS_CONF3_ISA)
 721                 c->options |= MIPS_CPU_MICROMIPS;
 722         if (config3 & MIPS_CONF3_VZ)
 723                 c->ases |= MIPS_ASE_VZ;
 724         if (config3 & MIPS_CONF3_SC)
 725                 c->options |= MIPS_CPU_SEGMENTS;
 726         if (config3 & MIPS_CONF3_BI)
 727                 c->options |= MIPS_CPU_BADINSTR;
 728         if (config3 & MIPS_CONF3_BP)
 729                 c->options |= MIPS_CPU_BADINSTRP;
 730         if (config3 & MIPS_CONF3_MSA)
 731                 c->ases |= MIPS_ASE_MSA;
 732         if (config3 & MIPS_CONF3_PW) {
 733                 c->htw_seq = 0;
 734                 c->options |= MIPS_CPU_HTW;
 735         }
 736         if (config3 & MIPS_CONF3_CDMM)
 737                 c->options |= MIPS_CPU_CDMM;
 738         if (config3 & MIPS_CONF3_SP)
 739                 c->options |= MIPS_CPU_SP;
 740
 741         return config3 & MIPS_CONF_M;
 742 }
 743
 744 static inline unsigned int decode_config4(struct cpuinfo_mips *c)
 745 {
 746         unsigned int config4;
 747         unsigned int newcf4;
 748         unsigned int mmuextdef;
 749         unsigned int ftlb_page = MIPS_CONF4_FTLBPAGESIZE;
 750         unsigned long asid_mask;
 751
 752         config4 = read_c0_config4();
 753
 754         if (cpu_has_tlb) {
 755                 if (((config4 & MIPS_CONF4_IE) >> 29) == 2)
 756                         c->options |= MIPS_CPU_TLBINV;
 757
 758                 /*
 759                  * R6 has dropped the MMUExtDef field from config4.
 760                  * On R6 the fields always describe the FTLB, and only if it is
 761                  * present according to Config.MT.
 762                  */
 763                 if (!cpu_has_mips_r6)
 764                         mmuextdef = config4 & MIPS_CONF4_MMUEXTDEF;
 765                 else if (cpu_has_ftlb)
 766                         mmuextdef = MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT;
 767                 else
 768                         mmuextdef = 0;
 769
 770                 switch (mmuextdef) {
 771                 case MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT:
 772                         c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
 773                         c->tlbsizevtlb = c->tlbsize;
 774                         break;
 775                 case MIPS_CONF4_MMUEXTDEF_VTLBSIZEEXT:
 776                         c->tlbsizevtlb +=
 777                                 ((config4 & MIPS_CONF4_VTLBSIZEEXT) >>
 778                                   MIPS_CONF4_VTLBSIZEEXT_SHIFT) * 0x40;
 779                         c->tlbsize = c->tlbsizevtlb;
 780                         ftlb_page = MIPS_CONF4_VFTLBPAGESIZE;
 781                         /* fall through */
 782                 case MIPS_CONF4_MMUEXTDEF_FTLBSIZEEXT:
 783                         if (mips_ftlb_disabled)
 784                                 break;
 785                         newcf4 = (config4 & ~ftlb_page) |
 786                                 (page_size_ftlb(mmuextdef) <<
 787                                  MIPS_CONF4_FTLBPAGESIZE_SHIFT);
 788                         write_c0_config4(newcf4);
 789                         back_to_back_c0_hazard();
 790                         config4 = read_c0_config4();
 791                         if (config4 != newcf4) {
 792                                 pr_err("PAGE_SIZE 0x%lx is not supported by FTLB (config4=0x%x)\n",
 793                                        PAGE_SIZE, config4);
 794                                 /* Switch FTLB off */
 795                                 set_ftlb_enable(c, 0);
 796                                 mips_ftlb_disabled = 1;
 797                                 break;
 798                         }
 799                         c->tlbsizeftlbsets = 1 <<
 800                                 ((config4 & MIPS_CONF4_FTLBSETS) >>
 801                                  MIPS_CONF4_FTLBSETS_SHIFT);
 802                         c->tlbsizeftlbways = ((config4 & MIPS_CONF4_FTLBWAYS) >>
 803                                               MIPS_CONF4_FTLBWAYS_SHIFT) + 2;
 804                         c->tlbsize += c->tlbsizeftlbways * c->tlbsizeftlbsets;
 805                         mips_has_ftlb_configured = 1;
 806                         break;
 807                 }
 808         }
 809
 810         c->kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
 811                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
 812
 813         asid_mask = MIPS_ENTRYHI_ASID;
 814         if (config4 & MIPS_CONF4_AE)
 815                 asid_mask |= MIPS_ENTRYHI_ASIDX;
 816         set_cpu_asid_mask(c, asid_mask);
 817
 818         /*
 819          * Warn if the computed ASID mask doesn't match the mask the kernel
 820          * is built for. This may indicate either a serious problem or an
 821          * easy optimisation opportunity, but either way should be addressed.
 822          */
 823         WARN_ON(asid_mask != cpu_asid_mask(c));
 824
 825         return config4 & MIPS_CONF_M;
 826 }
 827
 828 static inline unsigned int decode_config5(struct cpuinfo_mips *c)
 829 {
 830         unsigned int config5;
 831
 832         config5 = read_c0_config5();
 833         config5 &= ~(MIPS_CONF5_UFR | MIPS_CONF5_UFE);
 834         write_c0_config5(config5);
 835
 836         if (config5 & MIPS_CONF5_EVA)
 837                 c->options |= MIPS_CPU_EVA;
 838         if (config5 & MIPS_CONF5_MRP)
 839                 c->options |= MIPS_CPU_MAAR;
 840         if (config5 & MIPS_CONF5_LLB)
 841                 c->options |= MIPS_CPU_RW_LLB;
 842         if (config5 & MIPS_CONF5_MVH)
 843                 c->options |= MIPS_CPU_MVH;
 844         if (cpu_has_mips_r6 && (config5 & MIPS_CONF5_VP))
 845                 c->options |= MIPS_CPU_VP;
 846
 847         return config5 & MIPS_CONF_M;
 848 }
 849
 850 static void decode_configs(struct cpuinfo_mips *c)
 851 {
 852         int ok;
 853
 854         /* MIPS32 or MIPS64 compliant CPU.  */
 855         c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
 856                      MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 857
 858         c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 859
 860         /* Enable FTLB if present and not disabled */
 861         set_ftlb_enable(c, mips_ftlb_disabled ? 0 : FTLB_EN);
 862
 863         ok = decode_config0(c);                 /* Read Config registers.  */
 864         BUG_ON(!ok);                            /* Arch spec violation!  */
 865         if (ok)
 866                 ok = decode_config1(c);
 867         if (ok)
 868                 ok = decode_config2(c);
 869         if (ok)
 870                 ok = decode_config3(c);
 871         if (ok)
 872                 ok = decode_config4(c);
 873         if (ok)
 874                 ok = decode_config5(c);
 875
 876         /* Probe the EBase.WG bit */
 877         if (cpu_has_mips_r2_r6) {
 878                 u64 ebase;
 879                 unsigned int status;
 880
 881                 /* {read,write}_c0_ebase_64() may be UNDEFINED prior to r6 */
 882                 ebase = cpu_has_mips64r6 ? read_c0_ebase_64()
 883                                          : (s32)read_c0_ebase();
 884                 if (ebase & MIPS_EBASE_WG) {
 885                         /* WG bit already set, we can avoid the clumsy probe */
 886                         c->options |= MIPS_CPU_EBASE_WG;
 887                 } else {
 888                         /* Its UNDEFINED to change EBase while BEV=0 */
 889                         status = read_c0_status();
 890                         write_c0_status(status | ST0_BEV);
 891                         irq_enable_hazard();
 892                         /*
 893                          * On pre-r6 cores, this may well clobber the upper bits
 894                          * of EBase. This is hard to avoid without potentially
 895                          * hitting UNDEFINED dm*c0 behaviour if EBase is 32-bit.
 896                          */
 897                         if (cpu_has_mips64r6)
 898                                 write_c0_ebase_64(ebase | MIPS_EBASE_WG);
 899                         else
 900                                 write_c0_ebase(ebase | MIPS_EBASE_WG);
 901                         back_to_back_c0_hazard();
 902                         /* Restore BEV */
 903                         write_c0_status(status);
 904                         if (read_c0_ebase() & MIPS_EBASE_WG) {
 905                                 c->options |= MIPS_CPU_EBASE_WG;
 906                                 write_c0_ebase(ebase);
 907                         }
 908                 }
 909         }
 910
 911         /* configure the FTLB write probability */
 912         set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
 913
 914         mips_probe_watch_registers(c);
 915
 916 #ifndef CONFIG_MIPS_CPS
 917         if (cpu_has_mips_r2_r6) {
 918                 c->core = get_ebase_cpunum();
 919                 if (cpu_has_mipsmt)
 920                         c->core >>= fls(core_nvpes()) - 1;
 921         }
 922 #endif
 923 }
 924
 925 /*
 926  * Probe for certain guest capabilities by writing config bits and reading back.
 927  * Finally write back the original value.
 928  */
 929 #define probe_gc0_config(name, maxconf, bits)                           \
 930 do {                                                                    \
 931         unsigned int tmp;                                               \
 932         tmp = read_gc0_##name();                                        \
 933         write_gc0_##name(tmp | (bits));                                 \
 934         back_to_back_c0_hazard();                                       \
 935         maxconf = read_gc0_##name();                                    \
 936         write_gc0_##name(tmp);                                          \
 937 } while (0)
 938
 939 /*
 940  * Probe for dynamic guest capabilities by changing certain config bits and
 941  * reading back to see if they change. Finally write back the original value.
 942  */
 943 #define probe_gc0_config_dyn(name, maxconf, dynconf, bits)              \
 944 do {                                                                    \
 945         maxconf = read_gc0_##name();                                    \
 946         write_gc0_##name(maxconf ^ (bits));                             \
 947         back_to_back_c0_hazard();                                       \
 948         dynconf = maxconf ^ read_gc0_##name();                          \
 949         write_gc0_##name(maxconf);                                      \
 950         maxconf |= dynconf;                                             \
 951 } while (0)
 952
 953 static inline unsigned int decode_guest_config0(struct cpuinfo_mips *c)
 954 {
 955         unsigned int config0;
 956
 957         probe_gc0_config(config, config0, MIPS_CONF_M);
 958
 959         if (config0 & MIPS_CONF_M)
 960                 c->guest.conf |= BIT(1);
 961         return config0 & MIPS_CONF_M;
 962 }
 963
 964 static inline unsigned int decode_guest_config1(struct cpuinfo_mips *c)
 965 {
 966         unsigned int config1, config1_dyn;
 967
 968         probe_gc0_config_dyn(config1, config1, config1_dyn,
 969                              MIPS_CONF_M | MIPS_CONF1_PC | MIPS_CONF1_WR |
 970                              MIPS_CONF1_FP);
 971
 972         if (config1 & MIPS_CONF1_FP)
 973                 c->guest.options |= MIPS_CPU_FPU;
 974         if (config1_dyn & MIPS_CONF1_FP)
 975                 c->guest.options_dyn |= MIPS_CPU_FPU;
 976
 977         if (config1 & MIPS_CONF1_WR)
 978                 c->guest.options |= MIPS_CPU_WATCH;
 979         if (config1_dyn & MIPS_CONF1_WR)
 980                 c->guest.options_dyn |= MIPS_CPU_WATCH;
 981
 982         if (config1 & MIPS_CONF1_PC)
 983                 c->guest.options |= MIPS_CPU_PERF;
 984         if (config1_dyn & MIPS_CONF1_PC)
 985                 c->guest.options_dyn |= MIPS_CPU_PERF;
 986
 987         if (config1 & MIPS_CONF_M)
 988                 c->guest.conf |= BIT(2);
 989         return config1 & MIPS_CONF_M;
 990 }
 991
 992 static inline unsigned int decode_guest_config2(struct cpuinfo_mips *c)
 993 {
 994         unsigned int config2;
 995
 996         probe_gc0_config(config2, config2, MIPS_CONF_M);
 997
 998         if (config2 & MIPS_CONF_M)
 999                 c->guest.conf |= BIT(3);
1000         return config2 & MIPS_CONF_M;
1001 }
1002
1003 static inline unsigned int decode_guest_config3(struct cpuinfo_mips *c)
1004 {
1005         unsigned int config3, config3_dyn;
1006
1007         probe_gc0_config_dyn(config3, config3, config3_dyn,
1008                              MIPS_CONF_M | MIPS_CONF3_MSA | MIPS_CONF3_ULRI |
1009                              MIPS_CONF3_CTXTC);
1010
1011         if (config3 & MIPS_CONF3_CTXTC)
1012                 c->guest.options |= MIPS_CPU_CTXTC;
1013         if (config3_dyn & MIPS_CONF3_CTXTC)
1014                 c->guest.options_dyn |= MIPS_CPU_CTXTC;
1015
1016         if (config3 & MIPS_CONF3_PW)
1017                 c->guest.options |= MIPS_CPU_HTW;
1018
1019         if (config3 & MIPS_CONF3_ULRI)
1020                 c->guest.options |= MIPS_CPU_ULRI;
1021
1022         if (config3 & MIPS_CONF3_SC)
1023                 c->guest.options |= MIPS_CPU_SEGMENTS;
1024
1025         if (config3 & MIPS_CONF3_BI)
1026                 c->guest.options |= MIPS_CPU_BADINSTR;
1027         if (config3 & MIPS_CONF3_BP)
1028                 c->guest.options |= MIPS_CPU_BADINSTRP;
1029
1030         if (config3 & MIPS_CONF3_MSA)
1031                 c->guest.ases |= MIPS_ASE_MSA;
1032         if (config3_dyn & MIPS_CONF3_MSA)
1033                 c->guest.ases_dyn |= MIPS_ASE_MSA;
1034
1035         if (config3 & MIPS_CONF_M)
1036                 c->guest.conf |= BIT(4);
1037         return config3 & MIPS_CONF_M;
1038 }
1039
1040 static inline unsigned int decode_guest_config4(struct cpuinfo_mips *c)
1041 {
1042         unsigned int config4;
1043
1044         probe_gc0_config(config4, config4,
1045                          MIPS_CONF_M | MIPS_CONF4_KSCREXIST);
1046
1047         c->guest.kscratch_mask = (config4 & MIPS_CONF4_KSCREXIST)
1048                                 >> MIPS_CONF4_KSCREXIST_SHIFT;
1049
1050         if (config4 & MIPS_CONF_M)
1051                 c->guest.conf |= BIT(5);
1052         return config4 & MIPS_CONF_M;
1053 }
1054
1055 static inline unsigned int decode_guest_config5(struct cpuinfo_mips *c)
1056 {
1057         unsigned int config5, config5_dyn;
1058
1059         probe_gc0_config_dyn(config5, config5, config5_dyn,
1060                          MIPS_CONF_M | MIPS_CONF5_MVH | MIPS_CONF5_MRP);
1061
1062         if (config5 & MIPS_CONF5_MRP)
1063                 c->guest.options |= MIPS_CPU_MAAR;
1064         if (config5_dyn & MIPS_CONF5_MRP)
1065                 c->guest.options_dyn |= MIPS_CPU_MAAR;
1066
1067         if (config5 & MIPS_CONF5_LLB)
1068                 c->guest.options |= MIPS_CPU_RW_LLB;
1069
1070         if (config5 & MIPS_CONF5_MVH)
1071                 c->guest.options |= MIPS_CPU_MVH;
1072
1073         if (config5 & MIPS_CONF_M)
1074                 c->guest.conf |= BIT(6);
1075         return config5 & MIPS_CONF_M;
1076 }
1077
1078 static inline void decode_guest_configs(struct cpuinfo_mips *c)
1079 {
1080         unsigned int ok;
1081
1082         ok = decode_guest_config0(c);
1083         if (ok)
1084                 ok = decode_guest_config1(c);
1085         if (ok)
1086                 ok = decode_guest_config2(c);
1087         if (ok)
1088                 ok = decode_guest_config3(c);
1089         if (ok)
1090                 ok = decode_guest_config4(c);
1091         if (ok)
1092                 decode_guest_config5(c);
1093 }
1094
1095 static inline void cpu_probe_guestctl0(struct cpuinfo_mips *c)
1096 {
1097         unsigned int guestctl0, temp;
1098
1099         guestctl0 = read_c0_guestctl0();
1100
1101         if (guestctl0 & MIPS_GCTL0_G0E)
1102                 c->options |= MIPS_CPU_GUESTCTL0EXT;
1103         if (guestctl0 & MIPS_GCTL0_G1)
1104                 c->options |= MIPS_CPU_GUESTCTL1;
1105         if (guestctl0 & MIPS_GCTL0_G2)
1106                 c->options |= MIPS_CPU_GUESTCTL2;
1107         if (!(guestctl0 & MIPS_GCTL0_RAD)) {
1108                 c->options |= MIPS_CPU_GUESTID;
1109
1110                 /*
1111                  * Probe for Direct Root to Guest (DRG). Set GuestCtl1.RID = 0
1112                  * first, otherwise all data accesses will be fully virtualised
1113                  * as if they were performed by guest mode.
1114                  */
1115                 write_c0_guestctl1(0);
1116                 tlbw_use_hazard();
1117
1118                 write_c0_guestctl0(guestctl0 | MIPS_GCTL0_DRG);
1119                 back_to_back_c0_hazard();
1120                 temp = read_c0_guestctl0();
1121
1122                 if (temp & MIPS_GCTL0_DRG) {
1123                         write_c0_guestctl0(guestctl0);
1124                         c->options |= MIPS_CPU_DRG;
1125                 }
1126         }
1127 }
1128
1129 static inline void cpu_probe_guestctl1(struct cpuinfo_mips *c)
1130 {
1131         if (cpu_has_guestid) {
1132                 /* determine the number of bits of GuestID available */
1133                 write_c0_guestctl1(MIPS_GCTL1_ID);
1134                 back_to_back_c0_hazard();
1135                 c->guestid_mask = (read_c0_guestctl1() & MIPS_GCTL1_ID)
1136                                                 >> MIPS_GCTL1_ID_SHIFT;
1137                 write_c0_guestctl1(0);
1138         }
1139 }
1140
1141 static inline void cpu_probe_gtoffset(struct cpuinfo_mips *c)
1142 {
1143         /* determine the number of bits of GTOffset available */
1144         write_c0_gtoffset(0xffffffff);
1145         back_to_back_c0_hazard();
1146         c->gtoffset_mask = read_c0_gtoffset();
1147         write_c0_gtoffset(0);
1148 }
1149
1150 static inline void cpu_probe_vz(struct cpuinfo_mips *c)
1151 {
1152         cpu_probe_guestctl0(c);
1153         if (cpu_has_guestctl1)
1154                 cpu_probe_guestctl1(c);
1155
1156         cpu_probe_gtoffset(c);
1157
1158         decode_guest_configs(c);
1159 }
1160
1161 #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
1162                 | MIPS_CPU_COUNTER)
1163
1164 static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
1165 {
1166         switch (c->processor_id & PRID_IMP_MASK) {
1167         case PRID_IMP_R2000:
1168                 c->cputype = CPU_R2000;
1169                 __cpu_name[cpu] = "R2000";
1170                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1171                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1172                              MIPS_CPU_NOFPUEX;
1173                 if (__cpu_has_fpu())
1174                         c->options |= MIPS_CPU_FPU;
1175                 c->tlbsize = 64;
1176                 break;
1177         case PRID_IMP_R3000:
1178                 if ((c->processor_id & PRID_REV_MASK) == PRID_REV_R3000A) {
1179                         if (cpu_has_confreg()) {
1180                                 c->cputype = CPU_R3081E;
1181                                 __cpu_name[cpu] = "R3081";
1182                         } else {
1183                                 c->cputype = CPU_R3000A;
1184                                 __cpu_name[cpu] = "R3000A";
1185                         }
1186                 } else {
1187                         c->cputype = CPU_R3000;
1188                         __cpu_name[cpu] = "R3000";
1189                 }
1190                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1191                 c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
1192                              MIPS_CPU_NOFPUEX;
1193                 if (__cpu_has_fpu())
1194                         c->options |= MIPS_CPU_FPU;
1195                 c->tlbsize = 64;
1196                 break;
1197         case PRID_IMP_R4000:
1198                 if (read_c0_config() & CONF_SC) {
1199                         if ((c->processor_id & PRID_REV_MASK) >=
1200                             PRID_REV_R4400) {
1201                                 c->cputype = CPU_R4400PC;
1202                                 __cpu_name[cpu] = "R4400PC";
1203                         } else {
1204                                 c->cputype = CPU_R4000PC;
1205                                 __cpu_name[cpu] = "R4000PC";
1206                         }
1207                 } else {
1208                         int cca = read_c0_config() & CONF_CM_CMASK;
1209                         int mc;
1210
1211                         /*
1212                          * SC and MC versions can't be reliably told apart,
1213                          * but only the latter support coherent caching
1214                          * modes so assume the firmware has set the KSEG0
1215                          * coherency attribute reasonably (if uncached, we
1216                          * assume SC).
1217                          */
1218                         switch (cca) {
1219                         case CONF_CM_CACHABLE_CE:
1220                         case CONF_CM_CACHABLE_COW:
1221                         case CONF_CM_CACHABLE_CUW:
1222                                 mc = 1;
1223                                 break;
1224                         default:
1225                                 mc = 0;
1226                                 break;
1227                         }
1228                         if ((c->processor_id & PRID_REV_MASK) >=
1229                             PRID_REV_R4400) {
1230                                 c->cputype = mc ? CPU_R4400MC : CPU_R4400SC;
1231                                 __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC";
1232                         } else {
1233                                 c->cputype = mc ? CPU_R4000MC : CPU_R4000SC;
1234                                 __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC";
1235                         }
1236                 }
1237
1238                 set_isa(c, MIPS_CPU_ISA_III);
1239                 c->fpu_msk31 |= FPU_CSR_CONDX;
1240                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1241                              MIPS_CPU_WATCH | MIPS_CPU_VCE |
1242                              MIPS_CPU_LLSC;
1243                 c->tlbsize = 48;
1244                 break;
1245         case PRID_IMP_VR41XX:
1246                 set_isa(c, MIPS_CPU_ISA_III);
1247                 c->fpu_msk31 |= FPU_CSR_CONDX;
1248                 c->options = R4K_OPTS;
1249                 c->tlbsize = 32;
1250                 switch (c->processor_id & 0xf0) {
1251                 case PRID_REV_VR4111:
1252                         c->cputype = CPU_VR4111;
1253                         __cpu_name[cpu] = "NEC VR4111";
1254                         break;
1255                 case PRID_REV_VR4121:
1256                         c->cputype = CPU_VR4121;
1257                         __cpu_name[cpu] = "NEC VR4121";
1258                         break;
1259                 case PRID_REV_VR4122:
1260                         if ((c->processor_id & 0xf) < 0x3) {
1261                                 c->cputype = CPU_VR4122;
1262                                 __cpu_name[cpu] = "NEC VR4122";
1263                         } else {
1264                                 c->cputype = CPU_VR4181A;
1265                                 __cpu_name[cpu] = "NEC VR4181A";
1266                         }
1267                         break;
1268                 case PRID_REV_VR4130:
1269                         if ((c->processor_id & 0xf) < 0x4) {
1270                                 c->cputype = CPU_VR4131;
1271                                 __cpu_name[cpu] = "NEC VR4131";
1272                         } else {
1273                                 c->cputype = CPU_VR4133;
1274                                 c->options |= MIPS_CPU_LLSC;
1275                                 __cpu_name[cpu] = "NEC VR4133";
1276                         }
1277                         break;
1278                 default:
1279                         printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
1280                         c->cputype = CPU_VR41XX;
1281                         __cpu_name[cpu] = "NEC Vr41xx";
1282                         break;
1283                 }
1284                 break;
1285         case PRID_IMP_R4300:
1286                 c->cputype = CPU_R4300;
1287                 __cpu_name[cpu] = "R4300";
1288                 set_isa(c, MIPS_CPU_ISA_III);
1289                 c->fpu_msk31 |= FPU_CSR_CONDX;
1290                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1291                              MIPS_CPU_LLSC;
1292                 c->tlbsize = 32;
1293                 break;
1294         case PRID_IMP_R4600:
1295                 c->cputype = CPU_R4600;
1296                 __cpu_name[cpu] = "R4600";
1297                 set_isa(c, MIPS_CPU_ISA_III);
1298                 c->fpu_msk31 |= FPU_CSR_CONDX;
1299                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1300                              MIPS_CPU_LLSC;
1301                 c->tlbsize = 48;
1302                 break;
1303         #if 0
1304         case PRID_IMP_R4650:
1305                 /*
1306                  * This processor doesn't have an MMU, so it's not
1307                  * "real easy" to run Linux on it. It is left purely
1308                  * for documentation.  Commented out because it shares
1309                  * it's c0_prid id number with the TX3900.
1310                  */
1311                 c->cputype = CPU_R4650;
1312                 __cpu_name[cpu] = "R4650";
1313                 set_isa(c, MIPS_CPU_ISA_III);
1314                 c->fpu_msk31 |= FPU_CSR_CONDX;
1315                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
1316                 c->tlbsize = 48;
1317                 break;
1318         #endif
1319         case PRID_IMP_TX39:
1320                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1321                 c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
1322
1323                 if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
1324                         c->cputype = CPU_TX3927;
1325                         __cpu_name[cpu] = "TX3927";
1326                         c->tlbsize = 64;
1327                 } else {
1328                         switch (c->processor_id & PRID_REV_MASK) {
1329                         case PRID_REV_TX3912:
1330                                 c->cputype = CPU_TX3912;
1331                                 __cpu_name[cpu] = "TX3912";
1332                                 c->tlbsize = 32;
1333                                 break;
1334                         case PRID_REV_TX3922:
1335                                 c->cputype = CPU_TX3922;
1336                                 __cpu_name[cpu] = "TX3922";
1337                                 c->tlbsize = 64;
1338                                 break;
1339                         }
1340                 }
1341                 break;
1342         case PRID_IMP_R4700:
1343                 c->cputype = CPU_R4700;
1344                 __cpu_name[cpu] = "R4700";
1345                 set_isa(c, MIPS_CPU_ISA_III);
1346                 c->fpu_msk31 |= FPU_CSR_CONDX;
1347                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1348                              MIPS_CPU_LLSC;
1349                 c->tlbsize = 48;
1350                 break;
1351         case PRID_IMP_TX49:
1352                 c->cputype = CPU_TX49XX;
1353                 __cpu_name[cpu] = "R49XX";
1354                 set_isa(c, MIPS_CPU_ISA_III);
1355                 c->fpu_msk31 |= FPU_CSR_CONDX;
1356                 c->options = R4K_OPTS | MIPS_CPU_LLSC;
1357                 if (!(c->processor_id & 0x08))
1358                         c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
1359                 c->tlbsize = 48;
1360                 break;
1361         case PRID_IMP_R5000:
1362                 c->cputype = CPU_R5000;
1363                 __cpu_name[cpu] = "R5000";
1364                 set_isa(c, MIPS_CPU_ISA_IV);
1365                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1366                              MIPS_CPU_LLSC;
1367                 c->tlbsize = 48;
1368                 break;
1369         case PRID_IMP_R5432:
1370                 c->cputype = CPU_R5432;
1371                 __cpu_name[cpu] = "R5432";
1372                 set_isa(c, MIPS_CPU_ISA_IV);
1373                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1374                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1375                 c->tlbsize = 48;
1376                 break;
1377         case PRID_IMP_R5500:
1378                 c->cputype = CPU_R5500;
1379                 __cpu_name[cpu] = "R5500";
1380                 set_isa(c, MIPS_CPU_ISA_IV);
1381                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1382                              MIPS_CPU_WATCH | MIPS_CPU_LLSC;
1383                 c->tlbsize = 48;
1384                 break;
1385         case PRID_IMP_NEVADA:
1386                 c->cputype = CPU_NEVADA;
1387                 __cpu_name[cpu] = "Nevada";
1388                 set_isa(c, MIPS_CPU_ISA_IV);
1389                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1390                              MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
1391                 c->tlbsize = 48;
1392                 break;
1393         case PRID_IMP_R6000:
1394                 c->cputype = CPU_R6000;
1395                 __cpu_name[cpu] = "R6000";
1396                 set_isa(c, MIPS_CPU_ISA_II);
1397                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1398                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1399                              MIPS_CPU_LLSC;
1400                 c->tlbsize = 32;
1401                 break;
1402         case PRID_IMP_R6000A:
1403                 c->cputype = CPU_R6000A;
1404                 __cpu_name[cpu] = "R6000A";
1405                 set_isa(c, MIPS_CPU_ISA_II);
1406                 c->fpu_msk31 |= FPU_CSR_CONDX | FPU_CSR_FS;
1407                 c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
1408                              MIPS_CPU_LLSC;
1409                 c->tlbsize = 32;
1410                 break;
1411         case PRID_IMP_RM7000:
1412                 c->cputype = CPU_RM7000;
1413                 __cpu_name[cpu] = "RM7000";
1414                 set_isa(c, MIPS_CPU_ISA_IV);
1415                 c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
1416                              MIPS_CPU_LLSC;
1417                 /*
1418                  * Undocumented RM7000:  Bit 29 in the info register of
1419                  * the RM7000 v2.0 indicates if the TLB has 48 or 64
1420                  * entries.
1421                  *
1422                  * 29      1 =>    64 entry JTLB
1423                  *         0 =>    48 entry JTLB
1424                  */
1425                 c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
1426                 break;
1427         case PRID_IMP_R8000:
1428                 c->cputype = CPU_R8000;
1429                 __cpu_name[cpu] = "RM8000";
1430                 set_isa(c, MIPS_CPU_ISA_IV);
1431                 c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
1432                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1433                              MIPS_CPU_LLSC;
1434                 c->tlbsize = 384;      /* has weird TLB: 3-way x 128 */
1435                 break;
1436         case PRID_IMP_R10000:
1437                 c->cputype = CPU_R10000;
1438                 __cpu_name[cpu] = "R10000";
1439                 set_isa(c, MIPS_CPU_ISA_IV);
1440                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1441                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1442                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1443                              MIPS_CPU_LLSC;
1444                 c->tlbsize = 64;
1445                 break;
1446         case PRID_IMP_R12000:
1447                 c->cputype = CPU_R12000;
1448                 __cpu_name[cpu] = "R12000";
1449                 set_isa(c, MIPS_CPU_ISA_IV);
1450                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1451                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1452                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1453                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1454                 c->tlbsize = 64;
1455                 break;
1456         case PRID_IMP_R14000:
1457                 if (((c->processor_id >> 4) & 0x0f) > 2) {
1458                         c->cputype = CPU_R16000;
1459                         __cpu_name[cpu] = "R16000";
1460                 } else {
1461                         c->cputype = CPU_R14000;
1462                         __cpu_name[cpu] = "R14000";
1463                 }
1464                 set_isa(c, MIPS_CPU_ISA_IV);
1465                 c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
1466                              MIPS_CPU_FPU | MIPS_CPU_32FPR |
1467                              MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
1468                              MIPS_CPU_LLSC | MIPS_CPU_BP_GHIST;
1469                 c->tlbsize = 64;
1470                 break;
1471         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
1472                 switch (c->processor_id & PRID_REV_MASK) {
1473                 case PRID_REV_LOONGSON2E:
1474                         c->cputype = CPU_LOONGSON2;
1475                         __cpu_name[cpu] = "ICT Loongson-2";
1476                         set_elf_platform(cpu, "loongson2e");
1477                         set_isa(c, MIPS_CPU_ISA_III);
1478                         c->fpu_msk31 |= FPU_CSR_CONDX;
1479                         break;
1480                 case PRID_REV_LOONGSON2F:
1481                         c->cputype = CPU_LOONGSON2;
1482                         __cpu_name[cpu] = "ICT Loongson-2";
1483                         set_elf_platform(cpu, "loongson2f");
1484                         set_isa(c, MIPS_CPU_ISA_III);
1485                         c->fpu_msk31 |= FPU_CSR_CONDX;
1486                         break;
1487                 case PRID_REV_LOONGSON3A_R1:
1488                         c->cputype = CPU_LOONGSON3;
1489                         __cpu_name[cpu] = "ICT Loongson-3";
1490                         set_elf_platform(cpu, "loongson3a");
1491                         set_isa(c, MIPS_CPU_ISA_M64R1);
1492                         break;
1493                 case PRID_REV_LOONGSON3B_R1:
1494                 case PRID_REV_LOONGSON3B_R2:
1495                         c->cputype = CPU_LOONGSON3;
1496                         __cpu_name[cpu] = "ICT Loongson-3";
1497                         set_elf_platform(cpu, "loongson3b");
1498                         set_isa(c, MIPS_CPU_ISA_M64R1);
1499                         break;
1500                 }
1501
1502                 c->options = R4K_OPTS |
1503                              MIPS_CPU_FPU | MIPS_CPU_LLSC |
1504                              MIPS_CPU_32FPR;
1505                 c->tlbsize = 64;
1506                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1507                 break;
1508         case PRID_IMP_LOONGSON_32:  /* Loongson-1 */
1509                 decode_configs(c);
1510
1511                 c->cputype = CPU_LOONGSON1;
1512
1513                 switch (c->processor_id & PRID_REV_MASK) {
1514                 case PRID_REV_LOONGSON1B:
1515                         __cpu_name[cpu] = "Loongson 1B";
1516                         break;
1517                 }
1518
1519                 break;
1520         }
1521 }
1522
1523 static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
1524 {
1525         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1526         switch (c->processor_id & PRID_IMP_MASK) {
1527         case PRID_IMP_QEMU_GENERIC:
1528                 c->writecombine = _CACHE_UNCACHED;
1529                 c->cputype = CPU_QEMU_GENERIC;
1530                 __cpu_name[cpu] = "MIPS GENERIC QEMU";
1531                 break;
1532         case PRID_IMP_4KC:
1533                 c->cputype = CPU_4KC;
1534                 c->writecombine = _CACHE_UNCACHED;
1535                 __cpu_name[cpu] = "MIPS 4Kc";
1536                 break;
1537         case PRID_IMP_4KEC:
1538         case PRID_IMP_4KECR2:
1539                 c->cputype = CPU_4KEC;
1540                 c->writecombine = _CACHE_UNCACHED;
1541                 __cpu_name[cpu] = "MIPS 4KEc";
1542                 break;
1543         case PRID_IMP_4KSC:
1544         case PRID_IMP_4KSD:
1545                 c->cputype = CPU_4KSC;
1546                 c->writecombine = _CACHE_UNCACHED;
1547                 __cpu_name[cpu] = "MIPS 4KSc";
1548                 break;
1549         case PRID_IMP_5KC:
1550                 c->cputype = CPU_5KC;
1551                 c->writecombine = _CACHE_UNCACHED;
1552                 __cpu_name[cpu] = "MIPS 5Kc";
1553                 break;
1554         case PRID_IMP_5KE:
1555                 c->cputype = CPU_5KE;
1556                 c->writecombine = _CACHE_UNCACHED;
1557                 __cpu_name[cpu] = "MIPS 5KE";
1558                 break;
1559         case PRID_IMP_20KC:
1560                 c->cputype = CPU_20KC;
1561                 c->writecombine = _CACHE_UNCACHED;
1562                 __cpu_name[cpu] = "MIPS 20Kc";
1563                 break;
1564         case PRID_IMP_24K:
1565                 c->cputype = CPU_24K;
1566                 c->writecombine = _CACHE_UNCACHED;
1567                 __cpu_name[cpu] = "MIPS 24Kc";
1568                 break;
1569         case PRID_IMP_24KE:
1570                 c->cputype = CPU_24K;
1571                 c->writecombine = _CACHE_UNCACHED;
1572                 __cpu_name[cpu] = "MIPS 24KEc";
1573                 break;
1574         case PRID_IMP_25KF:
1575                 c->cputype = CPU_25KF;
1576                 c->writecombine = _CACHE_UNCACHED;
1577                 __cpu_name[cpu] = "MIPS 25Kc";
1578                 break;
1579         case PRID_IMP_34K:
1580                 c->cputype = CPU_34K;
1581                 c->writecombine = _CACHE_UNCACHED;
1582                 __cpu_name[cpu] = "MIPS 34Kc";
1583                 break;
1584         case PRID_IMP_74K:
1585                 c->cputype = CPU_74K;
1586                 c->writecombine = _CACHE_UNCACHED;
1587                 __cpu_name[cpu] = "MIPS 74Kc";
1588                 break;
1589         case PRID_IMP_M14KC:
1590                 c->cputype = CPU_M14KC;
1591                 c->writecombine = _CACHE_UNCACHED;
1592                 __cpu_name[cpu] = "MIPS M14Kc";
1593                 break;
1594         case PRID_IMP_M14KEC:
1595                 c->cputype = CPU_M14KEC;
1596                 c->writecombine = _CACHE_UNCACHED;
1597                 __cpu_name[cpu] = "MIPS M14KEc";
1598                 break;
1599         case PRID_IMP_1004K:
1600                 c->cputype = CPU_1004K;
1601                 c->writecombine = _CACHE_UNCACHED;
1602                 __cpu_name[cpu] = "MIPS 1004Kc";
1603                 break;
1604         case PRID_IMP_1074K:
1605                 c->cputype = CPU_1074K;
1606                 c->writecombine = _CACHE_UNCACHED;
1607                 __cpu_name[cpu] = "MIPS 1074Kc";
1608                 break;
1609         case PRID_IMP_INTERAPTIV_UP:
1610                 c->cputype = CPU_INTERAPTIV;
1611                 __cpu_name[cpu] = "MIPS interAptiv";
1612                 break;
1613         case PRID_IMP_INTERAPTIV_MP:
1614                 c->cputype = CPU_INTERAPTIV;
1615                 __cpu_name[cpu] = "MIPS interAptiv (multi)";
1616                 break;
1617         case PRID_IMP_PROAPTIV_UP:
1618                 c->cputype = CPU_PROAPTIV;
1619                 __cpu_name[cpu] = "MIPS proAptiv";
1620                 break;
1621         case PRID_IMP_PROAPTIV_MP:
1622                 c->cputype = CPU_PROAPTIV;
1623                 __cpu_name[cpu] = "MIPS proAptiv (multi)";
1624                 break;
1625         case PRID_IMP_P5600:
1626                 c->cputype = CPU_P5600;
1627                 __cpu_name[cpu] = "MIPS P5600";
1628                 break;
1629         case PRID_IMP_P6600:
1630                 c->cputype = CPU_P6600;
1631                 __cpu_name[cpu] = "MIPS P6600";
1632                 break;
1633         case PRID_IMP_I6400:
1634                 c->cputype = CPU_I6400;
1635                 __cpu_name[cpu] = "MIPS I6400";
1636                 break;
1637         case PRID_IMP_M5150:
1638                 c->cputype = CPU_M5150;
1639                 __cpu_name[cpu] = "MIPS M5150";
1640                 break;
1641         case PRID_IMP_M6250:
1642                 c->cputype = CPU_M6250;
1643                 __cpu_name[cpu] = "MIPS M6250";
1644                 break;
1645         }
1646
1647         decode_configs(c);
1648
1649         spram_config();
1650 }
1651
1652 static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
1653 {
1654         decode_configs(c);
1655         switch (c->processor_id & PRID_IMP_MASK) {
1656         case PRID_IMP_AU1_REV1:
1657         case PRID_IMP_AU1_REV2:
1658                 c->cputype = CPU_ALCHEMY;
1659                 switch ((c->processor_id >> 24) & 0xff) {
1660                 case 0:
1661                         __cpu_name[cpu] = "Au1000";
1662                         break;
1663                 case 1:
1664                         __cpu_name[cpu] = "Au1500";
1665                         break;
1666                 case 2:
1667                         __cpu_name[cpu] = "Au1100";
1668                         break;
1669                 case 3:
1670                         __cpu_name[cpu] = "Au1550";
1671                         break;
1672                 case 4:
1673                         __cpu_name[cpu] = "Au1200";
1674                         if ((c->processor_id & PRID_REV_MASK) == 2)
1675                                 __cpu_name[cpu] = "Au1250";
1676                         break;
1677                 case 5:
1678                         __cpu_name[cpu] = "Au1210";
1679                         break;
1680                 default:
1681                         __cpu_name[cpu] = "Au1xxx";
1682                         break;
1683                 }
1684                 break;
1685         }
1686 }
1687
1688 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
1689 {
1690         decode_configs(c);
1691
1692         c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1693         switch (c->processor_id & PRID_IMP_MASK) {
1694         case PRID_IMP_SB1:
1695                 c->cputype = CPU_SB1;
1696                 __cpu_name[cpu] = "SiByte SB1";
1697                 /* FPU in pass1 is known to have issues. */
1698                 if ((c->processor_id & PRID_REV_MASK) < 0x02)
1699                         c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
1700                 break;
1701         case PRID_IMP_SB1A:
1702                 c->cputype = CPU_SB1A;
1703                 __cpu_name[cpu] = "SiByte SB1A";
1704                 break;
1705         }
1706 }
1707
1708 static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
1709 {
1710         decode_configs(c);
1711         switch (c->processor_id & PRID_IMP_MASK) {
1712         case PRID_IMP_SR71000:
1713                 c->cputype = CPU_SR71000;
1714                 __cpu_name[cpu] = "Sandcraft SR71000";
1715                 c->scache.ways = 8;
1716                 c->tlbsize = 64;
1717                 break;
1718         }
1719 }
1720
1721 static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
1722 {
1723         decode_configs(c);
1724         switch (c->processor_id & PRID_IMP_MASK) {
1725         case PRID_IMP_PR4450:
1726                 c->cputype = CPU_PR4450;
1727                 __cpu_name[cpu] = "Philips PR4450";
1728                 set_isa(c, MIPS_CPU_ISA_M32R1);
1729                 break;
1730         }
1731 }
1732
1733 static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
1734 {
1735         decode_configs(c);
1736         switch (c->processor_id & PRID_IMP_MASK) {
1737         case PRID_IMP_BMIPS32_REV4:
1738         case PRID_IMP_BMIPS32_REV8:
1739                 c->cputype = CPU_BMIPS32;
1740                 __cpu_name[cpu] = "Broadcom BMIPS32";
1741                 set_elf_platform(cpu, "bmips32");
1742                 break;
1743         case PRID_IMP_BMIPS3300:
1744         case PRID_IMP_BMIPS3300_ALT:
1745         case PRID_IMP_BMIPS3300_BUG:
1746                 c->cputype = CPU_BMIPS3300;
1747                 __cpu_name[cpu] = "Broadcom BMIPS3300";
1748                 set_elf_platform(cpu, "bmips3300");
1749                 break;
1750         case PRID_IMP_BMIPS43XX: {
1751                 int rev = c->processor_id & PRID_REV_MASK;
1752
1753                 if (rev >= PRID_REV_BMIPS4380_LO &&
1754                                 rev <= PRID_REV_BMIPS4380_HI) {
1755                         c->cputype = CPU_BMIPS4380;
1756                         __cpu_name[cpu] = "Broadcom BMIPS4380";
1757                         set_elf_platform(cpu, "bmips4380");
1758                         c->options |= MIPS_CPU_RIXI;
1759                 } else {
1760                         c->cputype = CPU_BMIPS4350;
1761                         __cpu_name[cpu] = "Broadcom BMIPS4350";
1762                         set_elf_platform(cpu, "bmips4350");
1763                 }
1764                 break;
1765         }
1766         case PRID_IMP_BMIPS5000:
1767         case PRID_IMP_BMIPS5200:
1768                 c->cputype = CPU_BMIPS5000;
1769                 if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_BMIPS5200)
1770                         __cpu_name[cpu] = "Broadcom BMIPS5200";
1771                 else
1772                         __cpu_name[cpu] = "Broadcom BMIPS5000";
1773                 set_elf_platform(cpu, "bmips5000");
1774                 c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
1775                 break;
1776         }
1777 }
1778
1779 static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
1780 {
1781         decode_configs(c);
1782         switch (c->processor_id & PRID_IMP_MASK) {
1783         case PRID_IMP_CAVIUM_CN38XX:
1784         case PRID_IMP_CAVIUM_CN31XX:
1785         case PRID_IMP_CAVIUM_CN30XX:
1786                 c->cputype = CPU_CAVIUM_OCTEON;
1787                 __cpu_name[cpu] = "Cavium Octeon";
1788                 goto platform;
1789         case PRID_IMP_CAVIUM_CN58XX:
1790         case PRID_IMP_CAVIUM_CN56XX:
1791         case PRID_IMP_CAVIUM_CN50XX:
1792         case PRID_IMP_CAVIUM_CN52XX:
1793                 c->cputype = CPU_CAVIUM_OCTEON_PLUS;
1794                 __cpu_name[cpu] = "Cavium Octeon+";
1795 platform:
1796                 set_elf_platform(cpu, "octeon");
1797                 break;
1798         case PRID_IMP_CAVIUM_CN61XX:
1799         case PRID_IMP_CAVIUM_CN63XX:
1800         case PRID_IMP_CAVIUM_CN66XX:
1801         case PRID_IMP_CAVIUM_CN68XX:
1802         case PRID_IMP_CAVIUM_CNF71XX:
1803                 c->cputype = CPU_CAVIUM_OCTEON2;
1804                 __cpu_name[cpu] = "Cavium Octeon II";
1805                 set_elf_platform(cpu, "octeon2");
1806                 break;
1807         case PRID_IMP_CAVIUM_CN70XX:
1808         case PRID_IMP_CAVIUM_CN73XX:
1809         case PRID_IMP_CAVIUM_CNF75XX:
1810         case PRID_IMP_CAVIUM_CN78XX:
1811                 c->cputype = CPU_CAVIUM_OCTEON3;
1812                 __cpu_name[cpu] = "Cavium Octeon III";
1813                 set_elf_platform(cpu, "octeon3");
1814                 break;
1815         default:
1816                 printk(KERN_INFO "Unknown Octeon chip!\n");
1817                 c->cputype = CPU_UNKNOWN;
1818                 break;
1819         }
1820 }
1821
1822 static inline void cpu_probe_loongson(struct cpuinfo_mips *c, unsigned int cpu)
1823 {
1824         switch (c->processor_id & PRID_IMP_MASK) {
1825         case PRID_IMP_LOONGSON_64:  /* Loongson-2/3 */
1826                 switch (c->processor_id & PRID_REV_MASK) {
1827                 case PRID_REV_LOONGSON3A_R2:
1828                         c->cputype = CPU_LOONGSON3;
1829                         __cpu_name[cpu] = "ICT Loongson-3";
1830                         set_elf_platform(cpu, "loongson3a");
1831                         set_isa(c, MIPS_CPU_ISA_M64R2);
1832                         break;
1833                 }
1834
1835                 decode_configs(c);
1836                 c->options |= MIPS_CPU_FTLB | MIPS_CPU_TLBINV | MIPS_CPU_LDPTE;
1837                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1838                 break;
1839         default:
1840                 panic("Unknown Loongson Processor ID!");
1841                 break;
1842         }
1843 }
1844
1845 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
1846 {
1847         decode_configs(c);
1848         /* JZRISC does not implement the CP0 counter. */
1849         c->options &= ~MIPS_CPU_COUNTER;
1850         BUG_ON(!__builtin_constant_p(cpu_has_counter) || cpu_has_counter);
1851         switch (c->processor_id & PRID_IMP_MASK) {
1852         case PRID_IMP_JZRISC:
1853                 c->cputype = CPU_JZRISC;
1854                 c->writecombine = _CACHE_UNCACHED_ACCELERATED;
1855                 __cpu_name[cpu] = "Ingenic JZRISC";
1856                 break;
1857         default:
1858                 panic("Unknown Ingenic Processor ID!");
1859                 break;
1860         }
1861 }
1862
1863 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
1864 {
1865         decode_configs(c);
1866
1867         if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_NETLOGIC_AU13XX) {
1868                 c->cputype = CPU_ALCHEMY;
1869                 __cpu_name[cpu] = "Au1300";
1870                 /* following stuff is not for Alchemy */
1871                 return;
1872         }
1873
1874         c->options = (MIPS_CPU_TLB       |
1875                         MIPS_CPU_4KEX    |
1876                         MIPS_CPU_COUNTER |
1877                         MIPS_CPU_DIVEC   |
1878                         MIPS_CPU_WATCH   |
1879                         MIPS_CPU_EJTAG   |
1880                         MIPS_CPU_LLSC);
1881
1882         switch (c->processor_id & PRID_IMP_MASK) {
1883         case PRID_IMP_NETLOGIC_XLP2XX:
1884         case PRID_IMP_NETLOGIC_XLP9XX:
1885         case PRID_IMP_NETLOGIC_XLP5XX:
1886                 c->cputype = CPU_XLP;
1887                 __cpu_name[cpu] = "Broadcom XLPII";
1888                 break;
1889
1890         case PRID_IMP_NETLOGIC_XLP8XX:
1891         case PRID_IMP_NETLOGIC_XLP3XX:
1892                 c->cputype = CPU_XLP;
1893                 __cpu_name[cpu] = "Netlogic XLP";
1894                 break;
1895
1896         case PRID_IMP_NETLOGIC_XLR732:
1897         case PRID_IMP_NETLOGIC_XLR716:
1898         case PRID_IMP_NETLOGIC_XLR532:
1899         case PRID_IMP_NETLOGIC_XLR308:
1900         case PRID_IMP_NETLOGIC_XLR532C:
1901         case PRID_IMP_NETLOGIC_XLR516C:
1902         case PRID_IMP_NETLOGIC_XLR508C:
1903         case PRID_IMP_NETLOGIC_XLR308C:
1904                 c->cputype = CPU_XLR;
1905                 __cpu_name[cpu] = "Netlogic XLR";
1906                 break;
1907
1908         case PRID_IMP_NETLOGIC_XLS608:
1909         case PRID_IMP_NETLOGIC_XLS408:
1910         case PRID_IMP_NETLOGIC_XLS404:
1911         case PRID_IMP_NETLOGIC_XLS208:
1912         case PRID_IMP_NETLOGIC_XLS204:
1913         case PRID_IMP_NETLOGIC_XLS108:
1914         case PRID_IMP_NETLOGIC_XLS104:
1915         case PRID_IMP_NETLOGIC_XLS616B:
1916         case PRID_IMP_NETLOGIC_XLS608B:
1917         case PRID_IMP_NETLOGIC_XLS416B:
1918         case PRID_IMP_NETLOGIC_XLS412B:
1919         case PRID_IMP_NETLOGIC_XLS408B:
1920         case PRID_IMP_NETLOGIC_XLS404B:
1921                 c->cputype = CPU_XLR;
1922                 __cpu_name[cpu] = "Netlogic XLS";
1923                 break;
1924
1925         default:
1926                 pr_info("Unknown Netlogic chip id [%02x]!\n",
1927                        c->processor_id);
1928                 c->cputype = CPU_XLR;
1929                 break;
1930         }
1931
1932         if (c->cputype == CPU_XLP) {
1933                 set_isa(c, MIPS_CPU_ISA_M64R2);
1934                 c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
1935                 /* This will be updated again after all threads are woken up */
1936                 c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
1937         } else {
1938                 set_isa(c, MIPS_CPU_ISA_M64R1);
1939                 c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
1940         }
1941         c->kscratch_mask = 0xf;
1942 }
1943
1944 #ifdef CONFIG_64BIT
1945 /* For use by uaccess.h */
1946 u64 __ua_limit;
1947 EXPORT_SYMBOL(__ua_limit);
1948 #endif
1949
1950 const char *__cpu_name[NR_CPUS];
1951 const char *__elf_platform;
1952
1953 void cpu_probe(void)
1954 {
1955         struct cpuinfo_mips *c = &current_cpu_data;
1956         unsigned int cpu = smp_processor_id();
1957
1958         c->processor_id = PRID_IMP_UNKNOWN;
1959         c->fpu_id       = FPIR_IMP_NONE;
1960         c->cputype      = CPU_UNKNOWN;
1961         c->writecombine = _CACHE_UNCACHED;
1962
1963         c->fpu_csr31    = FPU_CSR_RN;
1964         c->fpu_msk31    = FPU_CSR_RSVD | FPU_CSR_ABS2008 | FPU_CSR_NAN2008;
1965
1966         c->processor_id = read_c0_prid();
1967         switch (c->processor_id & PRID_COMP_MASK) {
1968         case PRID_COMP_LEGACY:
1969                 cpu_probe_legacy(c, cpu);
1970                 break;
1971         case PRID_COMP_MIPS:
1972                 cpu_probe_mips(c, cpu);
1973                 break;
1974         case PRID_COMP_ALCHEMY:
1975                 cpu_probe_alchemy(c, cpu);
1976                 break;
1977         case PRID_COMP_SIBYTE:
1978                 cpu_probe_sibyte(c, cpu);
1979                 break;
1980         case PRID_COMP_BROADCOM:
1981                 cpu_probe_broadcom(c, cpu);
1982                 break;
1983         case PRID_COMP_SANDCRAFT:
1984                 cpu_probe_sandcraft(c, cpu);
1985                 break;
1986         case PRID_COMP_NXP:
1987                 cpu_probe_nxp(c, cpu);
1988                 break;
1989         case PRID_COMP_CAVIUM:
1990                 cpu_probe_cavium(c, cpu);
1991                 break;
1992         case PRID_COMP_LOONGSON:
1993                 cpu_probe_loongson(c, cpu);
1994                 break;
1995         case PRID_COMP_INGENIC_D0:
1996         case PRID_COMP_INGENIC_D1:
1997         case PRID_COMP_INGENIC_E1:
1998                 cpu_probe_ingenic(c, cpu);
1999                 break;
2000         case PRID_COMP_NETLOGIC:
2001                 cpu_probe_netlogic(c, cpu);
2002                 break;
2003         }
2004
2005         BUG_ON(!__cpu_name[cpu]);
2006         BUG_ON(c->cputype == CPU_UNKNOWN);
2007
2008         /*
2009          * Platform code can force the cpu type to optimize code
2010          * generation. In that case be sure the cpu type is correctly
2011          * manually setup otherwise it could trigger some nasty bugs.
2012          */
2013         BUG_ON(current_cpu_type() != c->cputype);
2014
2015         if (cpu_has_rixi) {
2016                 /* Enable the RIXI exceptions */
2017                 set_c0_pagegrain(PG_IEC);
2018                 back_to_back_c0_hazard();
2019                 /* Verify the IEC bit is set */
2020                 if (read_c0_pagegrain() & PG_IEC)
2021                         c->options |= MIPS_CPU_RIXIEX;
2022         }
2023
2024         if (mips_fpu_disabled)
2025                 c->options &= ~MIPS_CPU_FPU;
2026
2027         if (mips_dsp_disabled)
2028                 c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
2029
2030         if (mips_htw_disabled) {
2031                 c->options &= ~MIPS_CPU_HTW;
2032                 write_c0_pwctl(read_c0_pwctl() &
2033                                ~(1 << MIPS_PWCTL_PWEN_SHIFT));
2034         }
2035
2036         if (c->options & MIPS_CPU_FPU)
2037                 cpu_set_fpu_opts(c);
2038         else
2039                 cpu_set_nofpu_opts(c);
2040
2041         if (cpu_has_bp_ghist)
2042                 write_c0_r10k_diag(read_c0_r10k_diag() |
2043                                    R10K_DIAG_E_GHIST);
2044
2045         if (cpu_has_mips_r2_r6) {
2046                 c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
2047                 /* R2 has Performance Counter Interrupt indicator */
2048                 c->options |= MIPS_CPU_PCI;
2049         }
2050         else
2051                 c->srsets = 1;
2052
2053         if (cpu_has_mips_r6)
2054                 elf_hwcap |= HWCAP_MIPS_R6;
2055
2056         if (cpu_has_msa) {
2057                 c->msa_id = cpu_get_msa_id();
2058                 WARN(c->msa_id & MSA_IR_WRPF,
2059                      "Vector register partitioning unimplemented!");
2060                 elf_hwcap |= HWCAP_MIPS_MSA;
2061         }
2062
2063         if (cpu_has_vz)
2064                 cpu_probe_vz(c);
2065
2066         cpu_probe_vmbits(c);
2067
2068 #ifdef CONFIG_64BIT
2069         if (cpu == 0)
2070                 __ua_limit = ~((1ull << cpu_vmbits) - 1);
2071 #endif
2072 }
2073
2074 void cpu_report(void)
2075 {
2076         struct cpuinfo_mips *c = &current_cpu_data;
2077
2078         pr_info("CPU%d revision is: %08x (%s)\n",
2079                 smp_processor_id(), c->processor_id, cpu_name_string());
2080         if (c->options & MIPS_CPU_FPU)
2081                 printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
2082         if (cpu_has_msa)
2083                 pr_info("MSA revision is: %08x\n", c->msa_id);
2084 }