arch/mips/jz4740/time.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  *  Copyright (C) 2010, Lars-Peter Clausen <lars@metafoo.de>
   4  *  JZ4740 platform time support
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/clk-provider.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/kernel.h>
  11 #include <linux/time.h>
  12
  13 #include <linux/clockchips.h>
  14 #include <linux/sched_clock.h>
  15
  16 #include <asm/mach-jz4740/clock.h>
  17 #include <asm/mach-jz4740/irq.h>
  18 #include <asm/mach-jz4740/timer.h>
  19 #include <asm/time.h>
  20
  21 #include "clock.h"
  22
  23 #define TIMER_CLOCKEVENT 0
  24 #define TIMER_CLOCKSOURCE 1
  25
  26 static uint16_t jz4740_jiffies_per_tick;
  27
  28 static u64 jz4740_clocksource_read(struct clocksource *cs)
  29 {
  30         return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
  31 }
  32
  33 static struct clocksource jz4740_clocksource = {
  34         .name = "jz4740-timer",
  35         .rating = 200,
  36         .read = jz4740_clocksource_read,
  37         .mask = CLOCKSOURCE_MASK(16),
  38         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  39 };
  40
  41 static u64 notrace jz4740_read_sched_clock(void)
  42 {
  43         return jz4740_timer_get_count(TIMER_CLOCKSOURCE);
  44 }
  45
  46 static irqreturn_t jz4740_clockevent_irq(int irq, void *devid)
  47 {
  48         struct clock_event_device *cd = devid;
  49
  50         jz4740_timer_ack_full(TIMER_CLOCKEVENT);
  51
  52         if (!clockevent_state_periodic(cd))
  53                 jz4740_timer_disable(TIMER_CLOCKEVENT);
  54
  55         cd->event_handler(cd);
  56
  57         return IRQ_HANDLED;
  58 }
  59
  60 static int jz4740_clockevent_set_periodic(struct clock_event_device *evt)
  61 {
  62         jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
  63         jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
  64         jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
  65         jz4740_timer_enable(TIMER_CLOCKEVENT);
  66
  67         return 0;
  68 }
  69
  70 static int jz4740_clockevent_resume(struct clock_event_device *evt)
  71 {
  72         jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
  73         jz4740_timer_enable(TIMER_CLOCKEVENT);
  74
  75         return 0;
  76 }
  77
  78 static int jz4740_clockevent_shutdown(struct clock_event_device *evt)
  79 {
  80         jz4740_timer_disable(TIMER_CLOCKEVENT);
  81
  82         return 0;
  83 }
  84
  85 static int jz4740_clockevent_set_next(unsigned long evt,
  86         struct clock_event_device *cd)
  87 {
  88         jz4740_timer_set_count(TIMER_CLOCKEVENT, 0);
  89         jz4740_timer_set_period(TIMER_CLOCKEVENT, evt);
  90         jz4740_timer_enable(TIMER_CLOCKEVENT);
  91
  92         return 0;
  93 }
  94
  95 static struct clock_event_device jz4740_clockevent = {
  96         .name = "jz4740-timer",
  97         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  98         .set_next_event = jz4740_clockevent_set_next,
  99         .set_state_shutdown = jz4740_clockevent_shutdown,
 100         .set_state_periodic = jz4740_clockevent_set_periodic,
 101         .set_state_oneshot = jz4740_clockevent_shutdown,
 102         .tick_resume = jz4740_clockevent_resume,
 103         .rating = 200,
 104 #ifdef CONFIG_MACH_JZ4740
 105         .irq = JZ4740_IRQ_TCU0,
 106 #endif
 107 #if defined(CONFIG_MACH_JZ4770) || defined(CONFIG_MACH_JZ4780)
 108         .irq = JZ4780_IRQ_TCU2,
 109 #endif
 110 };
 111
 112 static struct irqaction timer_irqaction = {
 113         .handler        = jz4740_clockevent_irq,
 114         .flags          = IRQF_PERCPU | IRQF_TIMER,
 115         .name           = "jz4740-timerirq",
 116         .dev_id         = &jz4740_clockevent,
 117 };
 118
 119 void __init plat_time_init(void)
 120 {
 121         int ret;
 122         uint32_t clk_rate;
 123         uint16_t ctrl;
 124         struct clk *ext_clk;
 125
 126         of_clk_init(NULL);
 127         jz4740_timer_init();
 128
 129         ext_clk = clk_get(NULL, "ext");
 130         if (IS_ERR(ext_clk))
 131                 panic("unable to get ext clock");
 132         clk_rate = clk_get_rate(ext_clk) >> 4;
 133         clk_put(ext_clk);
 134
 135         jz4740_jiffies_per_tick = DIV_ROUND_CLOSEST(clk_rate, HZ);
 136
 137         clockevent_set_clock(&jz4740_clockevent, clk_rate);
 138         jz4740_clockevent.min_delta_ns = clockevent_delta2ns(100, &jz4740_clockevent);
 139         jz4740_clockevent.min_delta_ticks = 100;
 140         jz4740_clockevent.max_delta_ns = clockevent_delta2ns(0xffff, &jz4740_clockevent);
 141         jz4740_clockevent.max_delta_ticks = 0xffff;
 142         jz4740_clockevent.cpumask = cpumask_of(0);
 143
 144         clockevents_register_device(&jz4740_clockevent);
 145
 146         ret = clocksource_register_hz(&jz4740_clocksource, clk_rate);
 147
 148         if (ret)
 149                 printk(KERN_ERR "Failed to register clocksource: %d\n", ret);
 150
 151         sched_clock_register(jz4740_read_sched_clock, 16, clk_rate);
 152
 153         setup_irq(jz4740_clockevent.irq, &timer_irqaction);
 154
 155         ctrl = JZ_TIMER_CTRL_PRESCALE_16 | JZ_TIMER_CTRL_SRC_EXT;
 156
 157         jz4740_timer_set_ctrl(TIMER_CLOCKEVENT, ctrl);
 158         jz4740_timer_set_ctrl(TIMER_CLOCKSOURCE, ctrl);
 159
 160         jz4740_timer_set_period(TIMER_CLOCKEVENT, jz4740_jiffies_per_tick);
 161         jz4740_timer_irq_full_enable(TIMER_CLOCKEVENT);
 162
 163         jz4740_timer_set_period(TIMER_CLOCKSOURCE, 0xffff);
 164
 165         jz4740_timer_enable(TIMER_CLOCKEVENT);
 166         jz4740_timer_enable(TIMER_CLOCKSOURCE);
 167 }