arch/mips/include/asm/octeon/cvmx-iob-defs.h

   1 /***********************license start***************
   2  * Author: Cavium Networks
   3  *
   4  * Contact: support@caviumnetworks.com
   5  * This file is part of the OCTEON SDK
   6  *
   7  * Copyright (c) 2003-2012 Cavium Networks
   8  *
   9  * This file is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License, Version 2, as
  11  * published by the Free Software Foundation.
  12  *
  13  * This file is distributed in the hope that it will be useful, but
  14  * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16  * NONINFRINGEMENT.  See the GNU General Public License for more
  17  * details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this file; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22  * or visit http://www.gnu.org/licenses/.
  23  *
  24  * This file may also be available under a different license from Cavium.
  25  * Contact Cavium Networks for more information
  26  ***********************license end**************************************/
  27
  28 #ifndef __CVMX_IOB_DEFS_H__
  29 #define __CVMX_IOB_DEFS_H__
  30
  31 #define CVMX_IOB_BIST_STATUS (CVMX_ADD_IO_SEG(0x00011800F00007F8ull))
  32 #define CVMX_IOB_CTL_STATUS (CVMX_ADD_IO_SEG(0x00011800F0000050ull))
  33 #define CVMX_IOB_DWB_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000028ull))
  34 #define CVMX_IOB_FAU_TIMEOUT (CVMX_ADD_IO_SEG(0x00011800F0000000ull))
  35 #define CVMX_IOB_I2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000010ull))
  36 #define CVMX_IOB_INB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000078ull))
  37 #define CVMX_IOB_INB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000088ull))
  38 #define CVMX_IOB_INB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000070ull))
  39 #define CVMX_IOB_INB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F0000080ull))
  40 #define CVMX_IOB_INT_ENB (CVMX_ADD_IO_SEG(0x00011800F0000060ull))
  41 #define CVMX_IOB_INT_SUM (CVMX_ADD_IO_SEG(0x00011800F0000058ull))
  42 #define CVMX_IOB_N2C_L2C_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000020ull))
  43 #define CVMX_IOB_N2C_RSP_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000008ull))
  44 #define CVMX_IOB_OUTB_COM_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000040ull))
  45 #define CVMX_IOB_OUTB_CONTROL_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000098ull))
  46 #define CVMX_IOB_OUTB_CONTROL_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A8ull))
  47 #define CVMX_IOB_OUTB_DATA_MATCH (CVMX_ADD_IO_SEG(0x00011800F0000090ull))
  48 #define CVMX_IOB_OUTB_DATA_MATCH_ENB (CVMX_ADD_IO_SEG(0x00011800F00000A0ull))
  49 #define CVMX_IOB_OUTB_FPA_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000048ull))
  50 #define CVMX_IOB_OUTB_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000038ull))
  51 #define CVMX_IOB_P2C_REQ_PRI_CNT (CVMX_ADD_IO_SEG(0x00011800F0000018ull))
  52 #define CVMX_IOB_PKT_ERR (CVMX_ADD_IO_SEG(0x00011800F0000068ull))
  53 #define CVMX_IOB_TO_CMB_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00000B0ull))
  54 #define CVMX_IOB_TO_NCB_DID_00_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000800ull))
  55 #define CVMX_IOB_TO_NCB_DID_111_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B78ull))
  56 #define CVMX_IOB_TO_NCB_DID_223_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000EF8ull))
  57 #define CVMX_IOB_TO_NCB_DID_24_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00008C0ull))
  58 #define CVMX_IOB_TO_NCB_DID_32_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000900ull))
  59 #define CVMX_IOB_TO_NCB_DID_40_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000940ull))
  60 #define CVMX_IOB_TO_NCB_DID_55_CREDITS (CVMX_ADD_IO_SEG(0x00011800F00009B8ull))
  61 #define CVMX_IOB_TO_NCB_DID_64_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A00ull))
  62 #define CVMX_IOB_TO_NCB_DID_79_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000A78ull))
  63 #define CVMX_IOB_TO_NCB_DID_96_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B00ull))
  64 #define CVMX_IOB_TO_NCB_DID_98_CREDITS (CVMX_ADD_IO_SEG(0x00011800F0000B10ull))
  65
  66 union cvmx_iob_bist_status {
  67         uint64_t u64;
  68         struct cvmx_iob_bist_status_s {
  69 #ifdef __BIG_ENDIAN_BITFIELD
  70                 uint64_t reserved_2_63:62;
  71                 uint64_t ibd:1;
  72                 uint64_t icd:1;
  73 #else
  74                 uint64_t icd:1;
  75                 uint64_t ibd:1;
  76                 uint64_t reserved_2_63:62;
  77 #endif
  78         } s;
  79         struct cvmx_iob_bist_status_cn30xx {
  80 #ifdef __BIG_ENDIAN_BITFIELD
  81                 uint64_t reserved_18_63:46;
  82                 uint64_t icnrcb:1;
  83                 uint64_t icr0:1;
  84                 uint64_t icr1:1;
  85                 uint64_t icnr1:1;
  86                 uint64_t icnr0:1;
  87                 uint64_t ibdr0:1;
  88                 uint64_t ibdr1:1;
  89                 uint64_t ibr0:1;
  90                 uint64_t ibr1:1;
  91                 uint64_t icnrt:1;
  92                 uint64_t ibrq0:1;
  93                 uint64_t ibrq1:1;
  94                 uint64_t icrn0:1;
  95                 uint64_t icrn1:1;
  96                 uint64_t icrp0:1;
  97                 uint64_t icrp1:1;
  98                 uint64_t ibd:1;
  99                 uint64_t icd:1;
 100 #else
 101                 uint64_t icd:1;
 102                 uint64_t ibd:1;
 103                 uint64_t icrp1:1;
 104                 uint64_t icrp0:1;
 105                 uint64_t icrn1:1;
 106                 uint64_t icrn0:1;
 107                 uint64_t ibrq1:1;
 108                 uint64_t ibrq0:1;
 109                 uint64_t icnrt:1;
 110                 uint64_t ibr1:1;
 111                 uint64_t ibr0:1;
 112                 uint64_t ibdr1:1;
 113                 uint64_t ibdr0:1;
 114                 uint64_t icnr0:1;
 115                 uint64_t icnr1:1;
 116                 uint64_t icr1:1;
 117                 uint64_t icr0:1;
 118                 uint64_t icnrcb:1;
 119                 uint64_t reserved_18_63:46;
 120 #endif
 121         } cn30xx;
 122         struct cvmx_iob_bist_status_cn61xx {
 123 #ifdef __BIG_ENDIAN_BITFIELD
 124                 uint64_t reserved_23_63:41;
 125                 uint64_t xmdfif:1;
 126                 uint64_t xmcfif:1;
 127                 uint64_t iorfif:1;
 128                 uint64_t rsdfif:1;
 129                 uint64_t iocfif:1;
 130                 uint64_t icnrcb:1;
 131                 uint64_t icr0:1;
 132                 uint64_t icr1:1;
 133                 uint64_t icnr1:1;
 134                 uint64_t icnr0:1;
 135                 uint64_t ibdr0:1;
 136                 uint64_t ibdr1:1;
 137                 uint64_t ibr0:1;
 138                 uint64_t ibr1:1;
 139                 uint64_t icnrt:1;
 140                 uint64_t ibrq0:1;
 141                 uint64_t ibrq1:1;
 142                 uint64_t icrn0:1;
 143                 uint64_t icrn1:1;
 144                 uint64_t icrp0:1;
 145                 uint64_t icrp1:1;
 146                 uint64_t ibd:1;
 147                 uint64_t icd:1;
 148 #else
 149                 uint64_t icd:1;
 150                 uint64_t ibd:1;
 151                 uint64_t icrp1:1;
 152                 uint64_t icrp0:1;
 153                 uint64_t icrn1:1;
 154                 uint64_t icrn0:1;
 155                 uint64_t ibrq1:1;
 156                 uint64_t ibrq0:1;
 157                 uint64_t icnrt:1;
 158                 uint64_t ibr1:1;
 159                 uint64_t ibr0:1;
 160                 uint64_t ibdr1:1;
 161                 uint64_t ibdr0:1;
 162                 uint64_t icnr0:1;
 163                 uint64_t icnr1:1;
 164                 uint64_t icr1:1;
 165                 uint64_t icr0:1;
 166                 uint64_t icnrcb:1;
 167                 uint64_t iocfif:1;
 168                 uint64_t rsdfif:1;
 169                 uint64_t iorfif:1;
 170                 uint64_t xmcfif:1;
 171                 uint64_t xmdfif:1;
 172                 uint64_t reserved_23_63:41;
 173 #endif
 174         } cn61xx;
 175         struct cvmx_iob_bist_status_cn68xx {
 176 #ifdef __BIG_ENDIAN_BITFIELD
 177                 uint64_t reserved_18_63:46;
 178                 uint64_t xmdfif:1;
 179                 uint64_t xmcfif:1;
 180                 uint64_t iorfif:1;
 181                 uint64_t rsdfif:1;
 182                 uint64_t iocfif:1;
 183                 uint64_t icnrcb:1;
 184                 uint64_t icr0:1;
 185                 uint64_t icr1:1;
 186                 uint64_t icnr0:1;
 187                 uint64_t ibr0:1;
 188                 uint64_t ibr1:1;
 189                 uint64_t icnrt:1;
 190                 uint64_t ibrq0:1;
 191                 uint64_t ibrq1:1;
 192                 uint64_t icrn0:1;
 193                 uint64_t icrn1:1;
 194                 uint64_t ibd:1;
 195                 uint64_t icd:1;
 196 #else
 197                 uint64_t icd:1;
 198                 uint64_t ibd:1;
 199                 uint64_t icrn1:1;
 200                 uint64_t icrn0:1;
 201                 uint64_t ibrq1:1;
 202                 uint64_t ibrq0:1;
 203                 uint64_t icnrt:1;
 204                 uint64_t ibr1:1;
 205                 uint64_t ibr0:1;
 206                 uint64_t icnr0:1;
 207                 uint64_t icr1:1;
 208                 uint64_t icr0:1;
 209                 uint64_t icnrcb:1;
 210                 uint64_t iocfif:1;
 211                 uint64_t rsdfif:1;
 212                 uint64_t iorfif:1;
 213                 uint64_t xmcfif:1;
 214                 uint64_t xmdfif:1;
 215                 uint64_t reserved_18_63:46;
 216 #endif
 217         } cn68xx;
 218 };
 219
 220 union cvmx_iob_ctl_status {
 221         uint64_t u64;
 222         struct cvmx_iob_ctl_status_s {
 223 #ifdef __BIG_ENDIAN_BITFIELD
 224                 uint64_t reserved_11_63:53;
 225                 uint64_t fif_dly:1;
 226                 uint64_t xmc_per:4;
 227                 uint64_t reserved_5_5:1;
 228                 uint64_t outb_mat:1;
 229                 uint64_t inb_mat:1;
 230                 uint64_t pko_enb:1;
 231                 uint64_t dwb_enb:1;
 232                 uint64_t fau_end:1;
 233 #else
 234                 uint64_t fau_end:1;
 235                 uint64_t dwb_enb:1;
 236                 uint64_t pko_enb:1;
 237                 uint64_t inb_mat:1;
 238                 uint64_t outb_mat:1;
 239                 uint64_t reserved_5_5:1;
 240                 uint64_t xmc_per:4;
 241                 uint64_t fif_dly:1;
 242                 uint64_t reserved_11_63:53;
 243 #endif
 244         } s;
 245         struct cvmx_iob_ctl_status_cn30xx {
 246 #ifdef __BIG_ENDIAN_BITFIELD
 247                 uint64_t reserved_5_63:59;
 248                 uint64_t outb_mat:1;
 249                 uint64_t inb_mat:1;
 250                 uint64_t pko_enb:1;
 251                 uint64_t dwb_enb:1;
 252                 uint64_t fau_end:1;
 253 #else
 254                 uint64_t fau_end:1;
 255                 uint64_t dwb_enb:1;
 256                 uint64_t pko_enb:1;
 257                 uint64_t inb_mat:1;
 258                 uint64_t outb_mat:1;
 259                 uint64_t reserved_5_63:59;
 260 #endif
 261         } cn30xx;
 262         struct cvmx_iob_ctl_status_cn52xx {
 263 #ifdef __BIG_ENDIAN_BITFIELD
 264                 uint64_t reserved_6_63:58;
 265                 uint64_t rr_mode:1;
 266                 uint64_t outb_mat:1;
 267                 uint64_t inb_mat:1;
 268                 uint64_t pko_enb:1;
 269                 uint64_t dwb_enb:1;
 270                 uint64_t fau_end:1;
 271 #else
 272                 uint64_t fau_end:1;
 273                 uint64_t dwb_enb:1;
 274                 uint64_t pko_enb:1;
 275                 uint64_t inb_mat:1;
 276                 uint64_t outb_mat:1;
 277                 uint64_t rr_mode:1;
 278                 uint64_t reserved_6_63:58;
 279 #endif
 280         } cn52xx;
 281         struct cvmx_iob_ctl_status_cn61xx {
 282 #ifdef __BIG_ENDIAN_BITFIELD
 283                 uint64_t reserved_11_63:53;
 284                 uint64_t fif_dly:1;
 285                 uint64_t xmc_per:4;
 286                 uint64_t rr_mode:1;
 287                 uint64_t outb_mat:1;
 288                 uint64_t inb_mat:1;
 289                 uint64_t pko_enb:1;
 290                 uint64_t dwb_enb:1;
 291                 uint64_t fau_end:1;
 292 #else
 293                 uint64_t fau_end:1;
 294                 uint64_t dwb_enb:1;
 295                 uint64_t pko_enb:1;
 296                 uint64_t inb_mat:1;
 297                 uint64_t outb_mat:1;
 298                 uint64_t rr_mode:1;
 299                 uint64_t xmc_per:4;
 300                 uint64_t fif_dly:1;
 301                 uint64_t reserved_11_63:53;
 302 #endif
 303         } cn61xx;
 304         struct cvmx_iob_ctl_status_cn63xx {
 305 #ifdef __BIG_ENDIAN_BITFIELD
 306                 uint64_t reserved_10_63:54;
 307                 uint64_t xmc_per:4;
 308                 uint64_t rr_mode:1;
 309                 uint64_t outb_mat:1;
 310                 uint64_t inb_mat:1;
 311                 uint64_t pko_enb:1;
 312                 uint64_t dwb_enb:1;
 313                 uint64_t fau_end:1;
 314 #else
 315                 uint64_t fau_end:1;
 316                 uint64_t dwb_enb:1;
 317                 uint64_t pko_enb:1;
 318                 uint64_t inb_mat:1;
 319                 uint64_t outb_mat:1;
 320                 uint64_t rr_mode:1;
 321                 uint64_t xmc_per:4;
 322                 uint64_t reserved_10_63:54;
 323 #endif
 324         } cn63xx;
 325         struct cvmx_iob_ctl_status_cn68xx {
 326 #ifdef __BIG_ENDIAN_BITFIELD
 327                 uint64_t reserved_11_63:53;
 328                 uint64_t fif_dly:1;
 329                 uint64_t xmc_per:4;
 330                 uint64_t rsvr5:1;
 331                 uint64_t outb_mat:1;
 332                 uint64_t inb_mat:1;
 333                 uint64_t pko_enb:1;
 334                 uint64_t dwb_enb:1;
 335                 uint64_t fau_end:1;
 336 #else
 337                 uint64_t fau_end:1;
 338                 uint64_t dwb_enb:1;
 339                 uint64_t pko_enb:1;
 340                 uint64_t inb_mat:1;
 341                 uint64_t outb_mat:1;
 342                 uint64_t rsvr5:1;
 343                 uint64_t xmc_per:4;
 344                 uint64_t fif_dly:1;
 345                 uint64_t reserved_11_63:53;
 346 #endif
 347         } cn68xx;
 348 };
 349
 350 union cvmx_iob_dwb_pri_cnt {
 351         uint64_t u64;
 352         struct cvmx_iob_dwb_pri_cnt_s {
 353 #ifdef __BIG_ENDIAN_BITFIELD
 354                 uint64_t reserved_16_63:48;
 355                 uint64_t cnt_enb:1;
 356                 uint64_t cnt_val:15;
 357 #else
 358                 uint64_t cnt_val:15;
 359                 uint64_t cnt_enb:1;
 360                 uint64_t reserved_16_63:48;
 361 #endif
 362         } s;
 363 };
 364
 365 union cvmx_iob_fau_timeout {
 366         uint64_t u64;
 367         struct cvmx_iob_fau_timeout_s {
 368 #ifdef __BIG_ENDIAN_BITFIELD
 369                 uint64_t reserved_13_63:51;
 370                 uint64_t tout_enb:1;
 371                 uint64_t tout_val:12;
 372 #else
 373                 uint64_t tout_val:12;
 374                 uint64_t tout_enb:1;
 375                 uint64_t reserved_13_63:51;
 376 #endif
 377         } s;
 378 };
 379
 380 union cvmx_iob_i2c_pri_cnt {
 381         uint64_t u64;
 382         struct cvmx_iob_i2c_pri_cnt_s {
 383 #ifdef __BIG_ENDIAN_BITFIELD
 384                 uint64_t reserved_16_63:48;
 385                 uint64_t cnt_enb:1;
 386                 uint64_t cnt_val:15;
 387 #else
 388                 uint64_t cnt_val:15;
 389                 uint64_t cnt_enb:1;
 390                 uint64_t reserved_16_63:48;
 391 #endif
 392         } s;
 393 };
 394
 395 union cvmx_iob_inb_control_match {
 396         uint64_t u64;
 397         struct cvmx_iob_inb_control_match_s {
 398 #ifdef __BIG_ENDIAN_BITFIELD
 399                 uint64_t reserved_29_63:35;
 400                 uint64_t mask:8;
 401                 uint64_t opc:4;
 402                 uint64_t dst:9;
 403                 uint64_t src:8;
 404 #else
 405                 uint64_t src:8;
 406                 uint64_t dst:9;
 407                 uint64_t opc:4;
 408                 uint64_t mask:8;
 409                 uint64_t reserved_29_63:35;
 410 #endif
 411         } s;
 412 };
 413
 414 union cvmx_iob_inb_control_match_enb {
 415         uint64_t u64;
 416         struct cvmx_iob_inb_control_match_enb_s {
 417 #ifdef __BIG_ENDIAN_BITFIELD
 418                 uint64_t reserved_29_63:35;
 419                 uint64_t mask:8;
 420                 uint64_t opc:4;
 421                 uint64_t dst:9;
 422                 uint64_t src:8;
 423 #else
 424                 uint64_t src:8;
 425                 uint64_t dst:9;
 426                 uint64_t opc:4;
 427                 uint64_t mask:8;
 428                 uint64_t reserved_29_63:35;
 429 #endif
 430         } s;
 431 };
 432
 433 union cvmx_iob_inb_data_match {
 434         uint64_t u64;
 435         struct cvmx_iob_inb_data_match_s {
 436 #ifdef __BIG_ENDIAN_BITFIELD
 437                 uint64_t data:64;
 438 #else
 439                 uint64_t data:64;
 440 #endif
 441         } s;
 442 };
 443
 444 union cvmx_iob_inb_data_match_enb {
 445         uint64_t u64;
 446         struct cvmx_iob_inb_data_match_enb_s {
 447 #ifdef __BIG_ENDIAN_BITFIELD
 448                 uint64_t data:64;
 449 #else
 450                 uint64_t data:64;
 451 #endif
 452         } s;
 453 };
 454
 455 union cvmx_iob_int_enb {
 456         uint64_t u64;
 457         struct cvmx_iob_int_enb_s {
 458 #ifdef __BIG_ENDIAN_BITFIELD
 459                 uint64_t reserved_6_63:58;
 460                 uint64_t p_dat:1;
 461                 uint64_t np_dat:1;
 462                 uint64_t p_eop:1;
 463                 uint64_t p_sop:1;
 464                 uint64_t np_eop:1;
 465                 uint64_t np_sop:1;
 466 #else
 467                 uint64_t np_sop:1;
 468                 uint64_t np_eop:1;
 469                 uint64_t p_sop:1;
 470                 uint64_t p_eop:1;
 471                 uint64_t np_dat:1;
 472                 uint64_t p_dat:1;
 473                 uint64_t reserved_6_63:58;
 474 #endif
 475         } s;
 476         struct cvmx_iob_int_enb_cn30xx {
 477 #ifdef __BIG_ENDIAN_BITFIELD
 478                 uint64_t reserved_4_63:60;
 479                 uint64_t p_eop:1;
 480                 uint64_t p_sop:1;
 481                 uint64_t np_eop:1;
 482                 uint64_t np_sop:1;
 483 #else
 484                 uint64_t np_sop:1;
 485                 uint64_t np_eop:1;
 486                 uint64_t p_sop:1;
 487                 uint64_t p_eop:1;
 488                 uint64_t reserved_4_63:60;
 489 #endif
 490         } cn30xx;
 491         struct cvmx_iob_int_enb_cn68xx {
 492 #ifdef __BIG_ENDIAN_BITFIELD
 493                 uint64_t reserved_0_63:64;
 494 #else
 495                 uint64_t reserved_0_63:64;
 496 #endif
 497         } cn68xx;
 498 };
 499
 500 union cvmx_iob_int_sum {
 501         uint64_t u64;
 502         struct cvmx_iob_int_sum_s {
 503 #ifdef __BIG_ENDIAN_BITFIELD
 504                 uint64_t reserved_6_63:58;
 505                 uint64_t p_dat:1;
 506                 uint64_t np_dat:1;
 507                 uint64_t p_eop:1;
 508                 uint64_t p_sop:1;
 509                 uint64_t np_eop:1;
 510                 uint64_t np_sop:1;
 511 #else
 512                 uint64_t np_sop:1;
 513                 uint64_t np_eop:1;
 514                 uint64_t p_sop:1;
 515                 uint64_t p_eop:1;
 516                 uint64_t np_dat:1;
 517                 uint64_t p_dat:1;
 518                 uint64_t reserved_6_63:58;
 519 #endif
 520         } s;
 521         struct cvmx_iob_int_sum_cn30xx {
 522 #ifdef __BIG_ENDIAN_BITFIELD
 523                 uint64_t reserved_4_63:60;
 524                 uint64_t p_eop:1;
 525                 uint64_t p_sop:1;
 526                 uint64_t np_eop:1;
 527                 uint64_t np_sop:1;
 528 #else
 529                 uint64_t np_sop:1;
 530                 uint64_t np_eop:1;
 531                 uint64_t p_sop:1;
 532                 uint64_t p_eop:1;
 533                 uint64_t reserved_4_63:60;
 534 #endif
 535         } cn30xx;
 536         struct cvmx_iob_int_sum_cn68xx {
 537 #ifdef __BIG_ENDIAN_BITFIELD
 538                 uint64_t reserved_0_63:64;
 539 #else
 540                 uint64_t reserved_0_63:64;
 541 #endif
 542         } cn68xx;
 543 };
 544
 545 union cvmx_iob_n2c_l2c_pri_cnt {
 546         uint64_t u64;
 547         struct cvmx_iob_n2c_l2c_pri_cnt_s {
 548 #ifdef __BIG_ENDIAN_BITFIELD
 549                 uint64_t reserved_16_63:48;
 550                 uint64_t cnt_enb:1;
 551                 uint64_t cnt_val:15;
 552 #else
 553                 uint64_t cnt_val:15;
 554                 uint64_t cnt_enb:1;
 555                 uint64_t reserved_16_63:48;
 556 #endif
 557         } s;
 558 };
 559
 560 union cvmx_iob_n2c_rsp_pri_cnt {
 561         uint64_t u64;
 562         struct cvmx_iob_n2c_rsp_pri_cnt_s {
 563 #ifdef __BIG_ENDIAN_BITFIELD
 564                 uint64_t reserved_16_63:48;
 565                 uint64_t cnt_enb:1;
 566                 uint64_t cnt_val:15;
 567 #else
 568                 uint64_t cnt_val:15;
 569                 uint64_t cnt_enb:1;
 570                 uint64_t reserved_16_63:48;
 571 #endif
 572         } s;
 573 };
 574
 575 union cvmx_iob_outb_com_pri_cnt {
 576         uint64_t u64;
 577         struct cvmx_iob_outb_com_pri_cnt_s {
 578 #ifdef __BIG_ENDIAN_BITFIELD
 579                 uint64_t reserved_16_63:48;
 580                 uint64_t cnt_enb:1;
 581                 uint64_t cnt_val:15;
 582 #else
 583                 uint64_t cnt_val:15;
 584                 uint64_t cnt_enb:1;
 585                 uint64_t reserved_16_63:48;
 586 #endif
 587         } s;
 588 };
 589
 590 union cvmx_iob_outb_control_match {
 591         uint64_t u64;
 592         struct cvmx_iob_outb_control_match_s {
 593 #ifdef __BIG_ENDIAN_BITFIELD
 594                 uint64_t reserved_26_63:38;
 595                 uint64_t mask:8;
 596                 uint64_t eot:1;
 597                 uint64_t dst:8;
 598                 uint64_t src:9;
 599 #else
 600                 uint64_t src:9;
 601                 uint64_t dst:8;
 602                 uint64_t eot:1;
 603                 uint64_t mask:8;
 604                 uint64_t reserved_26_63:38;
 605 #endif
 606         } s;
 607 };
 608
 609 union cvmx_iob_outb_control_match_enb {
 610         uint64_t u64;
 611         struct cvmx_iob_outb_control_match_enb_s {
 612 #ifdef __BIG_ENDIAN_BITFIELD
 613                 uint64_t reserved_26_63:38;
 614                 uint64_t mask:8;
 615                 uint64_t eot:1;
 616                 uint64_t dst:8;
 617                 uint64_t src:9;
 618 #else
 619                 uint64_t src:9;
 620                 uint64_t dst:8;
 621                 uint64_t eot:1;
 622                 uint64_t mask:8;
 623                 uint64_t reserved_26_63:38;
 624 #endif
 625         } s;
 626 };
 627
 628 union cvmx_iob_outb_data_match {
 629         uint64_t u64;
 630         struct cvmx_iob_outb_data_match_s {
 631 #ifdef __BIG_ENDIAN_BITFIELD
 632                 uint64_t data:64;
 633 #else
 634                 uint64_t data:64;
 635 #endif
 636         } s;
 637 };
 638
 639 union cvmx_iob_outb_data_match_enb {
 640         uint64_t u64;
 641         struct cvmx_iob_outb_data_match_enb_s {
 642 #ifdef __BIG_ENDIAN_BITFIELD
 643                 uint64_t data:64;
 644 #else
 645                 uint64_t data:64;
 646 #endif
 647         } s;
 648 };
 649
 650 union cvmx_iob_outb_fpa_pri_cnt {
 651         uint64_t u64;
 652         struct cvmx_iob_outb_fpa_pri_cnt_s {
 653 #ifdef __BIG_ENDIAN_BITFIELD
 654                 uint64_t reserved_16_63:48;
 655                 uint64_t cnt_enb:1;
 656                 uint64_t cnt_val:15;
 657 #else
 658                 uint64_t cnt_val:15;
 659                 uint64_t cnt_enb:1;
 660                 uint64_t reserved_16_63:48;
 661 #endif
 662         } s;
 663 };
 664
 665 union cvmx_iob_outb_req_pri_cnt {
 666         uint64_t u64;
 667         struct cvmx_iob_outb_req_pri_cnt_s {
 668 #ifdef __BIG_ENDIAN_BITFIELD
 669                 uint64_t reserved_16_63:48;
 670                 uint64_t cnt_enb:1;
 671                 uint64_t cnt_val:15;
 672 #else
 673                 uint64_t cnt_val:15;
 674                 uint64_t cnt_enb:1;
 675                 uint64_t reserved_16_63:48;
 676 #endif
 677         } s;
 678 };
 679
 680 union cvmx_iob_p2c_req_pri_cnt {
 681         uint64_t u64;
 682         struct cvmx_iob_p2c_req_pri_cnt_s {
 683 #ifdef __BIG_ENDIAN_BITFIELD
 684                 uint64_t reserved_16_63:48;
 685                 uint64_t cnt_enb:1;
 686                 uint64_t cnt_val:15;
 687 #else
 688                 uint64_t cnt_val:15;
 689                 uint64_t cnt_enb:1;
 690                 uint64_t reserved_16_63:48;
 691 #endif
 692         } s;
 693 };
 694
 695 union cvmx_iob_pkt_err {
 696         uint64_t u64;
 697         struct cvmx_iob_pkt_err_s {
 698 #ifdef __BIG_ENDIAN_BITFIELD
 699                 uint64_t reserved_12_63:52;
 700                 uint64_t vport:6;
 701                 uint64_t port:6;
 702 #else
 703                 uint64_t port:6;
 704                 uint64_t vport:6;
 705                 uint64_t reserved_12_63:52;
 706 #endif
 707         } s;
 708         struct cvmx_iob_pkt_err_cn30xx {
 709 #ifdef __BIG_ENDIAN_BITFIELD
 710                 uint64_t reserved_6_63:58;
 711                 uint64_t port:6;
 712 #else
 713                 uint64_t port:6;
 714                 uint64_t reserved_6_63:58;
 715 #endif
 716         } cn30xx;
 717 };
 718
 719 union cvmx_iob_to_cmb_credits {
 720         uint64_t u64;
 721         struct cvmx_iob_to_cmb_credits_s {
 722 #ifdef __BIG_ENDIAN_BITFIELD
 723                 uint64_t reserved_6_63:58;
 724                 uint64_t ncb_rd:3;
 725                 uint64_t ncb_wr:3;
 726 #else
 727                 uint64_t ncb_wr:3;
 728                 uint64_t ncb_rd:3;
 729                 uint64_t reserved_6_63:58;
 730 #endif
 731         } s;
 732         struct cvmx_iob_to_cmb_credits_cn52xx {
 733 #ifdef __BIG_ENDIAN_BITFIELD
 734                 uint64_t reserved_9_63:55;
 735                 uint64_t pko_rd:3;
 736                 uint64_t ncb_rd:3;
 737                 uint64_t ncb_wr:3;
 738 #else
 739                 uint64_t ncb_wr:3;
 740                 uint64_t ncb_rd:3;
 741                 uint64_t pko_rd:3;
 742                 uint64_t reserved_9_63:55;
 743 #endif
 744         } cn52xx;
 745         struct cvmx_iob_to_cmb_credits_cn68xx {
 746 #ifdef __BIG_ENDIAN_BITFIELD
 747                 uint64_t reserved_9_63:55;
 748                 uint64_t dwb:3;
 749                 uint64_t ncb_rd:3;
 750                 uint64_t ncb_wr:3;
 751 #else
 752                 uint64_t ncb_wr:3;
 753                 uint64_t ncb_rd:3;
 754                 uint64_t dwb:3;
 755                 uint64_t reserved_9_63:55;
 756 #endif
 757         } cn68xx;
 758 };
 759
 760 union cvmx_iob_to_ncb_did_00_credits {
 761         uint64_t u64;
 762         struct cvmx_iob_to_ncb_did_00_credits_s {
 763 #ifdef __BIG_ENDIAN_BITFIELD
 764                 uint64_t reserved_7_63:57;
 765                 uint64_t crd:7;
 766 #else
 767                 uint64_t crd:7;
 768                 uint64_t reserved_7_63:57;
 769 #endif
 770         } s;
 771 };
 772
 773 union cvmx_iob_to_ncb_did_111_credits {
 774         uint64_t u64;
 775         struct cvmx_iob_to_ncb_did_111_credits_s {
 776 #ifdef __BIG_ENDIAN_BITFIELD
 777                 uint64_t reserved_7_63:57;
 778                 uint64_t crd:7;
 779 #else
 780                 uint64_t crd:7;
 781                 uint64_t reserved_7_63:57;
 782 #endif
 783         } s;
 784 };
 785
 786 union cvmx_iob_to_ncb_did_223_credits {
 787         uint64_t u64;
 788         struct cvmx_iob_to_ncb_did_223_credits_s {
 789 #ifdef __BIG_ENDIAN_BITFIELD
 790                 uint64_t reserved_7_63:57;
 791                 uint64_t crd:7;
 792 #else
 793                 uint64_t crd:7;
 794                 uint64_t reserved_7_63:57;
 795 #endif
 796         } s;
 797 };
 798
 799 union cvmx_iob_to_ncb_did_24_credits {
 800         uint64_t u64;
 801         struct cvmx_iob_to_ncb_did_24_credits_s {
 802 #ifdef __BIG_ENDIAN_BITFIELD
 803                 uint64_t reserved_7_63:57;
 804                 uint64_t crd:7;
 805 #else
 806                 uint64_t crd:7;
 807                 uint64_t reserved_7_63:57;
 808 #endif
 809         } s;
 810 };
 811
 812 union cvmx_iob_to_ncb_did_32_credits {
 813         uint64_t u64;
 814         struct cvmx_iob_to_ncb_did_32_credits_s {
 815 #ifdef __BIG_ENDIAN_BITFIELD
 816                 uint64_t reserved_7_63:57;
 817                 uint64_t crd:7;
 818 #else
 819                 uint64_t crd:7;
 820                 uint64_t reserved_7_63:57;
 821 #endif
 822         } s;
 823 };
 824
 825 union cvmx_iob_to_ncb_did_40_credits {
 826         uint64_t u64;
 827         struct cvmx_iob_to_ncb_did_40_credits_s {
 828 #ifdef __BIG_ENDIAN_BITFIELD
 829                 uint64_t reserved_7_63:57;
 830                 uint64_t crd:7;
 831 #else
 832                 uint64_t crd:7;
 833                 uint64_t reserved_7_63:57;
 834 #endif
 835         } s;
 836 };
 837
 838 union cvmx_iob_to_ncb_did_55_credits {
 839         uint64_t u64;
 840         struct cvmx_iob_to_ncb_did_55_credits_s {
 841 #ifdef __BIG_ENDIAN_BITFIELD
 842                 uint64_t reserved_7_63:57;
 843                 uint64_t crd:7;
 844 #else
 845                 uint64_t crd:7;
 846                 uint64_t reserved_7_63:57;
 847 #endif
 848         } s;
 849 };
 850
 851 union cvmx_iob_to_ncb_did_64_credits {
 852         uint64_t u64;
 853         struct cvmx_iob_to_ncb_did_64_credits_s {
 854 #ifdef __BIG_ENDIAN_BITFIELD
 855                 uint64_t reserved_7_63:57;
 856                 uint64_t crd:7;
 857 #else
 858                 uint64_t crd:7;
 859                 uint64_t reserved_7_63:57;
 860 #endif
 861         } s;
 862 };
 863
 864 union cvmx_iob_to_ncb_did_79_credits {
 865         uint64_t u64;
 866         struct cvmx_iob_to_ncb_did_79_credits_s {
 867 #ifdef __BIG_ENDIAN_BITFIELD
 868                 uint64_t reserved_7_63:57;
 869                 uint64_t crd:7;
 870 #else
 871                 uint64_t crd:7;
 872                 uint64_t reserved_7_63:57;
 873 #endif
 874         } s;
 875 };
 876
 877 union cvmx_iob_to_ncb_did_96_credits {
 878         uint64_t u64;
 879         struct cvmx_iob_to_ncb_did_96_credits_s {
 880 #ifdef __BIG_ENDIAN_BITFIELD
 881                 uint64_t reserved_7_63:57;
 882                 uint64_t crd:7;
 883 #else
 884                 uint64_t crd:7;
 885                 uint64_t reserved_7_63:57;
 886 #endif
 887         } s;
 888 };
 889
 890 union cvmx_iob_to_ncb_did_98_credits {
 891         uint64_t u64;
 892         struct cvmx_iob_to_ncb_did_98_credits_s {
 893 #ifdef __BIG_ENDIAN_BITFIELD
 894                 uint64_t reserved_7_63:57;
 895                 uint64_t crd:7;
 896 #else
 897                 uint64_t crd:7;
 898                 uint64_t reserved_7_63:57;
 899 #endif
 900         } s;
 901 };
 902
 903 #endif