1 /***********************license start***************
2 * Author: Cavium Networks
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
7 * Copyright (C) 2003-2018 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
28 #ifndef __CVMX_ASXX_DEFS_H__
29 #define __CVMX_ASXX_DEFS_H__
31 #define CVMX_ASXX_GMII_RX_CLK_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000180ull))
32 #define CVMX_ASXX_GMII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000188ull))
33 #define CVMX_ASXX_INT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000018ull) + ((block_id) & 1) * 0x8000000ull)
34 #define CVMX_ASXX_INT_REG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000010ull) + ((block_id) & 1) * 0x8000000ull)
35 #define CVMX_ASXX_MII_RX_DAT_SET(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000190ull))
36 #define CVMX_ASXX_PRT_LOOP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000040ull) + ((block_id) & 1) * 0x8000000ull)
37 #define CVMX_ASXX_RLD_BYPASS(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000248ull) + ((block_id) & 1) * 0x8000000ull)
38 #define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000250ull) + ((block_id) & 1) * 0x8000000ull)
39 #define CVMX_ASXX_RLD_COMP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000220ull) + ((block_id) & 1) * 0x8000000ull)
40 #define CVMX_ASXX_RLD_DATA_DRV(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000218ull) + ((block_id) & 1) * 0x8000000ull)
41 #define CVMX_ASXX_RLD_FCRAM_MODE(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000210ull) + ((block_id) & 1) * 0x8000000ull)
42 #define CVMX_ASXX_RLD_NCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000230ull) + ((block_id) & 1) * 0x8000000ull)
43 #define CVMX_ASXX_RLD_NCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000240ull) + ((block_id) & 1) * 0x8000000ull)
44 #define CVMX_ASXX_RLD_PCTL_STRONG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000228ull) + ((block_id) & 1) * 0x8000000ull)
45 #define CVMX_ASXX_RLD_PCTL_WEAK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000238ull) + ((block_id) & 1) * 0x8000000ull)
46 #define CVMX_ASXX_RLD_SETTING(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000258ull) + ((block_id) & 1) * 0x8000000ull)
47 #define CVMX_ASXX_RX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000020ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
48 #define CVMX_ASXX_RX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000000ull) + ((block_id) & 1) * 0x8000000ull)
49 #define CVMX_ASXX_RX_WOL(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000100ull) + ((block_id) & 1) * 0x8000000ull)
50 #define CVMX_ASXX_RX_WOL_MSK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000108ull) + ((block_id) & 1) * 0x8000000ull)
51 #define CVMX_ASXX_RX_WOL_POWOK(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000118ull) + ((block_id) & 1) * 0x8000000ull)
52 #define CVMX_ASXX_RX_WOL_SIG(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000110ull) + ((block_id) & 1) * 0x8000000ull)
53 #define CVMX_ASXX_TX_CLK_SETX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
54 #define CVMX_ASXX_TX_COMP_BYP(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000068ull) + ((block_id) & 1) * 0x8000000ull)
55 #define CVMX_ASXX_TX_HI_WATERX(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800B0000080ull) + (((offset) & 3) + ((block_id) & 1) * 0x1000000ull) * 8)
56 #define CVMX_ASXX_TX_PRT_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800B0000008ull) + ((block_id) & 1) * 0x8000000ull)
58 void __cvmx_interrupt_asxx_enable(int block);
60 union cvmx_asxx_gmii_rx_clk_set {
62 struct cvmx_asxx_gmii_rx_clk_set_s {
63 #ifdef __BIG_ENDIAN_BITFIELD
64 uint64_t reserved_5_63:59;
68 uint64_t reserved_5_63:59;
71 struct cvmx_asxx_gmii_rx_clk_set_s cn30xx;
72 struct cvmx_asxx_gmii_rx_clk_set_s cn31xx;
73 struct cvmx_asxx_gmii_rx_clk_set_s cn50xx;
76 union cvmx_asxx_gmii_rx_dat_set {
78 struct cvmx_asxx_gmii_rx_dat_set_s {
79 #ifdef __BIG_ENDIAN_BITFIELD
80 uint64_t reserved_5_63:59;
84 uint64_t reserved_5_63:59;
87 struct cvmx_asxx_gmii_rx_dat_set_s cn30xx;
88 struct cvmx_asxx_gmii_rx_dat_set_s cn31xx;
89 struct cvmx_asxx_gmii_rx_dat_set_s cn50xx;
92 union cvmx_asxx_int_en {
94 struct cvmx_asxx_int_en_s {
95 #ifdef __BIG_ENDIAN_BITFIELD
96 uint64_t reserved_12_63:52;
104 uint64_t reserved_12_63:52;
107 struct cvmx_asxx_int_en_cn30xx {
108 #ifdef __BIG_ENDIAN_BITFIELD
109 uint64_t reserved_11_63:53;
111 uint64_t reserved_7_7:1;
113 uint64_t reserved_3_3:1;
117 uint64_t reserved_3_3:1;
119 uint64_t reserved_7_7:1;
121 uint64_t reserved_11_63:53;
124 struct cvmx_asxx_int_en_cn30xx cn31xx;
125 struct cvmx_asxx_int_en_s cn38xx;
126 struct cvmx_asxx_int_en_s cn38xxp2;
127 struct cvmx_asxx_int_en_cn30xx cn50xx;
128 struct cvmx_asxx_int_en_s cn58xx;
129 struct cvmx_asxx_int_en_s cn58xxp1;
132 union cvmx_asxx_int_reg {
134 struct cvmx_asxx_int_reg_s {
135 #ifdef __BIG_ENDIAN_BITFIELD
136 uint64_t reserved_12_63:52;
144 uint64_t reserved_12_63:52;
147 struct cvmx_asxx_int_reg_cn30xx {
148 #ifdef __BIG_ENDIAN_BITFIELD
149 uint64_t reserved_11_63:53;
151 uint64_t reserved_7_7:1;
153 uint64_t reserved_3_3:1;
157 uint64_t reserved_3_3:1;
159 uint64_t reserved_7_7:1;
161 uint64_t reserved_11_63:53;
164 struct cvmx_asxx_int_reg_cn30xx cn31xx;
165 struct cvmx_asxx_int_reg_s cn38xx;
166 struct cvmx_asxx_int_reg_s cn38xxp2;
167 struct cvmx_asxx_int_reg_cn30xx cn50xx;
168 struct cvmx_asxx_int_reg_s cn58xx;
169 struct cvmx_asxx_int_reg_s cn58xxp1;
172 union cvmx_asxx_mii_rx_dat_set {
174 struct cvmx_asxx_mii_rx_dat_set_s {
175 #ifdef __BIG_ENDIAN_BITFIELD
176 uint64_t reserved_5_63:59;
180 uint64_t reserved_5_63:59;
183 struct cvmx_asxx_mii_rx_dat_set_s cn30xx;
184 struct cvmx_asxx_mii_rx_dat_set_s cn50xx;
187 union cvmx_asxx_prt_loop {
189 struct cvmx_asxx_prt_loop_s {
190 #ifdef __BIG_ENDIAN_BITFIELD
191 uint64_t reserved_8_63:56;
197 uint64_t reserved_8_63:56;
200 struct cvmx_asxx_prt_loop_cn30xx {
201 #ifdef __BIG_ENDIAN_BITFIELD
202 uint64_t reserved_7_63:57;
204 uint64_t reserved_3_3:1;
208 uint64_t reserved_3_3:1;
210 uint64_t reserved_7_63:57;
213 struct cvmx_asxx_prt_loop_cn30xx cn31xx;
214 struct cvmx_asxx_prt_loop_s cn38xx;
215 struct cvmx_asxx_prt_loop_s cn38xxp2;
216 struct cvmx_asxx_prt_loop_cn30xx cn50xx;
217 struct cvmx_asxx_prt_loop_s cn58xx;
218 struct cvmx_asxx_prt_loop_s cn58xxp1;
221 union cvmx_asxx_rld_bypass {
223 struct cvmx_asxx_rld_bypass_s {
224 #ifdef __BIG_ENDIAN_BITFIELD
225 uint64_t reserved_1_63:63;
229 uint64_t reserved_1_63:63;
232 struct cvmx_asxx_rld_bypass_s cn38xx;
233 struct cvmx_asxx_rld_bypass_s cn38xxp2;
234 struct cvmx_asxx_rld_bypass_s cn58xx;
235 struct cvmx_asxx_rld_bypass_s cn58xxp1;
238 union cvmx_asxx_rld_bypass_setting {
240 struct cvmx_asxx_rld_bypass_setting_s {
241 #ifdef __BIG_ENDIAN_BITFIELD
242 uint64_t reserved_5_63:59;
246 uint64_t reserved_5_63:59;
249 struct cvmx_asxx_rld_bypass_setting_s cn38xx;
250 struct cvmx_asxx_rld_bypass_setting_s cn38xxp2;
251 struct cvmx_asxx_rld_bypass_setting_s cn58xx;
252 struct cvmx_asxx_rld_bypass_setting_s cn58xxp1;
255 union cvmx_asxx_rld_comp {
257 struct cvmx_asxx_rld_comp_s {
258 #ifdef __BIG_ENDIAN_BITFIELD
259 uint64_t reserved_9_63:55;
265 uint64_t reserved_9_63:55;
268 struct cvmx_asxx_rld_comp_cn38xx {
269 #ifdef __BIG_ENDIAN_BITFIELD
270 uint64_t reserved_8_63:56;
276 uint64_t reserved_8_63:56;
279 struct cvmx_asxx_rld_comp_cn38xx cn38xxp2;
280 struct cvmx_asxx_rld_comp_s cn58xx;
281 struct cvmx_asxx_rld_comp_s cn58xxp1;
284 union cvmx_asxx_rld_data_drv {
286 struct cvmx_asxx_rld_data_drv_s {
287 #ifdef __BIG_ENDIAN_BITFIELD
288 uint64_t reserved_8_63:56;
294 uint64_t reserved_8_63:56;
297 struct cvmx_asxx_rld_data_drv_s cn38xx;
298 struct cvmx_asxx_rld_data_drv_s cn38xxp2;
299 struct cvmx_asxx_rld_data_drv_s cn58xx;
300 struct cvmx_asxx_rld_data_drv_s cn58xxp1;
303 union cvmx_asxx_rld_fcram_mode {
305 struct cvmx_asxx_rld_fcram_mode_s {
306 #ifdef __BIG_ENDIAN_BITFIELD
307 uint64_t reserved_1_63:63;
311 uint64_t reserved_1_63:63;
314 struct cvmx_asxx_rld_fcram_mode_s cn38xx;
315 struct cvmx_asxx_rld_fcram_mode_s cn38xxp2;
318 union cvmx_asxx_rld_nctl_strong {
320 struct cvmx_asxx_rld_nctl_strong_s {
321 #ifdef __BIG_ENDIAN_BITFIELD
322 uint64_t reserved_5_63:59;
326 uint64_t reserved_5_63:59;
329 struct cvmx_asxx_rld_nctl_strong_s cn38xx;
330 struct cvmx_asxx_rld_nctl_strong_s cn38xxp2;
331 struct cvmx_asxx_rld_nctl_strong_s cn58xx;
332 struct cvmx_asxx_rld_nctl_strong_s cn58xxp1;
335 union cvmx_asxx_rld_nctl_weak {
337 struct cvmx_asxx_rld_nctl_weak_s {
338 #ifdef __BIG_ENDIAN_BITFIELD
339 uint64_t reserved_5_63:59;
343 uint64_t reserved_5_63:59;
346 struct cvmx_asxx_rld_nctl_weak_s cn38xx;
347 struct cvmx_asxx_rld_nctl_weak_s cn38xxp2;
348 struct cvmx_asxx_rld_nctl_weak_s cn58xx;
349 struct cvmx_asxx_rld_nctl_weak_s cn58xxp1;
352 union cvmx_asxx_rld_pctl_strong {
354 struct cvmx_asxx_rld_pctl_strong_s {
355 #ifdef __BIG_ENDIAN_BITFIELD
356 uint64_t reserved_5_63:59;
360 uint64_t reserved_5_63:59;
363 struct cvmx_asxx_rld_pctl_strong_s cn38xx;
364 struct cvmx_asxx_rld_pctl_strong_s cn38xxp2;
365 struct cvmx_asxx_rld_pctl_strong_s cn58xx;
366 struct cvmx_asxx_rld_pctl_strong_s cn58xxp1;
369 union cvmx_asxx_rld_pctl_weak {
371 struct cvmx_asxx_rld_pctl_weak_s {
372 #ifdef __BIG_ENDIAN_BITFIELD
373 uint64_t reserved_5_63:59;
377 uint64_t reserved_5_63:59;
380 struct cvmx_asxx_rld_pctl_weak_s cn38xx;
381 struct cvmx_asxx_rld_pctl_weak_s cn38xxp2;
382 struct cvmx_asxx_rld_pctl_weak_s cn58xx;
383 struct cvmx_asxx_rld_pctl_weak_s cn58xxp1;
386 union cvmx_asxx_rld_setting {
388 struct cvmx_asxx_rld_setting_s {
389 #ifdef __BIG_ENDIAN_BITFIELD
390 uint64_t reserved_13_63:51;
402 uint64_t reserved_13_63:51;
405 struct cvmx_asxx_rld_setting_cn38xx {
406 #ifdef __BIG_ENDIAN_BITFIELD
407 uint64_t reserved_5_63:59;
411 uint64_t reserved_5_63:59;
414 struct cvmx_asxx_rld_setting_cn38xx cn38xxp2;
415 struct cvmx_asxx_rld_setting_s cn58xx;
416 struct cvmx_asxx_rld_setting_s cn58xxp1;
419 union cvmx_asxx_rx_clk_setx {
421 struct cvmx_asxx_rx_clk_setx_s {
422 #ifdef __BIG_ENDIAN_BITFIELD
423 uint64_t reserved_5_63:59;
427 uint64_t reserved_5_63:59;
430 struct cvmx_asxx_rx_clk_setx_s cn30xx;
431 struct cvmx_asxx_rx_clk_setx_s cn31xx;
432 struct cvmx_asxx_rx_clk_setx_s cn38xx;
433 struct cvmx_asxx_rx_clk_setx_s cn38xxp2;
434 struct cvmx_asxx_rx_clk_setx_s cn50xx;
435 struct cvmx_asxx_rx_clk_setx_s cn58xx;
436 struct cvmx_asxx_rx_clk_setx_s cn58xxp1;
439 union cvmx_asxx_rx_prt_en {
441 struct cvmx_asxx_rx_prt_en_s {
442 #ifdef __BIG_ENDIAN_BITFIELD
443 uint64_t reserved_4_63:60;
447 uint64_t reserved_4_63:60;
450 struct cvmx_asxx_rx_prt_en_cn30xx {
451 #ifdef __BIG_ENDIAN_BITFIELD
452 uint64_t reserved_3_63:61;
456 uint64_t reserved_3_63:61;
459 struct cvmx_asxx_rx_prt_en_cn30xx cn31xx;
460 struct cvmx_asxx_rx_prt_en_s cn38xx;
461 struct cvmx_asxx_rx_prt_en_s cn38xxp2;
462 struct cvmx_asxx_rx_prt_en_cn30xx cn50xx;
463 struct cvmx_asxx_rx_prt_en_s cn58xx;
464 struct cvmx_asxx_rx_prt_en_s cn58xxp1;
467 union cvmx_asxx_rx_wol {
469 struct cvmx_asxx_rx_wol_s {
470 #ifdef __BIG_ENDIAN_BITFIELD
471 uint64_t reserved_2_63:62;
477 uint64_t reserved_2_63:62;
480 struct cvmx_asxx_rx_wol_s cn38xx;
481 struct cvmx_asxx_rx_wol_s cn38xxp2;
484 union cvmx_asxx_rx_wol_msk {
486 struct cvmx_asxx_rx_wol_msk_s {
487 #ifdef __BIG_ENDIAN_BITFIELD
493 struct cvmx_asxx_rx_wol_msk_s cn38xx;
494 struct cvmx_asxx_rx_wol_msk_s cn38xxp2;
497 union cvmx_asxx_rx_wol_powok {
499 struct cvmx_asxx_rx_wol_powok_s {
500 #ifdef __BIG_ENDIAN_BITFIELD
501 uint64_t reserved_1_63:63;
505 uint64_t reserved_1_63:63;
508 struct cvmx_asxx_rx_wol_powok_s cn38xx;
509 struct cvmx_asxx_rx_wol_powok_s cn38xxp2;
512 union cvmx_asxx_rx_wol_sig {
514 struct cvmx_asxx_rx_wol_sig_s {
515 #ifdef __BIG_ENDIAN_BITFIELD
516 uint64_t reserved_32_63:32;
520 uint64_t reserved_32_63:32;
523 struct cvmx_asxx_rx_wol_sig_s cn38xx;
524 struct cvmx_asxx_rx_wol_sig_s cn38xxp2;
527 union cvmx_asxx_tx_clk_setx {
529 struct cvmx_asxx_tx_clk_setx_s {
530 #ifdef __BIG_ENDIAN_BITFIELD
531 uint64_t reserved_5_63:59;
535 uint64_t reserved_5_63:59;
538 struct cvmx_asxx_tx_clk_setx_s cn30xx;
539 struct cvmx_asxx_tx_clk_setx_s cn31xx;
540 struct cvmx_asxx_tx_clk_setx_s cn38xx;
541 struct cvmx_asxx_tx_clk_setx_s cn38xxp2;
542 struct cvmx_asxx_tx_clk_setx_s cn50xx;
543 struct cvmx_asxx_tx_clk_setx_s cn58xx;
544 struct cvmx_asxx_tx_clk_setx_s cn58xxp1;
547 union cvmx_asxx_tx_comp_byp {
549 struct cvmx_asxx_tx_comp_byp_s {
550 #ifdef __BIG_ENDIAN_BITFIELD
551 uint64_t reserved_0_63:64;
553 uint64_t reserved_0_63:64;
556 struct cvmx_asxx_tx_comp_byp_cn30xx {
557 #ifdef __BIG_ENDIAN_BITFIELD
558 uint64_t reserved_9_63:55;
566 uint64_t reserved_9_63:55;
569 struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx;
570 struct cvmx_asxx_tx_comp_byp_cn38xx {
571 #ifdef __BIG_ENDIAN_BITFIELD
572 uint64_t reserved_8_63:56;
578 uint64_t reserved_8_63:56;
581 struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2;
582 struct cvmx_asxx_tx_comp_byp_cn50xx {
583 #ifdef __BIG_ENDIAN_BITFIELD
584 uint64_t reserved_17_63:47;
586 uint64_t reserved_13_15:3;
588 uint64_t reserved_5_7:3;
592 uint64_t reserved_5_7:3;
594 uint64_t reserved_13_15:3;
596 uint64_t reserved_17_63:47;
599 struct cvmx_asxx_tx_comp_byp_cn58xx {
600 #ifdef __BIG_ENDIAN_BITFIELD
601 uint64_t reserved_13_63:51;
603 uint64_t reserved_5_7:3;
607 uint64_t reserved_5_7:3;
609 uint64_t reserved_13_63:51;
612 struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1;
615 union cvmx_asxx_tx_hi_waterx {
617 struct cvmx_asxx_tx_hi_waterx_s {
618 #ifdef __BIG_ENDIAN_BITFIELD
619 uint64_t reserved_4_63:60;
623 uint64_t reserved_4_63:60;
626 struct cvmx_asxx_tx_hi_waterx_cn30xx {
627 #ifdef __BIG_ENDIAN_BITFIELD
628 uint64_t reserved_3_63:61;
632 uint64_t reserved_3_63:61;
635 struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx;
636 struct cvmx_asxx_tx_hi_waterx_s cn38xx;
637 struct cvmx_asxx_tx_hi_waterx_s cn38xxp2;
638 struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx;
639 struct cvmx_asxx_tx_hi_waterx_s cn58xx;
640 struct cvmx_asxx_tx_hi_waterx_s cn58xxp1;
643 union cvmx_asxx_tx_prt_en {
645 struct cvmx_asxx_tx_prt_en_s {
646 #ifdef __BIG_ENDIAN_BITFIELD
647 uint64_t reserved_4_63:60;
651 uint64_t reserved_4_63:60;
654 struct cvmx_asxx_tx_prt_en_cn30xx {
655 #ifdef __BIG_ENDIAN_BITFIELD
656 uint64_t reserved_3_63:61;
660 uint64_t reserved_3_63:61;
663 struct cvmx_asxx_tx_prt_en_cn30xx cn31xx;
664 struct cvmx_asxx_tx_prt_en_s cn38xx;
665 struct cvmx_asxx_tx_prt_en_s cn38xxp2;
666 struct cvmx_asxx_tx_prt_en_cn30xx cn50xx;
667 struct cvmx_asxx_tx_prt_en_s cn58xx;
668 struct cvmx_asxx_tx_prt_en_s cn58xxp1;