arch/mips/include/asm/mmu_context.h

   1 /*
   2  * Switch a MMU context.
   3  *
   4  * This file is subject to the terms and conditions of the GNU General Public
   5  * License.  See the file "COPYING" in the main directory of this archive
   6  * for more details.
   7  *
   8  * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
   9  * Copyright (C) 1999 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_MMU_CONTEXT_H
  12 #define _ASM_MMU_CONTEXT_H
  13
  14 #include <linux/errno.h>
  15 #include <linux/sched.h>
  16 #include <linux/mm_types.h>
  17 #include <linux/smp.h>
  18 #include <linux/slab.h>
  19
  20 #include <asm/cacheflush.h>
  21 #include <asm/dsemul.h>
  22 #include <asm/hazards.h>
  23 #include <asm/tlbflush.h>
  24 #include <asm-generic/mm_hooks.h>
  25
  26 #define htw_set_pwbase(pgd)                                             \
  27 do {                                                                    \
  28         if (cpu_has_htw) {                                              \
  29                 write_c0_pwbase(pgd);                                   \
  30                 back_to_back_c0_hazard();                               \
  31         }                                                               \
  32 } while (0)
  33
  34 extern void tlbmiss_handler_setup_pgd(unsigned long);
  35 extern char tlbmiss_handler_setup_pgd_end[];
  36
  37 /* Note: This is also implemented with uasm in arch/mips/kvm/entry.c */
  38 #define TLBMISS_HANDLER_SETUP_PGD(pgd)                                  \
  39 do {                                                                    \
  40         tlbmiss_handler_setup_pgd((unsigned long)(pgd));                \
  41         htw_set_pwbase((unsigned long)pgd);                             \
  42 } while (0)
  43
  44 #ifdef CONFIG_MIPS_PGD_C0_CONTEXT
  45
  46 #define TLBMISS_HANDLER_RESTORE()                                       \
  47         write_c0_xcontext((unsigned long) smp_processor_id() <<         \
  48                           SMP_CPUID_REGSHIFT)
  49
  50 #define TLBMISS_HANDLER_SETUP()                                         \
  51         do {                                                            \
  52                 TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir);              \
  53                 TLBMISS_HANDLER_RESTORE();                              \
  54         } while (0)
  55
  56 #else /* !CONFIG_MIPS_PGD_C0_CONTEXT: using  pgd_current*/
  57
  58 /*
  59  * For the fast tlb miss handlers, we keep a per cpu array of pointers
  60  * to the current pgd for each processor. Also, the proc. id is stuffed
  61  * into the context register.
  62  */
  63 extern unsigned long pgd_current[];
  64
  65 #define TLBMISS_HANDLER_RESTORE()                                       \
  66         write_c0_context((unsigned long) smp_processor_id() <<          \
  67                          SMP_CPUID_REGSHIFT)
  68
  69 #define TLBMISS_HANDLER_SETUP()                                         \
  70         TLBMISS_HANDLER_RESTORE();                                      \
  71         back_to_back_c0_hazard();                                       \
  72         TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
  73 #endif /* CONFIG_MIPS_PGD_C0_CONTEXT*/
  74
  75 /*
  76  *  All unused by hardware upper bits will be considered
  77  *  as a software asid extension.
  78  */
  79 static unsigned long asid_version_mask(unsigned int cpu)
  80 {
  81         unsigned long asid_mask = cpu_asid_mask(&cpu_data[cpu]);
  82
  83         return ~(asid_mask | (asid_mask - 1));
  84 }
  85
  86 static unsigned long asid_first_version(unsigned int cpu)
  87 {
  88         return ~asid_version_mask(cpu) + 1;
  89 }
  90
  91 #define cpu_context(cpu, mm)    ((mm)->context.asid[cpu])
  92 #define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
  93 #define cpu_asid(cpu, mm) \
  94         (cpu_context((cpu), (mm)) & cpu_asid_mask(&cpu_data[cpu]))
  95
  96 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  97 {
  98 }
  99
 100
 101 /* Normal, classic MIPS get_new_mmu_context */
 102 static inline void
 103 get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
 104 {
 105         unsigned long asid = asid_cache(cpu);
 106
 107         if (!((asid += cpu_asid_inc()) & cpu_asid_mask(&cpu_data[cpu]))) {
 108                 if (cpu_has_vtag_icache)
 109                         flush_icache_all();
 110                 local_flush_tlb_all();  /* start new asid cycle */
 111                 if (!asid)              /* fix version if needed */
 112                         asid = asid_first_version(cpu);
 113         }
 114
 115         cpu_context(cpu, mm) = asid_cache(cpu) = asid;
 116 }
 117
 118 /*
 119  * Initialize the context related info for a new mm_struct
 120  * instance.
 121  */
 122 static inline int
 123 init_new_context(struct task_struct *tsk, struct mm_struct *mm)
 124 {
 125         int i;
 126
 127         for_each_possible_cpu(i)
 128                 cpu_context(i, mm) = 0;
 129
 130         mm->context.bd_emupage_allocmap = NULL;
 131         spin_lock_init(&mm->context.bd_emupage_lock);
 132         init_waitqueue_head(&mm->context.bd_emupage_queue);
 133
 134         return 0;
 135 }
 136
 137 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
 138                              struct task_struct *tsk)
 139 {
 140         unsigned int cpu = smp_processor_id();
 141         unsigned long flags;
 142         local_irq_save(flags);
 143
 144         htw_stop();
 145         /* Check if our ASID is of an older version and thus invalid */
 146         if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & asid_version_mask(cpu))
 147                 get_new_mmu_context(next, cpu);
 148         write_c0_entryhi(cpu_asid(cpu, next));
 149         TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 150
 151         /*
 152          * Mark current->active_mm as not "active" anymore.
 153          * We don't want to mislead possible IPI tlb flush routines.
 154          */
 155         cpumask_clear_cpu(cpu, mm_cpumask(prev));
 156         cpumask_set_cpu(cpu, mm_cpumask(next));
 157         htw_start();
 158
 159         local_irq_restore(flags);
 160 }
 161
 162 /*
 163  * Destroy context related info for an mm_struct that is about
 164  * to be put to rest.
 165  */
 166 static inline void destroy_context(struct mm_struct *mm)
 167 {
 168         dsemul_mm_cleanup(mm);
 169 }
 170
 171 #define deactivate_mm(tsk, mm)  do { } while (0)
 172
 173 /*
 174  * After we have set current->mm to a new value, this activates
 175  * the context for the new mm so we see the new mappings.
 176  */
 177 static inline void
 178 activate_mm(struct mm_struct *prev, struct mm_struct *next)
 179 {
 180         unsigned long flags;
 181         unsigned int cpu = smp_processor_id();
 182
 183         local_irq_save(flags);
 184
 185         htw_stop();
 186         /* Unconditionally get a new ASID.  */
 187         get_new_mmu_context(next, cpu);
 188
 189         write_c0_entryhi(cpu_asid(cpu, next));
 190         TLBMISS_HANDLER_SETUP_PGD(next->pgd);
 191
 192         /* mark mmu ownership change */
 193         cpumask_clear_cpu(cpu, mm_cpumask(prev));
 194         cpumask_set_cpu(cpu, mm_cpumask(next));
 195         htw_start();
 196
 197         local_irq_restore(flags);
 198 }
 199
 200 /*
 201  * If mm is currently active_mm, we can't really drop it.  Instead,
 202  * we will get a new one for it.
 203  */
 204 static inline void
 205 drop_mmu_context(struct mm_struct *mm, unsigned cpu)
 206 {
 207         unsigned long flags;
 208
 209         local_irq_save(flags);
 210         htw_stop();
 211
 212         if (cpumask_test_cpu(cpu, mm_cpumask(mm)))  {
 213                 get_new_mmu_context(mm, cpu);
 214                 write_c0_entryhi(cpu_asid(cpu, mm));
 215         } else {
 216                 /* will get a new context next time */
 217                 cpu_context(cpu, mm) = 0;
 218         }
 219         htw_start();
 220         local_irq_restore(flags);
 221 }
 222
 223 #endif /* _ASM_MMU_CONTEXT_H */