arch/mips/include/asm/mach-excite/excite.h

   1 #ifndef __EXCITE_H__
   2 #define __EXCITE_H__
   3
   4 #include <linux/init.h>
   5 #include <asm/addrspace.h>
   6 #include <asm/types.h>
   7
   8 #define EXCITE_CPU_EXT_CLOCK 100000000
   9
  10 #if !defined(__ASSEMBLY__)
  11 void __init excite_kgdb_init(void);
  12 void excite_procfs_init(void);
  13 extern unsigned long memsize;
  14 extern char modetty[];
  15 extern u32 unit_id;
  16 #endif
  17
  18 /* Base name for XICAP devices */
  19 #define XICAP_NAME      "xicap_gpi"
  20
  21 /* OCD register offsets */
  22 #define LKB0            0x0038
  23 #define LKB5            0x0128
  24 #define LKM5            0x012C
  25 #define LKB7            0x0138
  26 #define LKM7            0x013c
  27 #define LKB8            0x0140
  28 #define LKM8            0x0144
  29 #define LKB9            0x0148
  30 #define LKM9            0x014c
  31 #define LKB10           0x0150
  32 #define LKM10           0x0154
  33 #define LKB11           0x0158
  34 #define LKM11           0x015c
  35 #define LKB12           0x0160
  36 #define LKM12           0x0164
  37 #define LKB13           0x0168
  38 #define LKM13           0x016c
  39 #define LDP0            0x0200
  40 #define LDP1            0x0210
  41 #define LDP2            0x0220
  42 #define LDP3            0x0230
  43 #define INTPIN0         0x0A40
  44 #define INTPIN1         0x0A44
  45 #define INTPIN2         0x0A48
  46 #define INTPIN3         0x0A4C
  47 #define INTPIN4         0x0A50
  48 #define INTPIN5         0x0A54
  49 #define INTPIN6         0x0A58
  50 #define INTPIN7         0x0A5C
  51
  52
  53
  54
  55 /* TITAN register offsets */
  56 #define CPRR            0x0004
  57 #define CPDSR           0x0008
  58 #define CPTC0R          0x000c
  59 #define CPTC1R          0x0010
  60 #define CPCFG0          0x0020
  61 #define CPCFG1          0x0024
  62 #define CPDST0A         0x0028
  63 #define CPDST0B         0x002c
  64 #define CPDST1A         0x0030
  65 #define CPDST1B         0x0034
  66 #define CPXDSTA         0x0038
  67 #define CPXDSTB         0x003c
  68 #define CPXCISRA        0x0048
  69 #define CPXCISRB        0x004c
  70 #define CPGIG0ER        0x0050
  71 #define CPGIG1ER        0x0054
  72 #define CPGRWL          0x0068
  73 #define CPURSLMT        0x00f8
  74 #define UACFG           0x0200
  75 #define UAINTS          0x0204
  76 #define SDRXFCIE        0x4828
  77 #define SDTXFCIE        0x4928
  78 #define INTP0Status0    0x1B00
  79 #define INTP0Mask0      0x1B04
  80 #define INTP0Set0       0x1B08
  81 #define INTP0Clear0     0x1B0C
  82 #define GXCFG           0x5000
  83 #define GXDMADRPFX      0x5018
  84 #define GXDMA_DESCADR   0x501c
  85 #define GXCH0TDESSTRT   0x5054
  86
  87 /* IRQ definitions */
  88 #define NMICONFIG               0xac0
  89 #define TITAN_MSGINT    0xc4
  90 #define TITAN_IRQ       ((TITAN_MSGINT / 0x20) + 2)
  91 #define FPGA0_MSGINT    0x5a
  92 #define FPGA0_IRQ       ((FPGA0_MSGINT / 0x20) + 2)
  93 #define FPGA1_MSGINT    0x7b
  94 #define FPGA1_IRQ       ((FPGA1_MSGINT / 0x20) + 2)
  95 #define PHY_MSGINT      0x9c
  96 #define PHY_IRQ         ((PHY_MSGINT   / 0x20) + 2)
  97
  98 #if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
  99 /* Pre-release units used interrupt pin #9 */
 100 #define USB_IRQ         11
 101 #else
 102 /* Re-designed units use interrupt pin #1 */
 103 #define USB_MSGINT      0x39
 104 #define USB_IRQ         ((USB_MSGINT / 0x20) + 2)
 105 #endif
 106 #define TIMER_IRQ       12
 107
 108
 109 /* Device address ranges */
 110 #define EXCITE_OFFS_OCD         0x1fffc000
 111 #define EXCITE_SIZE_OCD         (16 * 1024)
 112 #define EXCITE_PHYS_OCD         CPHYSADDR(EXCITE_OFFS_OCD)
 113 #define EXCITE_ADDR_OCD         CKSEG1ADDR(EXCITE_OFFS_OCD)
 114
 115 #define EXCITE_OFFS_SCRAM       0x1fffa000
 116 #define EXCITE_SIZE_SCRAM       (8 << 10)
 117 #define EXCITE_PHYS_SCRAM       CPHYSADDR(EXCITE_OFFS_SCRAM)
 118 #define EXCITE_ADDR_SCRAM       CKSEG1ADDR(EXCITE_OFFS_SCRAM)
 119
 120 #define EXCITE_OFFS_PCI_IO      0x1fff8000
 121 #define EXCITE_SIZE_PCI_IO      (8 << 10)
 122 #define EXCITE_PHYS_PCI_IO      CPHYSADDR(EXCITE_OFFS_PCI_IO)
 123 #define EXCITE_ADDR_PCI_IO      CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
 124
 125 #define EXCITE_OFFS_TITAN       0x1fff0000
 126 #define EXCITE_SIZE_TITAN       (32 << 10)
 127 #define EXCITE_PHYS_TITAN       CPHYSADDR(EXCITE_OFFS_TITAN)
 128 #define EXCITE_ADDR_TITAN       CKSEG1ADDR(EXCITE_OFFS_TITAN)
 129
 130 #define EXCITE_OFFS_PCI_MEM     0x1ffe0000
 131 #define EXCITE_SIZE_PCI_MEM     (64 << 10)
 132 #define EXCITE_PHYS_PCI_MEM     CPHYSADDR(EXCITE_OFFS_PCI_MEM)
 133 #define EXCITE_ADDR_PCI_MEM     CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
 134
 135 #define EXCITE_OFFS_FPGA        0x1ffdc000
 136 #define EXCITE_SIZE_FPGA        (16 << 10)
 137 #define EXCITE_PHYS_FPGA        CPHYSADDR(EXCITE_OFFS_FPGA)
 138 #define EXCITE_ADDR_FPGA        CKSEG1ADDR(EXCITE_OFFS_FPGA)
 139
 140 #define EXCITE_OFFS_NAND        0x1ffd8000
 141 #define EXCITE_SIZE_NAND        (16 << 10)
 142 #define EXCITE_PHYS_NAND        CPHYSADDR(EXCITE_OFFS_NAND)
 143 #define EXCITE_ADDR_NAND        CKSEG1ADDR(EXCITE_OFFS_NAND)
 144
 145 #define EXCITE_OFFS_BOOTROM     0x1f000000
 146 #define EXCITE_SIZE_BOOTROM     (8 << 20)
 147 #define EXCITE_PHYS_BOOTROM     CPHYSADDR(EXCITE_OFFS_BOOTROM)
 148 #define EXCITE_ADDR_BOOTROM     CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
 149
 150 /* FPGA address offsets */
 151 #define EXCITE_FPGA_DPR         0x0104  /* dual-ported ram */
 152 #define EXCITE_FPGA_SYSCTL      0x0200  /* system control register block */
 153
 154 #endif /* __EXCITE_H__ */