arch/mips/alchemy/common/irq.c

   1 /*
   2  * Copyright 2001, 2007-2008 MontaVista Software Inc.
   3  * Author: MontaVista Software, Inc. <source@mvista.com>
   4  *
   5  * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
   6  *
   7  *  This program is free software; you can redistribute  it and/or modify it
   8  *  under  the terms of  the GNU General  Public License as published by the
   9  *  Free Software Foundation;  either version 2 of the  License, or (at your
  10  *  option) any later version.
  11  *
  12  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  13  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  14  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  15  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  16  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  18  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  20  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  *  You should have received a copy of the  GNU General Public License along
  24  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  25  *  675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27
  28 #include <linux/bitops.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/slab.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/irq_cpu.h>
  36 #include <asm/mipsregs.h>
  37 #include <asm/mach-au1x00/au1000.h>
  38 #ifdef CONFIG_MIPS_PB1000
  39 #include <asm/mach-pb1x00/pb1000.h>
  40 #endif
  41
  42 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type);
  43
  44 /* NOTE on interrupt priorities: The original writers of this code said:
  45  *
  46  * Because of the tight timing of SETUP token to reply transactions,
  47  * the USB devices-side packet complete interrupt (USB_DEV_REQ_INT)
  48  * needs the highest priority.
  49  */
  50
  51 /* per-processor fixed function irqs */
  52 struct au1xxx_irqmap {
  53         int im_irq;
  54         int im_type;
  55         int im_request;         /* set 1 to get higher priority */
  56 };
  57
  58 struct au1xxx_irqmap au1000_irqmap[] __initdata = {
  59         { AU1000_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  60         { AU1000_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  61         { AU1000_UART2_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  62         { AU1000_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  63         { AU1000_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
  64         { AU1000_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
  65         { AU1000_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
  66         { AU1000_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
  67         { AU1000_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
  68         { AU1000_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
  69         { AU1000_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
  70         { AU1000_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
  71         { AU1000_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
  72         { AU1000_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
  73         { AU1000_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
  74         { AU1000_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  75         { AU1000_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  76         { AU1000_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  77         { AU1000_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
  78         { AU1000_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  79         { AU1000_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
  80         { AU1000_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
  81         { AU1000_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
  82         { AU1000_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
  83         { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
  84         { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
  85         { AU1000_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
  86         { AU1000_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
  87         { AU1000_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
  88         { AU1000_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
  89         { AU1000_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
  90         { -1, },
  91 };
  92
  93 struct au1xxx_irqmap au1500_irqmap[] __initdata = {
  94         { AU1500_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  95         { AU1500_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
  96         { AU1500_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
  97         { AU1500_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
  98         { AU1500_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
  99         { AU1500_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
 100         { AU1500_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
 101         { AU1500_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
 102         { AU1500_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
 103         { AU1500_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
 104         { AU1500_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
 105         { AU1500_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
 106         { AU1500_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
 107         { AU1500_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
 108         { AU1500_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 109         { AU1500_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 110         { AU1500_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 111         { AU1500_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 112         { AU1500_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 113         { AU1500_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 114         { AU1500_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 115         { AU1500_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 116         { AU1500_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 117         { AU1500_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 118         { AU1500_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 119         { AU1500_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
 120         { AU1500_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 121         { AU1500_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 122         { AU1500_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
 123         { -1, },
 124 };
 125
 126 struct au1xxx_irqmap au1100_irqmap[] __initdata = {
 127         { AU1100_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 128         { AU1100_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 129         { AU1100_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
 130         { AU1100_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 131         { AU1100_SSI0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 132         { AU1100_SSI1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 133         { AU1100_DMA_INT_BASE,    IRQ_TYPE_LEVEL_HIGH,  0 },
 134         { AU1100_DMA_INT_BASE+1,  IRQ_TYPE_LEVEL_HIGH,  0 },
 135         { AU1100_DMA_INT_BASE+2,  IRQ_TYPE_LEVEL_HIGH,  0 },
 136         { AU1100_DMA_INT_BASE+3,  IRQ_TYPE_LEVEL_HIGH,  0 },
 137         { AU1100_DMA_INT_BASE+4,  IRQ_TYPE_LEVEL_HIGH,  0 },
 138         { AU1100_DMA_INT_BASE+5,  IRQ_TYPE_LEVEL_HIGH,  0 },
 139         { AU1100_DMA_INT_BASE+6,  IRQ_TYPE_LEVEL_HIGH,  0 },
 140         { AU1100_DMA_INT_BASE+7,  IRQ_TYPE_LEVEL_HIGH,  0 },
 141         { AU1100_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 142         { AU1100_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 143         { AU1100_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 144         { AU1100_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 145         { AU1100_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 146         { AU1100_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 147         { AU1100_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 148         { AU1100_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 149         { AU1100_IRDA_TX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
 150         { AU1100_IRDA_RX_INT,     IRQ_TYPE_LEVEL_HIGH,  0 },
 151         { AU1100_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 152         { AU1100_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 153         { AU1100_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 154         { AU1100_ACSYNC_INT,      IRQ_TYPE_EDGE_RISING, 0 },
 155         { AU1100_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 156         { AU1100_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 157         { AU1100_AC97C_INT,       IRQ_TYPE_EDGE_RISING, 0 },
 158         { -1, },
 159 };
 160
 161 struct au1xxx_irqmap au1550_irqmap[] __initdata = {
 162         { AU1550_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 163         { AU1550_PCI_INTA,        IRQ_TYPE_LEVEL_LOW,   0 },
 164         { AU1550_PCI_INTB,        IRQ_TYPE_LEVEL_LOW,   0 },
 165         { AU1550_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 166         { AU1550_CRYPTO_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 167         { AU1550_PCI_INTC,        IRQ_TYPE_LEVEL_LOW,   0 },
 168         { AU1550_PCI_INTD,        IRQ_TYPE_LEVEL_LOW,   0 },
 169         { AU1550_PCI_RST_INT,     IRQ_TYPE_LEVEL_LOW,   0 },
 170         { AU1550_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 171         { AU1550_UART3_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 172         { AU1550_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 173         { AU1550_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 174         { AU1550_PSC2_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 175         { AU1550_PSC3_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 176         { AU1550_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 177         { AU1550_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 178         { AU1550_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 179         { AU1550_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 180         { AU1550_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 181         { AU1550_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 182         { AU1550_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 183         { AU1550_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 184         { AU1550_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
 185         { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH,  1 },
 186         { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 },
 187         { AU1550_USB_HOST_INT,    IRQ_TYPE_LEVEL_LOW,   0 },
 188         { AU1550_MAC0_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 189         { AU1550_MAC1_DMA_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 190         { -1, },
 191 };
 192
 193 struct au1xxx_irqmap au1200_irqmap[] __initdata = {
 194         { AU1200_UART0_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 195         { AU1200_SWT_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 196         { AU1200_SD_INT,          IRQ_TYPE_LEVEL_HIGH,  0 },
 197         { AU1200_DDMA_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 198         { AU1200_MAE_BE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 199         { AU1200_UART1_INT,       IRQ_TYPE_LEVEL_HIGH,  0 },
 200         { AU1200_MAE_FE_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 201         { AU1200_PSC0_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 202         { AU1200_PSC1_INT,        IRQ_TYPE_LEVEL_HIGH,  0 },
 203         { AU1200_AES_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 204         { AU1200_CAMERA_INT,      IRQ_TYPE_LEVEL_HIGH,  0 },
 205         { AU1200_TOY_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 206         { AU1200_TOY_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 207         { AU1200_TOY_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 208         { AU1200_TOY_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 209         { AU1200_RTC_INT,         IRQ_TYPE_EDGE_RISING, 0 },
 210         { AU1200_RTC_MATCH0_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 211         { AU1200_RTC_MATCH1_INT,  IRQ_TYPE_EDGE_RISING, 0 },
 212         { AU1200_RTC_MATCH2_INT,  IRQ_TYPE_EDGE_RISING, 1 },
 213         { AU1200_NAND_INT,        IRQ_TYPE_EDGE_RISING, 0 },
 214         { AU1200_USB_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 215         { AU1200_LCD_INT,         IRQ_TYPE_LEVEL_HIGH,  0 },
 216         { AU1200_MAE_BOTH_INT,    IRQ_TYPE_LEVEL_HIGH,  0 },
 217         { -1, },
 218 };
 219
 220
 221 static void au1x_ic0_unmask(unsigned int irq_nr)
 222 {
 223         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 224         au_writel(1 << bit, IC0_MASKSET);
 225         au_writel(1 << bit, IC0_WAKESET);
 226         au_sync();
 227 }
 228
 229 static void au1x_ic1_unmask(unsigned int irq_nr)
 230 {
 231         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 232         au_writel(1 << bit, IC1_MASKSET);
 233         au_writel(1 << bit, IC1_WAKESET);
 234
 235 /* very hacky. does the pb1000 cpld auto-disable this int?
 236  * nowhere in the current kernel sources is it disabled.        --mlau
 237  */
 238 #if defined(CONFIG_MIPS_PB1000)
 239         if (irq_nr == AU1000_GPIO15_INT)
 240                 au_writel(0x4000, PB1000_MDR); /* enable int */
 241 #endif
 242         au_sync();
 243 }
 244
 245 static void au1x_ic0_mask(unsigned int irq_nr)
 246 {
 247         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 248         au_writel(1 << bit, IC0_MASKCLR);
 249         au_writel(1 << bit, IC0_WAKECLR);
 250         au_sync();
 251 }
 252
 253 static void au1x_ic1_mask(unsigned int irq_nr)
 254 {
 255         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 256         au_writel(1 << bit, IC1_MASKCLR);
 257         au_writel(1 << bit, IC1_WAKECLR);
 258         au_sync();
 259 }
 260
 261 static void au1x_ic0_ack(unsigned int irq_nr)
 262 {
 263         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 264
 265         /*
 266          * This may assume that we don't get interrupts from
 267          * both edges at once, or if we do, that we don't care.
 268          */
 269         au_writel(1 << bit, IC0_FALLINGCLR);
 270         au_writel(1 << bit, IC0_RISINGCLR);
 271         au_sync();
 272 }
 273
 274 static void au1x_ic1_ack(unsigned int irq_nr)
 275 {
 276         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 277
 278         /*
 279          * This may assume that we don't get interrupts from
 280          * both edges at once, or if we do, that we don't care.
 281          */
 282         au_writel(1 << bit, IC1_FALLINGCLR);
 283         au_writel(1 << bit, IC1_RISINGCLR);
 284         au_sync();
 285 }
 286
 287 static void au1x_ic0_maskack(unsigned int irq_nr)
 288 {
 289         unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
 290
 291         au_writel(1 << bit, IC0_WAKECLR);
 292         au_writel(1 << bit, IC0_MASKCLR);
 293         au_writel(1 << bit, IC0_RISINGCLR);
 294         au_writel(1 << bit, IC0_FALLINGCLR);
 295         au_sync();
 296 }
 297
 298 static void au1x_ic1_maskack(unsigned int irq_nr)
 299 {
 300         unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE;
 301
 302         au_writel(1 << bit, IC1_WAKECLR);
 303         au_writel(1 << bit, IC1_MASKCLR);
 304         au_writel(1 << bit, IC1_RISINGCLR);
 305         au_writel(1 << bit, IC1_FALLINGCLR);
 306         au_sync();
 307 }
 308
 309 static int au1x_ic1_setwake(unsigned int irq, unsigned int on)
 310 {
 311         int bit = irq - AU1000_INTC1_INT_BASE;
 312         unsigned long wakemsk, flags;
 313
 314         /* only GPIO 0-7 can act as wakeup source.  Fortunately these
 315          * are wired up identically on all supported variants.
 316          */
 317         if ((bit < 0) || (bit > 7))
 318                 return -EINVAL;
 319
 320         local_irq_save(flags);
 321         wakemsk = au_readl(SYS_WAKEMSK);
 322         if (on)
 323                 wakemsk |= 1 << bit;
 324         else
 325                 wakemsk &= ~(1 << bit);
 326         au_writel(wakemsk, SYS_WAKEMSK);
 327         au_sync();
 328         local_irq_restore(flags);
 329
 330         return 0;
 331 }
 332
 333 /*
 334  * irq_chips for both ICs; this way the mask handlers can be
 335  * as short as possible.
 336  */
 337 static struct irq_chip au1x_ic0_chip = {
 338         .name           = "Alchemy-IC0",
 339         .ack            = au1x_ic0_ack,
 340         .mask           = au1x_ic0_mask,
 341         .mask_ack       = au1x_ic0_maskack,
 342         .unmask         = au1x_ic0_unmask,
 343         .set_type       = au1x_ic_settype,
 344 };
 345
 346 static struct irq_chip au1x_ic1_chip = {
 347         .name           = "Alchemy-IC1",
 348         .ack            = au1x_ic1_ack,
 349         .mask           = au1x_ic1_mask,
 350         .mask_ack       = au1x_ic1_maskack,
 351         .unmask         = au1x_ic1_unmask,
 352         .set_type       = au1x_ic_settype,
 353         .set_wake       = au1x_ic1_setwake,
 354 };
 355
 356 static int au1x_ic_settype(unsigned int irq, unsigned int flow_type)
 357 {
 358         struct irq_chip *chip;
 359         unsigned long icr[6];
 360         unsigned int bit, ic;
 361         int ret;
 362
 363         if (irq >= AU1000_INTC1_INT_BASE) {
 364                 bit = irq - AU1000_INTC1_INT_BASE;
 365                 chip = &au1x_ic1_chip;
 366                 ic = 1;
 367         } else {
 368                 bit = irq - AU1000_INTC0_INT_BASE;
 369                 chip = &au1x_ic0_chip;
 370                 ic = 0;
 371         }
 372
 373         if (bit > 31)
 374                 return -EINVAL;
 375
 376         icr[0] = ic ? IC1_CFG0SET : IC0_CFG0SET;
 377         icr[1] = ic ? IC1_CFG1SET : IC0_CFG1SET;
 378         icr[2] = ic ? IC1_CFG2SET : IC0_CFG2SET;
 379         icr[3] = ic ? IC1_CFG0CLR : IC0_CFG0CLR;
 380         icr[4] = ic ? IC1_CFG1CLR : IC0_CFG1CLR;
 381         icr[5] = ic ? IC1_CFG2CLR : IC0_CFG2CLR;
 382
 383         ret = 0;
 384
 385         switch (flow_type) {    /* cfgregs 2:1:0 */
 386         case IRQ_TYPE_EDGE_RISING:      /* 0:0:1 */
 387                 au_writel(1 << bit, icr[5]);
 388                 au_writel(1 << bit, icr[4]);
 389                 au_writel(1 << bit, icr[0]);
 390                 set_irq_chip_and_handler_name(irq, chip,
 391                                 handle_edge_irq, "riseedge");
 392                 break;
 393         case IRQ_TYPE_EDGE_FALLING:     /* 0:1:0 */
 394                 au_writel(1 << bit, icr[5]);
 395                 au_writel(1 << bit, icr[1]);
 396                 au_writel(1 << bit, icr[3]);
 397                 set_irq_chip_and_handler_name(irq, chip,
 398                                 handle_edge_irq, "falledge");
 399                 break;
 400         case IRQ_TYPE_EDGE_BOTH:        /* 0:1:1 */
 401                 au_writel(1 << bit, icr[5]);
 402                 au_writel(1 << bit, icr[1]);
 403                 au_writel(1 << bit, icr[0]);
 404                 set_irq_chip_and_handler_name(irq, chip,
 405                                 handle_edge_irq, "bothedge");
 406                 break;
 407         case IRQ_TYPE_LEVEL_HIGH:       /* 1:0:1 */
 408                 au_writel(1 << bit, icr[2]);
 409                 au_writel(1 << bit, icr[4]);
 410                 au_writel(1 << bit, icr[0]);
 411                 set_irq_chip_and_handler_name(irq, chip,
 412                                 handle_level_irq, "hilevel");
 413                 break;
 414         case IRQ_TYPE_LEVEL_LOW:        /* 1:1:0 */
 415                 au_writel(1 << bit, icr[2]);
 416                 au_writel(1 << bit, icr[1]);
 417                 au_writel(1 << bit, icr[3]);
 418                 set_irq_chip_and_handler_name(irq, chip,
 419                                 handle_level_irq, "lowlevel");
 420                 break;
 421         case IRQ_TYPE_NONE:             /* 0:0:0 */
 422                 au_writel(1 << bit, icr[5]);
 423                 au_writel(1 << bit, icr[4]);
 424                 au_writel(1 << bit, icr[3]);
 425                 /* set at least chip so we can call set_irq_type() on it */
 426                 set_irq_chip(irq, chip);
 427                 break;
 428         default:
 429                 ret = -EINVAL;
 430         }
 431         au_sync();
 432
 433         return ret;
 434 }
 435
 436 asmlinkage void plat_irq_dispatch(void)
 437 {
 438         unsigned int pending = read_c0_status() & read_c0_cause();
 439         unsigned long s, off;
 440
 441         if (pending & CAUSEF_IP7) {
 442                 off = MIPS_CPU_IRQ_BASE + 7;
 443                 goto handle;
 444         } else if (pending & CAUSEF_IP2) {
 445                 s = IC0_REQ0INT;
 446                 off = AU1000_INTC0_INT_BASE;
 447         } else if (pending & CAUSEF_IP3) {
 448                 s = IC0_REQ1INT;
 449                 off = AU1000_INTC0_INT_BASE;
 450         } else if (pending & CAUSEF_IP4) {
 451                 s = IC1_REQ0INT;
 452                 off = AU1000_INTC1_INT_BASE;
 453         } else if (pending & CAUSEF_IP5) {
 454                 s = IC1_REQ1INT;
 455                 off = AU1000_INTC1_INT_BASE;
 456         } else
 457                 goto spurious;
 458
 459         s = au_readl(s);
 460         if (unlikely(!s)) {
 461 spurious:
 462                 spurious_interrupt();
 463                 return;
 464         }
 465         off += __ffs(s);
 466 handle:
 467         do_IRQ(off);
 468 }
 469
 470 static void __init au1000_init_irq(struct au1xxx_irqmap *map)
 471 {
 472         unsigned int bit, irq_nr;
 473         int i;
 474
 475         /*
 476          * Initialize interrupt controllers to a safe state.
 477          */
 478         au_writel(0xffffffff, IC0_CFG0CLR);
 479         au_writel(0xffffffff, IC0_CFG1CLR);
 480         au_writel(0xffffffff, IC0_CFG2CLR);
 481         au_writel(0xffffffff, IC0_MASKCLR);
 482         au_writel(0xffffffff, IC0_ASSIGNCLR);
 483         au_writel(0xffffffff, IC0_WAKECLR);
 484         au_writel(0xffffffff, IC0_SRCSET);
 485         au_writel(0xffffffff, IC0_FALLINGCLR);
 486         au_writel(0xffffffff, IC0_RISINGCLR);
 487         au_writel(0x00000000, IC0_TESTBIT);
 488
 489         au_writel(0xffffffff, IC1_CFG0CLR);
 490         au_writel(0xffffffff, IC1_CFG1CLR);
 491         au_writel(0xffffffff, IC1_CFG2CLR);
 492         au_writel(0xffffffff, IC1_MASKCLR);
 493         au_writel(0xffffffff, IC1_ASSIGNCLR);
 494         au_writel(0xffffffff, IC1_WAKECLR);
 495         au_writel(0xffffffff, IC1_SRCSET);
 496         au_writel(0xffffffff, IC1_FALLINGCLR);
 497         au_writel(0xffffffff, IC1_RISINGCLR);
 498         au_writel(0x00000000, IC1_TESTBIT);
 499
 500         mips_cpu_irq_init();
 501
 502         /* register all 64 possible IC0+IC1 irq sources as type "none".
 503          * Use set_irq_type() to set edge/level behaviour at runtime.
 504          */
 505         for (i = AU1000_INTC0_INT_BASE;
 506              (i < AU1000_INTC0_INT_BASE + 32); i++)
 507                 au1x_ic_settype(i, IRQ_TYPE_NONE);
 508
 509         for (i = AU1000_INTC1_INT_BASE;
 510              (i < AU1000_INTC1_INT_BASE + 32); i++)
 511                 au1x_ic_settype(i, IRQ_TYPE_NONE);
 512
 513         /*
 514          * Initialize IC0, which is fixed per processor.
 515          */
 516         while (map->im_irq != -1) {
 517                 irq_nr = map->im_irq;
 518
 519                 if (irq_nr >= AU1000_INTC1_INT_BASE) {
 520                         bit = irq_nr - AU1000_INTC1_INT_BASE;
 521                         if (map->im_request)
 522                                 au_writel(1 << bit, IC1_ASSIGNSET);
 523                 } else {
 524                         bit = irq_nr - AU1000_INTC0_INT_BASE;
 525                         if (map->im_request)
 526                                 au_writel(1 << bit, IC0_ASSIGNSET);
 527                 }
 528
 529                 au1x_ic_settype(irq_nr, map->im_type);
 530                 ++map;
 531         }
 532
 533         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3);
 534 }
 535
 536 void __init arch_init_irq(void)
 537 {
 538         switch (alchemy_get_cputype()) {
 539         case ALCHEMY_CPU_AU1000:
 540                 au1000_init_irq(au1000_irqmap);
 541                 break;
 542         case ALCHEMY_CPU_AU1500:
 543                 au1000_init_irq(au1500_irqmap);
 544                 break;
 545         case ALCHEMY_CPU_AU1100:
 546                 au1000_init_irq(au1100_irqmap);
 547                 break;
 548         case ALCHEMY_CPU_AU1550:
 549                 au1000_init_irq(au1550_irqmap);
 550                 break;
 551         case ALCHEMY_CPU_AU1200:
 552                 au1000_init_irq(au1200_irqmap);
 553                 break;
 554         }
 555 }
 556
 557 struct alchemy_ic_sysdev {
 558         struct sys_device sysdev;
 559         void __iomem *base;
 560         unsigned long pmdata[7];
 561 };
 562
 563 static int alchemy_ic_suspend(struct sys_device *dev, pm_message_t state)
 564 {
 565         struct alchemy_ic_sysdev *icdev =
 566                         container_of(dev, struct alchemy_ic_sysdev, sysdev);
 567
 568         icdev->pmdata[0] = __raw_readl(icdev->base + IC_CFG0RD);
 569         icdev->pmdata[1] = __raw_readl(icdev->base + IC_CFG1RD);
 570         icdev->pmdata[2] = __raw_readl(icdev->base + IC_CFG2RD);
 571         icdev->pmdata[3] = __raw_readl(icdev->base + IC_SRCRD);
 572         icdev->pmdata[4] = __raw_readl(icdev->base + IC_ASSIGNRD);
 573         icdev->pmdata[5] = __raw_readl(icdev->base + IC_WAKERD);
 574         icdev->pmdata[6] = __raw_readl(icdev->base + IC_MASKRD);
 575
 576         return 0;
 577 }
 578
 579 static int alchemy_ic_resume(struct sys_device *dev)
 580 {
 581         struct alchemy_ic_sysdev *icdev =
 582                         container_of(dev, struct alchemy_ic_sysdev, sysdev);
 583
 584         __raw_writel(0xffffffff, icdev->base + IC_MASKCLR);
 585         __raw_writel(0xffffffff, icdev->base + IC_CFG0CLR);
 586         __raw_writel(0xffffffff, icdev->base + IC_CFG1CLR);
 587         __raw_writel(0xffffffff, icdev->base + IC_CFG2CLR);
 588         __raw_writel(0xffffffff, icdev->base + IC_SRCCLR);
 589         __raw_writel(0xffffffff, icdev->base + IC_ASSIGNCLR);
 590         __raw_writel(0xffffffff, icdev->base + IC_WAKECLR);
 591         __raw_writel(0xffffffff, icdev->base + IC_RISINGCLR);
 592         __raw_writel(0xffffffff, icdev->base + IC_FALLINGCLR);
 593         __raw_writel(0x00000000, icdev->base + IC_TESTBIT);
 594         wmb();
 595         __raw_writel(icdev->pmdata[0], icdev->base + IC_CFG0SET);
 596         __raw_writel(icdev->pmdata[1], icdev->base + IC_CFG1SET);
 597         __raw_writel(icdev->pmdata[2], icdev->base + IC_CFG2SET);
 598         __raw_writel(icdev->pmdata[3], icdev->base + IC_SRCSET);
 599         __raw_writel(icdev->pmdata[4], icdev->base + IC_ASSIGNSET);
 600         __raw_writel(icdev->pmdata[5], icdev->base + IC_WAKESET);
 601         wmb();
 602
 603         __raw_writel(icdev->pmdata[6], icdev->base + IC_MASKSET);
 604         wmb();
 605
 606         return 0;
 607 }
 608
 609 static struct sysdev_class alchemy_ic_sysdev_class = {
 610         .name           = "ic",
 611         .suspend        = alchemy_ic_suspend,
 612         .resume         = alchemy_ic_resume,
 613 };
 614
 615 static int __init alchemy_ic_sysdev_init(void)
 616 {
 617         struct alchemy_ic_sysdev *icdev;
 618         unsigned long icbase[2] = { IC0_PHYS_ADDR, IC1_PHYS_ADDR };
 619         int err, i;
 620
 621         err = sysdev_class_register(&alchemy_ic_sysdev_class);
 622         if (err)
 623                 return err;
 624
 625         for (i = 0; i < 2; i++) {
 626                 icdev = kzalloc(sizeof(struct alchemy_ic_sysdev), GFP_KERNEL);
 627                 if (!icdev)
 628                         return -ENOMEM;
 629
 630                 icdev->base = ioremap(icbase[i], 0x1000);
 631
 632                 icdev->sysdev.id = i;
 633                 icdev->sysdev.cls = &alchemy_ic_sysdev_class;
 634                 err = sysdev_register(&icdev->sysdev);
 635                 if (err) {
 636                         kfree(icdev);
 637                         return err;
 638                 }
 639         }
 640
 641         return 0;
 642 }
 643 device_initcall(alchemy_ic_sysdev_init);