arch/m32r/kernel/setup_oaks32r.c

   1 /*
   2  *  linux/arch/m32r/kernel/setup_oaks32r.c
   3  *
   4  *  Setup routines for OAKS32R Board
   5  *
   6  *  Copyright (c) 2002-2005  Hiroyuki Kondo, Hirokazu Takata,
   7  *                           Hitoshi Yamamoto, Mamoru Sakugawa
   8  */
   9
  10 #include <linux/config.h>
  11 #include <linux/irq.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14
  15 #include <asm/system.h>
  16 #include <asm/m32r.h>
  17 #include <asm/io.h>
  18
  19 #define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
  20
  21 icu_data_t icu_data[NR_IRQS];
  22
  23 static void disable_oaks32r_irq(unsigned int irq)
  24 {
  25         unsigned long port, data;
  26
  27         port = irq2port(irq);
  28         data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
  29         outl(data, port);
  30 }
  31
  32 static void enable_oaks32r_irq(unsigned int irq)
  33 {
  34         unsigned long port, data;
  35
  36         port = irq2port(irq);
  37         data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
  38         outl(data, port);
  39 }
  40
  41 static void mask_and_ack_mappi(unsigned int irq)
  42 {
  43         disable_oaks32r_irq(irq);
  44 }
  45
  46 static void end_oaks32r_irq(unsigned int irq)
  47 {
  48         enable_oaks32r_irq(irq);
  49 }
  50
  51 static unsigned int startup_oaks32r_irq(unsigned int irq)
  52 {
  53         enable_oaks32r_irq(irq);
  54         return (0);
  55 }
  56
  57 static void shutdown_oaks32r_irq(unsigned int irq)
  58 {
  59         unsigned long port;
  60
  61         port = irq2port(irq);
  62         outl(M32R_ICUCR_ILEVEL7, port);
  63 }
  64
  65 static struct hw_interrupt_type oaks32r_irq_type =
  66 {
  67         .typename = "OAKS32R-IRQ",
  68         .startup = startup_oaks32r_irq,
  69         .shutdown = shutdown_oaks32r_irq,
  70         .enable = enable_oaks32r_irq,
  71         .disable = disable_oaks32r_irq,
  72         .ack = mask_and_ack_mappi,
  73         .end = end_oaks32r_irq
  74 };
  75
  76 void __init init_IRQ(void)
  77 {
  78         static int once = 0;
  79
  80         if (once)
  81                 return;
  82         else
  83                 once++;
  84
  85 #ifdef CONFIG_NE2000
  86         /* INT3 : LAN controller (RTL8019AS) */
  87         irq_desc[M32R_IRQ_INT3].status = IRQ_DISABLED;
  88         irq_desc[M32R_IRQ_INT3].chip = &oaks32r_irq_type;
  89         irq_desc[M32R_IRQ_INT3].action = 0;
  90         irq_desc[M32R_IRQ_INT3].depth = 1;
  91         icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
  92         disable_oaks32r_irq(M32R_IRQ_INT3);
  93 #endif /* CONFIG_M32R_NE2000 */
  94
  95         /* MFT2 : system timer */
  96         irq_desc[M32R_IRQ_MFT2].status = IRQ_DISABLED;
  97         irq_desc[M32R_IRQ_MFT2].chip = &oaks32r_irq_type;
  98         irq_desc[M32R_IRQ_MFT2].action = 0;
  99         irq_desc[M32R_IRQ_MFT2].depth = 1;
 100         icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
 101         disable_oaks32r_irq(M32R_IRQ_MFT2);
 102
 103 #ifdef CONFIG_SERIAL_M32R_SIO
 104         /* SIO0_R : uart receive data */
 105         irq_desc[M32R_IRQ_SIO0_R].status = IRQ_DISABLED;
 106         irq_desc[M32R_IRQ_SIO0_R].chip = &oaks32r_irq_type;
 107         irq_desc[M32R_IRQ_SIO0_R].action = 0;
 108         irq_desc[M32R_IRQ_SIO0_R].depth = 1;
 109         icu_data[M32R_IRQ_SIO0_R].icucr = 0;
 110         disable_oaks32r_irq(M32R_IRQ_SIO0_R);
 111
 112         /* SIO0_S : uart send data */
 113         irq_desc[M32R_IRQ_SIO0_S].status = IRQ_DISABLED;
 114         irq_desc[M32R_IRQ_SIO0_S].chip = &oaks32r_irq_type;
 115         irq_desc[M32R_IRQ_SIO0_S].action = 0;
 116         irq_desc[M32R_IRQ_SIO0_S].depth = 1;
 117         icu_data[M32R_IRQ_SIO0_S].icucr = 0;
 118         disable_oaks32r_irq(M32R_IRQ_SIO0_S);
 119
 120         /* SIO1_R : uart receive data */
 121         irq_desc[M32R_IRQ_SIO1_R].status = IRQ_DISABLED;
 122         irq_desc[M32R_IRQ_SIO1_R].chip = &oaks32r_irq_type;
 123         irq_desc[M32R_IRQ_SIO1_R].action = 0;
 124         irq_desc[M32R_IRQ_SIO1_R].depth = 1;
 125         icu_data[M32R_IRQ_SIO1_R].icucr = 0;
 126         disable_oaks32r_irq(M32R_IRQ_SIO1_R);
 127
 128         /* SIO1_S : uart send data */
 129         irq_desc[M32R_IRQ_SIO1_S].status = IRQ_DISABLED;
 130         irq_desc[M32R_IRQ_SIO1_S].chip = &oaks32r_irq_type;
 131         irq_desc[M32R_IRQ_SIO1_S].action = 0;
 132         irq_desc[M32R_IRQ_SIO1_S].depth = 1;
 133         icu_data[M32R_IRQ_SIO1_S].icucr = 0;
 134         disable_oaks32r_irq(M32R_IRQ_SIO1_S);
 135 #endif /* CONFIG_SERIAL_M32R_SIO */
 136 }