2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2000,2002-2005 Silicon Graphics, Inc. All rights reserved.
8 * Routines for PCI DMA mapping. See Documentation/DMA-API.txt for
9 * a description of how these routines should be used.
12 #include <linux/gfp.h>
13 #include <linux/module.h>
14 #include <linux/dma-mapping.h>
16 #include <asm/sn/intr.h>
17 #include <asm/sn/pcibus_provider_defs.h>
18 #include <asm/sn/pcidev.h>
19 #include <asm/sn/sn_sal.h>
21 #define SG_ENT_VIRT_ADDRESS(sg) (sg_virt((sg)))
22 #define SG_ENT_PHYS_ADDRESS(SG) virt_to_phys(SG_ENT_VIRT_ADDRESS(SG))
25 * sn_dma_supported - test a DMA mask
26 * @dev: device to test
27 * @mask: DMA mask to test
29 * Return whether the given PCI device DMA address mask can be supported
30 * properly. For example, if your device can only drive the low 24-bits
31 * during PCI bus mastering, then you would pass 0x00ffffff as the mask to
32 * this function. Of course, SN only supports devices that have 32 or more
33 * address bits when using the PMU.
35 static int sn_dma_supported(struct device *dev, u64 mask)
37 BUG_ON(!dev_is_pci(dev));
39 if (mask < 0x7fffffff)
45 * sn_dma_set_mask - set the DMA mask
49 * Set @dev's DMA mask if the hw supports it.
51 int sn_dma_set_mask(struct device *dev, u64 dma_mask)
53 BUG_ON(!dev_is_pci(dev));
55 if (!sn_dma_supported(dev, dma_mask))
58 *dev->dma_mask = dma_mask;
61 EXPORT_SYMBOL(sn_dma_set_mask);
64 * sn_dma_alloc_coherent - allocate memory for coherent DMA
65 * @dev: device to allocate for
66 * @size: size of the region
67 * @dma_handle: DMA (bus) address
68 * @flags: memory allocation flags
70 * dma_alloc_coherent() returns a pointer to a memory region suitable for
71 * coherent DMA traffic to/from a PCI device. On SN platforms, this means
72 * that @dma_handle will have the %PCIIO_DMA_CMD flag set.
74 * This interface is usually used for "command" streams (e.g. the command
75 * queue for a SCSI controller). See Documentation/DMA-API.txt for
78 static void *sn_dma_alloc_coherent(struct device *dev, size_t size,
79 dma_addr_t * dma_handle, gfp_t flags,
83 unsigned long phys_addr;
85 struct pci_dev *pdev = to_pci_dev(dev);
86 struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
88 BUG_ON(!dev_is_pci(dev));
91 * Allocate the memory.
93 node = pcibus_to_node(pdev->bus);
94 if (likely(node >=0)) {
95 struct page *p = __alloc_pages_node(node,
96 flags, get_order(size));
99 cpuaddr = page_address(p);
103 cpuaddr = (void *)__get_free_pages(flags, get_order(size));
105 if (unlikely(!cpuaddr))
108 memset(cpuaddr, 0x0, size);
110 /* physical addr. of the memory we just got */
111 phys_addr = __pa(cpuaddr);
114 * 64 bit address translations should never fail.
115 * 32 bit translations can fail if there are insufficient mapping
119 *dma_handle = provider->dma_map_consistent(pdev, phys_addr, size,
122 printk(KERN_ERR "%s: out of ATEs\n", __func__);
123 free_pages((unsigned long)cpuaddr, get_order(size));
131 * sn_pci_free_coherent - free memory associated with coherent DMAable region
132 * @dev: device to free for
133 * @size: size to free
134 * @cpu_addr: kernel virtual address to free
135 * @dma_handle: DMA address associated with this region
137 * Frees the memory allocated by dma_alloc_coherent(), potentially unmapping
138 * any associated IOMMU mappings.
140 static void sn_dma_free_coherent(struct device *dev, size_t size, void *cpu_addr,
141 dma_addr_t dma_handle, unsigned long attrs)
143 struct pci_dev *pdev = to_pci_dev(dev);
144 struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
146 BUG_ON(!dev_is_pci(dev));
148 provider->dma_unmap(pdev, dma_handle, 0);
149 free_pages((unsigned long)cpu_addr, get_order(size));
153 * sn_dma_map_single_attrs - map a single page for DMA
154 * @dev: device to map for
155 * @cpu_addr: kernel virtual address of the region to map
156 * @size: size of the region
157 * @direction: DMA direction
158 * @attrs: optional dma attributes
160 * Map the region pointed to by @cpu_addr for DMA and return the
163 * We map this to the one step pcibr_dmamap_trans interface rather than
164 * the two step pcibr_dmamap_alloc/pcibr_dmamap_addr because we have
165 * no way of saving the dmamap handle from the alloc to later free
166 * (which is pretty much unacceptable).
168 * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
169 * dma_map_consistent() so that writes force a flush of pending DMA.
170 * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
171 * Document Number: 007-4763-001)
173 * TODO: simplify our interface;
174 * figure out how to save dmamap handle so can use two step.
176 static dma_addr_t sn_dma_map_page(struct device *dev, struct page *page,
177 unsigned long offset, size_t size,
178 enum dma_data_direction dir,
181 void *cpu_addr = page_address(page) + offset;
183 unsigned long phys_addr;
184 struct pci_dev *pdev = to_pci_dev(dev);
185 struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
187 BUG_ON(!dev_is_pci(dev));
189 phys_addr = __pa(cpu_addr);
190 if (attrs & DMA_ATTR_WRITE_BARRIER)
191 dma_addr = provider->dma_map_consistent(pdev, phys_addr,
192 size, SN_DMA_ADDR_PHYS);
194 dma_addr = provider->dma_map(pdev, phys_addr, size,
198 printk(KERN_ERR "%s: out of ATEs\n", __func__);
199 return DMA_MAPPING_ERROR;
205 * sn_dma_unmap_single_attrs - unamp a DMA mapped page
206 * @dev: device to sync
207 * @dma_addr: DMA address to sync
208 * @size: size of region
209 * @direction: DMA direction
210 * @attrs: optional dma attributes
212 * This routine is supposed to sync the DMA region specified
213 * by @dma_handle into the coherence domain. On SN, we're always cache
214 * coherent, so we just need to free any ATEs associated with this mapping.
216 static void sn_dma_unmap_page(struct device *dev, dma_addr_t dma_addr,
217 size_t size, enum dma_data_direction dir,
220 struct pci_dev *pdev = to_pci_dev(dev);
221 struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
223 BUG_ON(!dev_is_pci(dev));
225 provider->dma_unmap(pdev, dma_addr, dir);
229 * sn_dma_unmap_sg - unmap a DMA scatterlist
230 * @dev: device to unmap
231 * @sg: scatterlist to unmap
232 * @nhwentries: number of scatterlist entries
233 * @direction: DMA direction
234 * @attrs: optional dma attributes
236 * Unmap a set of streaming mode DMA translations.
238 static void sn_dma_unmap_sg(struct device *dev, struct scatterlist *sgl,
239 int nhwentries, enum dma_data_direction dir,
243 struct pci_dev *pdev = to_pci_dev(dev);
244 struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
245 struct scatterlist *sg;
247 BUG_ON(!dev_is_pci(dev));
249 for_each_sg(sgl, sg, nhwentries, i) {
250 provider->dma_unmap(pdev, sg->dma_address, dir);
251 sg->dma_address = (dma_addr_t) NULL;
257 * sn_dma_map_sg - map a scatterlist for DMA
258 * @dev: device to map for
259 * @sg: scatterlist to map
260 * @nhwentries: number of entries
261 * @direction: direction of the DMA transaction
262 * @attrs: optional dma attributes
264 * mappings with the DMA_ATTR_WRITE_BARRIER get mapped with
265 * dma_map_consistent() so that writes force a flush of pending DMA.
266 * (See "SGI Altix Architecture Considerations for Linux Device Drivers",
267 * Document Number: 007-4763-001)
269 * Maps each entry of @sg for DMA.
271 static int sn_dma_map_sg(struct device *dev, struct scatterlist *sgl,
272 int nhwentries, enum dma_data_direction dir,
275 unsigned long phys_addr;
276 struct scatterlist *saved_sg = sgl, *sg;
277 struct pci_dev *pdev = to_pci_dev(dev);
278 struct sn_pcibus_provider *provider = SN_PCIDEV_BUSPROVIDER(pdev);
281 BUG_ON(!dev_is_pci(dev));
284 * Setup a DMA address for each entry in the scatterlist.
286 for_each_sg(sgl, sg, nhwentries, i) {
288 phys_addr = SG_ENT_PHYS_ADDRESS(sg);
289 if (attrs & DMA_ATTR_WRITE_BARRIER)
290 dma_addr = provider->dma_map_consistent(pdev,
295 dma_addr = provider->dma_map(pdev, phys_addr,
299 sg->dma_address = dma_addr;
300 if (!sg->dma_address) {
301 printk(KERN_ERR "%s: out of ATEs\n", __func__);
304 * Free any successfully allocated entries.
307 sn_dma_unmap_sg(dev, saved_sg, i, dir, attrs);
311 sg->dma_length = sg->length;
317 static u64 sn_dma_get_required_mask(struct device *dev)
319 return DMA_BIT_MASK(64);
322 char *sn_pci_get_legacy_mem(struct pci_bus *bus)
324 if (!SN_PCIBUS_BUSSOFT(bus))
325 return ERR_PTR(-ENODEV);
327 return (char *)(SN_PCIBUS_BUSSOFT(bus)->bs_legacy_mem | __IA64_UNCACHED_OFFSET);
330 int sn_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
334 struct ia64_sal_retval isrv;
337 * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
338 * around hw issues at the pci bus level. SGI proms older than
339 * 4.10 don't implement this.
342 SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
343 pci_domain_nr(bus), bus->number,
346 port, size, __pa(val));
348 if (isrv.status == 0)
352 * If the above failed, retry using the SAL_PROBE call which should
353 * be present in all proms (but which cannot work round PCI chipset
354 * bugs). This code is retained for compatibility with old
355 * pre-4.10 proms, and should be removed at some point in the future.
358 if (!SN_PCIBUS_BUSSOFT(bus))
361 addr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
364 ret = ia64_sn_probe_mem(addr, (long)size, (void *)val);
375 int sn_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
380 struct ia64_sal_retval isrv;
383 * First, try the SN_SAL_IOIF_PCI_SAFE SAL call which can work
384 * around hw issues at the pci bus level. SGI proms older than
385 * 4.10 don't implement this.
388 SAL_CALL(isrv, SN_SAL_IOIF_PCI_SAFE,
389 pci_domain_nr(bus), bus->number,
392 port, size, __pa(&val));
394 if (isrv.status == 0)
398 * If the above failed, retry using the SAL_PROBE call which should
399 * be present in all proms (but which cannot work round PCI chipset
400 * bugs). This code is retained for compatibility with old
401 * pre-4.10 proms, and should be removed at some point in the future.
404 if (!SN_PCIBUS_BUSSOFT(bus)) {
409 /* Put the phys addr in uncached space */
410 paddr = SN_PCIBUS_BUSSOFT(bus)->bs_legacy_io | __IA64_UNCACHED_OFFSET;
412 addr = (unsigned long *)paddr;
416 *(volatile u8 *)(addr) = (u8)(val);
419 *(volatile u16 *)(addr) = (u16)(val);
422 *(volatile u32 *)(addr) = (u32)(val);
432 static struct dma_map_ops sn_dma_ops = {
433 .alloc = sn_dma_alloc_coherent,
434 .free = sn_dma_free_coherent,
435 .map_page = sn_dma_map_page,
436 .unmap_page = sn_dma_unmap_page,
437 .map_sg = sn_dma_map_sg,
438 .unmap_sg = sn_dma_unmap_sg,
439 .dma_supported = sn_dma_supported,
440 .get_required_mask = sn_dma_get_required_mask,
443 void sn_dma_init(void)
445 dma_ops = &sn_dma_ops;