b57e723f194c782aa6bc639717dcd57d5db0a947
[sfrench/cifs-2.6.git] / arch / ia64 / kernel / mca.c
1 /*
2  * File:        mca.c
3  * Purpose:     Generic MCA handling layer
4  *
5  * Updated for latest kernel
6  * Copyright (C) 2003 Hewlett-Packard Co
7  *      David Mosberger-Tang <davidm@hpl.hp.com>
8  *
9  * Copyright (C) 2002 Dell Inc.
10  * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
11  *
12  * Copyright (C) 2002 Intel
13  * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
14  *
15  * Copyright (C) 2001 Intel
16  * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
17  *
18  * Copyright (C) 2000 Intel
19  * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
20  *
21  * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22  * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
23  *
24  * 03/04/15 D. Mosberger Added INIT backtrace support.
25  * 02/03/25 M. Domsch   GUID cleanups
26  *
27  * 02/01/04 J. Hall     Aligned MCA stack to 16 bytes, added platform vs. CPU
28  *                      error flag, set SAL default return values, changed
29  *                      error record structure to linked list, added init call
30  *                      to sal_get_state_info_size().
31  *
32  * 01/01/03 F. Lewis    Added setup of CMCI and CPEI IRQs, logging of corrected
33  *                      platform errors, completed code for logging of
34  *                      corrected & uncorrected machine check errors, and
35  *                      updated for conformance with Nov. 2000 revision of the
36  *                      SAL 3.0 spec.
37  * 00/03/29 C. Fleckenstein  Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38  *                           added min save state dump, added INIT handler.
39  *
40  * 2003-12-08 Keith Owens <kaos@sgi.com>
41  *            smp_call_function() must not be called from interrupt context (can
42  *            deadlock on tasklist_lock).  Use keventd to call smp_call_function().
43  *
44  * 2004-02-01 Keith Owens <kaos@sgi.com>
45  *            Avoid deadlock when using printk() for MCA and INIT records.
46  *            Delete all record printing code, moved to salinfo_decode in user space.
47  *            Mark variables and functions static where possible.
48  *            Delete dead variables and functions.
49  *            Reorder to remove the need for forward declarations and to consolidate
50  *            related code.
51  *
52  * 2005-08-12 Keith Owens <kaos@sgi.com>
53  *            Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
54  *
55  * 2005-10-07 Keith Owens <kaos@sgi.com>
56  *            Add notify_die() hooks.
57  */
58 #include <linux/config.h>
59 #include <linux/types.h>
60 #include <linux/init.h>
61 #include <linux/sched.h>
62 #include <linux/interrupt.h>
63 #include <linux/irq.h>
64 #include <linux/smp_lock.h>
65 #include <linux/bootmem.h>
66 #include <linux/acpi.h>
67 #include <linux/timer.h>
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/smp.h>
71 #include <linux/workqueue.h>
72
73 #include <asm/delay.h>
74 #include <asm/kdebug.h>
75 #include <asm/machvec.h>
76 #include <asm/meminit.h>
77 #include <asm/page.h>
78 #include <asm/ptrace.h>
79 #include <asm/system.h>
80 #include <asm/sal.h>
81 #include <asm/mca.h>
82
83 #include <asm/irq.h>
84 #include <asm/hw_irq.h>
85
86 #include "entry.h"
87
88 #if defined(IA64_MCA_DEBUG_INFO)
89 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
90 #else
91 # define IA64_MCA_DEBUG(fmt...)
92 #endif
93
94 /* Used by mca_asm.S */
95 u32                             ia64_mca_serialize;
96 DEFINE_PER_CPU(u64, ia64_mca_data); /* == __per_cpu_mca[smp_processor_id()] */
97 DEFINE_PER_CPU(u64, ia64_mca_per_cpu_pte); /* PTE to map per-CPU area */
98 DEFINE_PER_CPU(u64, ia64_mca_pal_pte);      /* PTE to map PAL code */
99 DEFINE_PER_CPU(u64, ia64_mca_pal_base);    /* vaddr PAL code granule */
100
101 unsigned long __per_cpu_mca[NR_CPUS];
102
103 /* In mca_asm.S */
104 extern void                     ia64_os_init_dispatch_monarch (void);
105 extern void                     ia64_os_init_dispatch_slave (void);
106
107 static int monarch_cpu = -1;
108
109 static ia64_mc_info_t           ia64_mc_info;
110
111 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
112 #define MIN_CPE_POLL_INTERVAL (2*60*HZ)  /* 2 minutes */
113 #define CMC_POLL_INTERVAL     (1*60*HZ)  /* 1 minute */
114 #define CPE_HISTORY_LENGTH    5
115 #define CMC_HISTORY_LENGTH    5
116
117 static struct timer_list cpe_poll_timer;
118 static struct timer_list cmc_poll_timer;
119 /*
120  * This variable tells whether we are currently in polling mode.
121  * Start with this in the wrong state so we won't play w/ timers
122  * before the system is ready.
123  */
124 static int cmc_polling_enabled = 1;
125
126 /*
127  * Clearing this variable prevents CPE polling from getting activated
128  * in mca_late_init.  Use it if your system doesn't provide a CPEI,
129  * but encounters problems retrieving CPE logs.  This should only be
130  * necessary for debugging.
131  */
132 static int cpe_poll_enabled = 1;
133
134 extern void salinfo_log_wakeup(int type, u8 *buffer, u64 size, int irqsafe);
135
136 static int mca_init;
137
138
139 static void inline
140 ia64_mca_spin(const char *func)
141 {
142         printk(KERN_EMERG "%s: spinning here, not returning to SAL\n", func);
143         while (1)
144                 cpu_relax();
145 }
146 /*
147  * IA64_MCA log support
148  */
149 #define IA64_MAX_LOGS           2       /* Double-buffering for nested MCAs */
150 #define IA64_MAX_LOG_TYPES      4   /* MCA, INIT, CMC, CPE */
151
152 typedef struct ia64_state_log_s
153 {
154         spinlock_t      isl_lock;
155         int             isl_index;
156         unsigned long   isl_count;
157         ia64_err_rec_t  *isl_log[IA64_MAX_LOGS]; /* need space to store header + error log */
158 } ia64_state_log_t;
159
160 static ia64_state_log_t ia64_state_log[IA64_MAX_LOG_TYPES];
161
162 #define IA64_LOG_ALLOCATE(it, size) \
163         {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
164                 (ia64_err_rec_t *)alloc_bootmem(size); \
165         ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
166                 (ia64_err_rec_t *)alloc_bootmem(size);}
167 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
168 #define IA64_LOG_LOCK(it)      spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
169 #define IA64_LOG_UNLOCK(it)    spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
170 #define IA64_LOG_NEXT_INDEX(it)    ia64_state_log[it].isl_index
171 #define IA64_LOG_CURR_INDEX(it)    1 - ia64_state_log[it].isl_index
172 #define IA64_LOG_INDEX_INC(it) \
173     {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
174     ia64_state_log[it].isl_count++;}
175 #define IA64_LOG_INDEX_DEC(it) \
176     ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
177 #define IA64_LOG_NEXT_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
178 #define IA64_LOG_CURR_BUFFER(it)   (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
179 #define IA64_LOG_COUNT(it)         ia64_state_log[it].isl_count
180
181 /*
182  * ia64_log_init
183  *      Reset the OS ia64 log buffer
184  * Inputs   :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
185  * Outputs      :       None
186  */
187 static void
188 ia64_log_init(int sal_info_type)
189 {
190         u64     max_size = 0;
191
192         IA64_LOG_NEXT_INDEX(sal_info_type) = 0;
193         IA64_LOG_LOCK_INIT(sal_info_type);
194
195         // SAL will tell us the maximum size of any error record of this type
196         max_size = ia64_sal_get_state_info_size(sal_info_type);
197         if (!max_size)
198                 /* alloc_bootmem() doesn't like zero-sized allocations! */
199                 return;
200
201         // set up OS data structures to hold error info
202         IA64_LOG_ALLOCATE(sal_info_type, max_size);
203         memset(IA64_LOG_CURR_BUFFER(sal_info_type), 0, max_size);
204         memset(IA64_LOG_NEXT_BUFFER(sal_info_type), 0, max_size);
205 }
206
207 /*
208  * ia64_log_get
209  *
210  *      Get the current MCA log from SAL and copy it into the OS log buffer.
211  *
212  *  Inputs  :   info_type   (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
213  *              irq_safe    whether you can use printk at this point
214  *  Outputs :   size        (total record length)
215  *              *buffer     (ptr to error record)
216  *
217  */
218 static u64
219 ia64_log_get(int sal_info_type, u8 **buffer, int irq_safe)
220 {
221         sal_log_record_header_t     *log_buffer;
222         u64                         total_len = 0;
223         int                         s;
224
225         IA64_LOG_LOCK(sal_info_type);
226
227         /* Get the process state information */
228         log_buffer = IA64_LOG_NEXT_BUFFER(sal_info_type);
229
230         total_len = ia64_sal_get_state_info(sal_info_type, (u64 *)log_buffer);
231
232         if (total_len) {
233                 IA64_LOG_INDEX_INC(sal_info_type);
234                 IA64_LOG_UNLOCK(sal_info_type);
235                 if (irq_safe) {
236                         IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
237                                        "Record length = %ld\n", __FUNCTION__, sal_info_type, total_len);
238                 }
239                 *buffer = (u8 *) log_buffer;
240                 return total_len;
241         } else {
242                 IA64_LOG_UNLOCK(sal_info_type);
243                 return 0;
244         }
245 }
246
247 /*
248  *  ia64_mca_log_sal_error_record
249  *
250  *  This function retrieves a specified error record type from SAL
251  *  and wakes up any processes waiting for error records.
252  *
253  *  Inputs  :   sal_info_type   (Type of error record MCA/CMC/CPE)
254  *              FIXME: remove MCA and irq_safe.
255  */
256 static void
257 ia64_mca_log_sal_error_record(int sal_info_type)
258 {
259         u8 *buffer;
260         sal_log_record_header_t *rh;
261         u64 size;
262         int irq_safe = sal_info_type != SAL_INFO_TYPE_MCA;
263 #ifdef IA64_MCA_DEBUG_INFO
264         static const char * const rec_name[] = { "MCA", "INIT", "CMC", "CPE" };
265 #endif
266
267         size = ia64_log_get(sal_info_type, &buffer, irq_safe);
268         if (!size)
269                 return;
270
271         salinfo_log_wakeup(sal_info_type, buffer, size, irq_safe);
272
273         if (irq_safe)
274                 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
275                         smp_processor_id(),
276                         sal_info_type < ARRAY_SIZE(rec_name) ? rec_name[sal_info_type] : "UNKNOWN");
277
278         /* Clear logs from corrected errors in case there's no user-level logger */
279         rh = (sal_log_record_header_t *)buffer;
280         if (rh->severity == sal_log_severity_corrected)
281                 ia64_sal_clear_state_info(sal_info_type);
282 }
283
284 #ifdef CONFIG_ACPI
285
286 int cpe_vector = -1;
287 int ia64_cpe_irq = -1;
288
289 static irqreturn_t
290 ia64_mca_cpe_int_handler (int cpe_irq, void *arg, struct pt_regs *ptregs)
291 {
292         static unsigned long    cpe_history[CPE_HISTORY_LENGTH];
293         static int              index;
294         static DEFINE_SPINLOCK(cpe_history_lock);
295
296         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
297                        __FUNCTION__, cpe_irq, smp_processor_id());
298
299         /* SAL spec states this should run w/ interrupts enabled */
300         local_irq_enable();
301
302         /* Get the CPE error record and log it */
303         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE);
304
305         spin_lock(&cpe_history_lock);
306         if (!cpe_poll_enabled && cpe_vector >= 0) {
307
308                 int i, count = 1; /* we know 1 happened now */
309                 unsigned long now = jiffies;
310
311                 for (i = 0; i < CPE_HISTORY_LENGTH; i++) {
312                         if (now - cpe_history[i] <= HZ)
313                                 count++;
314                 }
315
316                 IA64_MCA_DEBUG(KERN_INFO "CPE threshold %d/%d\n", count, CPE_HISTORY_LENGTH);
317                 if (count >= CPE_HISTORY_LENGTH) {
318
319                         cpe_poll_enabled = 1;
320                         spin_unlock(&cpe_history_lock);
321                         disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR));
322
323                         /*
324                          * Corrected errors will still be corrected, but
325                          * make sure there's a log somewhere that indicates
326                          * something is generating more than we can handle.
327                          */
328                         printk(KERN_WARNING "WARNING: Switching to polling CPE handler; error records may be lost\n");
329
330                         mod_timer(&cpe_poll_timer, jiffies + MIN_CPE_POLL_INTERVAL);
331
332                         /* lock already released, get out now */
333                         return IRQ_HANDLED;
334                 } else {
335                         cpe_history[index++] = now;
336                         if (index == CPE_HISTORY_LENGTH)
337                                 index = 0;
338                 }
339         }
340         spin_unlock(&cpe_history_lock);
341         return IRQ_HANDLED;
342 }
343
344 #endif /* CONFIG_ACPI */
345
346 #ifdef CONFIG_ACPI
347 /*
348  * ia64_mca_register_cpev
349  *
350  *  Register the corrected platform error vector with SAL.
351  *
352  *  Inputs
353  *      cpev        Corrected Platform Error Vector number
354  *
355  *  Outputs
356  *      None
357  */
358 static void
359 ia64_mca_register_cpev (int cpev)
360 {
361         /* Register the CPE interrupt vector with SAL */
362         struct ia64_sal_retval isrv;
363
364         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT, SAL_MC_PARAM_MECHANISM_INT, cpev, 0, 0);
365         if (isrv.status) {
366                 printk(KERN_ERR "Failed to register Corrected Platform "
367                        "Error interrupt vector with SAL (status %ld)\n", isrv.status);
368                 return;
369         }
370
371         IA64_MCA_DEBUG("%s: corrected platform error "
372                        "vector %#x registered\n", __FUNCTION__, cpev);
373 }
374 #endif /* CONFIG_ACPI */
375
376 /*
377  * ia64_mca_cmc_vector_setup
378  *
379  *  Setup the corrected machine check vector register in the processor.
380  *  (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
381  *  This function is invoked on a per-processor basis.
382  *
383  * Inputs
384  *      None
385  *
386  * Outputs
387  *      None
388  */
389 void
390 ia64_mca_cmc_vector_setup (void)
391 {
392         cmcv_reg_t      cmcv;
393
394         cmcv.cmcv_regval        = 0;
395         cmcv.cmcv_mask          = 1;        /* Mask/disable interrupt at first */
396         cmcv.cmcv_vector        = IA64_CMC_VECTOR;
397         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
398
399         IA64_MCA_DEBUG("%s: CPU %d corrected "
400                        "machine check vector %#x registered.\n",
401                        __FUNCTION__, smp_processor_id(), IA64_CMC_VECTOR);
402
403         IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
404                        __FUNCTION__, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV));
405 }
406
407 /*
408  * ia64_mca_cmc_vector_disable
409  *
410  *  Mask the corrected machine check vector register in the processor.
411  *  This function is invoked on a per-processor basis.
412  *
413  * Inputs
414  *      dummy(unused)
415  *
416  * Outputs
417  *      None
418  */
419 static void
420 ia64_mca_cmc_vector_disable (void *dummy)
421 {
422         cmcv_reg_t      cmcv;
423
424         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
425
426         cmcv.cmcv_mask = 1; /* Mask/disable interrupt */
427         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
428
429         IA64_MCA_DEBUG("%s: CPU %d corrected "
430                        "machine check vector %#x disabled.\n",
431                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
432 }
433
434 /*
435  * ia64_mca_cmc_vector_enable
436  *
437  *  Unmask the corrected machine check vector register in the processor.
438  *  This function is invoked on a per-processor basis.
439  *
440  * Inputs
441  *      dummy(unused)
442  *
443  * Outputs
444  *      None
445  */
446 static void
447 ia64_mca_cmc_vector_enable (void *dummy)
448 {
449         cmcv_reg_t      cmcv;
450
451         cmcv.cmcv_regval = ia64_getreg(_IA64_REG_CR_CMCV);
452
453         cmcv.cmcv_mask = 0; /* Unmask/enable interrupt */
454         ia64_setreg(_IA64_REG_CR_CMCV, cmcv.cmcv_regval);
455
456         IA64_MCA_DEBUG("%s: CPU %d corrected "
457                        "machine check vector %#x enabled.\n",
458                        __FUNCTION__, smp_processor_id(), cmcv.cmcv_vector);
459 }
460
461 /*
462  * ia64_mca_cmc_vector_disable_keventd
463  *
464  * Called via keventd (smp_call_function() is not safe in interrupt context) to
465  * disable the cmc interrupt vector.
466  */
467 static void
468 ia64_mca_cmc_vector_disable_keventd(void *unused)
469 {
470         on_each_cpu(ia64_mca_cmc_vector_disable, NULL, 1, 0);
471 }
472
473 /*
474  * ia64_mca_cmc_vector_enable_keventd
475  *
476  * Called via keventd (smp_call_function() is not safe in interrupt context) to
477  * enable the cmc interrupt vector.
478  */
479 static void
480 ia64_mca_cmc_vector_enable_keventd(void *unused)
481 {
482         on_each_cpu(ia64_mca_cmc_vector_enable, NULL, 1, 0);
483 }
484
485 /*
486  * ia64_mca_wakeup
487  *
488  *      Send an inter-cpu interrupt to wake-up a particular cpu
489  *      and mark that cpu to be out of rendez.
490  *
491  *  Inputs  :   cpuid
492  *  Outputs :   None
493  */
494 static void
495 ia64_mca_wakeup(int cpu)
496 {
497         platform_send_ipi(cpu, IA64_MCA_WAKEUP_VECTOR, IA64_IPI_DM_INT, 0);
498         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
499
500 }
501
502 /*
503  * ia64_mca_wakeup_all
504  *
505  *      Wakeup all the cpus which have rendez'ed previously.
506  *
507  *  Inputs  :   None
508  *  Outputs :   None
509  */
510 static void
511 ia64_mca_wakeup_all(void)
512 {
513         int cpu;
514
515         /* Clear the Rendez checkin flag for all cpus */
516         for_each_online_cpu(cpu) {
517                 if (ia64_mc_info.imi_rendez_checkin[cpu] == IA64_MCA_RENDEZ_CHECKIN_DONE)
518                         ia64_mca_wakeup(cpu);
519         }
520
521 }
522
523 /*
524  * ia64_mca_rendez_interrupt_handler
525  *
526  *      This is handler used to put slave processors into spinloop
527  *      while the monarch processor does the mca handling and later
528  *      wake each slave up once the monarch is done.
529  *
530  *  Inputs  :   None
531  *  Outputs :   None
532  */
533 static irqreturn_t
534 ia64_mca_rendez_int_handler(int rendez_irq, void *arg, struct pt_regs *regs)
535 {
536         unsigned long flags;
537         int cpu = smp_processor_id();
538
539         /* Mask all interrupts */
540         local_irq_save(flags);
541         if (notify_die(DIE_MCA_RENDZVOUS_ENTER, "MCA", regs, 0, 0, 0)
542                         == NOTIFY_STOP)
543                 ia64_mca_spin(__FUNCTION__);
544
545         ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_DONE;
546         /* Register with the SAL monarch that the slave has
547          * reached SAL
548          */
549         ia64_sal_mc_rendez();
550
551         if (notify_die(DIE_MCA_RENDZVOUS_PROCESS, "MCA", regs, 0, 0, 0)
552                         == NOTIFY_STOP)
553                 ia64_mca_spin(__FUNCTION__);
554
555         /* Wait for the monarch cpu to exit. */
556         while (monarch_cpu != -1)
557                cpu_relax();     /* spin until monarch leaves */
558
559         if (notify_die(DIE_MCA_RENDZVOUS_LEAVE, "MCA", regs, 0, 0, 0)
560                         == NOTIFY_STOP)
561                 ia64_mca_spin(__FUNCTION__);
562
563         /* Enable all interrupts */
564         local_irq_restore(flags);
565         return IRQ_HANDLED;
566 }
567
568 /*
569  * ia64_mca_wakeup_int_handler
570  *
571  *      The interrupt handler for processing the inter-cpu interrupt to the
572  *      slave cpu which was spinning in the rendez loop.
573  *      Since this spinning is done by turning off the interrupts and
574  *      polling on the wakeup-interrupt bit in the IRR, there is
575  *      nothing useful to be done in the handler.
576  *
577  *  Inputs  :   wakeup_irq  (Wakeup-interrupt bit)
578  *      arg             (Interrupt handler specific argument)
579  *      ptregs          (Exception frame at the time of the interrupt)
580  *  Outputs :   None
581  *
582  */
583 static irqreturn_t
584 ia64_mca_wakeup_int_handler(int wakeup_irq, void *arg, struct pt_regs *ptregs)
585 {
586         return IRQ_HANDLED;
587 }
588
589 /* Function pointer for extra MCA recovery */
590 int (*ia64_mca_ucmc_extension)
591         (void*,struct ia64_sal_os_state*)
592         = NULL;
593
594 int
595 ia64_reg_MCA_extension(int (*fn)(void *, struct ia64_sal_os_state *))
596 {
597         if (ia64_mca_ucmc_extension)
598                 return 1;
599
600         ia64_mca_ucmc_extension = fn;
601         return 0;
602 }
603
604 void
605 ia64_unreg_MCA_extension(void)
606 {
607         if (ia64_mca_ucmc_extension)
608                 ia64_mca_ucmc_extension = NULL;
609 }
610
611 EXPORT_SYMBOL(ia64_reg_MCA_extension);
612 EXPORT_SYMBOL(ia64_unreg_MCA_extension);
613
614
615 static inline void
616 copy_reg(const u64 *fr, u64 fnat, u64 *tr, u64 *tnat)
617 {
618         u64 fslot, tslot, nat;
619         *tr = *fr;
620         fslot = ((unsigned long)fr >> 3) & 63;
621         tslot = ((unsigned long)tr >> 3) & 63;
622         *tnat &= ~(1UL << tslot);
623         nat = (fnat >> fslot) & 1;
624         *tnat |= (nat << tslot);
625 }
626
627 /* Change the comm field on the MCA/INT task to include the pid that
628  * was interrupted, it makes for easier debugging.  If that pid was 0
629  * (swapper or nested MCA/INIT) then use the start of the previous comm
630  * field suffixed with its cpu.
631  */
632
633 static void
634 ia64_mca_modify_comm(const task_t *previous_current)
635 {
636         char *p, comm[sizeof(current->comm)];
637         if (previous_current->pid)
638                 snprintf(comm, sizeof(comm), "%s %d",
639                         current->comm, previous_current->pid);
640         else {
641                 int l;
642                 if ((p = strchr(previous_current->comm, ' ')))
643                         l = p - previous_current->comm;
644                 else
645                         l = strlen(previous_current->comm);
646                 snprintf(comm, sizeof(comm), "%s %*s %d",
647                         current->comm, l, previous_current->comm,
648                         task_thread_info(previous_current)->cpu);
649         }
650         memcpy(current->comm, comm, sizeof(current->comm));
651 }
652
653 /* On entry to this routine, we are running on the per cpu stack, see
654  * mca_asm.h.  The original stack has not been touched by this event.  Some of
655  * the original stack's registers will be in the RBS on this stack.  This stack
656  * also contains a partial pt_regs and switch_stack, the rest of the data is in
657  * PAL minstate.
658  *
659  * The first thing to do is modify the original stack to look like a blocked
660  * task so we can run backtrace on the original task.  Also mark the per cpu
661  * stack as current to ensure that we use the correct task state, it also means
662  * that we can do backtrace on the MCA/INIT handler code itself.
663  */
664
665 static task_t *
666 ia64_mca_modify_original_stack(struct pt_regs *regs,
667                 const struct switch_stack *sw,
668                 struct ia64_sal_os_state *sos,
669                 const char *type)
670 {
671         char *p;
672         ia64_va va;
673         extern char ia64_leave_kernel[];        /* Need asm address, not function descriptor */
674         const pal_min_state_area_t *ms = sos->pal_min_state;
675         task_t *previous_current;
676         struct pt_regs *old_regs;
677         struct switch_stack *old_sw;
678         unsigned size = sizeof(struct pt_regs) +
679                         sizeof(struct switch_stack) + 16;
680         u64 *old_bspstore, *old_bsp;
681         u64 *new_bspstore, *new_bsp;
682         u64 old_unat, old_rnat, new_rnat, nat;
683         u64 slots, loadrs = regs->loadrs;
684         u64 r12 = ms->pmsa_gr[12-1], r13 = ms->pmsa_gr[13-1];
685         u64 ar_bspstore = regs->ar_bspstore;
686         u64 ar_bsp = regs->ar_bspstore + (loadrs >> 16);
687         const u64 *bank;
688         const char *msg;
689         int cpu = smp_processor_id();
690
691         previous_current = curr_task(cpu);
692         set_curr_task(cpu, current);
693         if ((p = strchr(current->comm, ' ')))
694                 *p = '\0';
695
696         /* Best effort attempt to cope with MCA/INIT delivered while in
697          * physical mode.
698          */
699         regs->cr_ipsr = ms->pmsa_ipsr;
700         if (ia64_psr(regs)->dt == 0) {
701                 va.l = r12;
702                 if (va.f.reg == 0) {
703                         va.f.reg = 7;
704                         r12 = va.l;
705                 }
706                 va.l = r13;
707                 if (va.f.reg == 0) {
708                         va.f.reg = 7;
709                         r13 = va.l;
710                 }
711         }
712         if (ia64_psr(regs)->rt == 0) {
713                 va.l = ar_bspstore;
714                 if (va.f.reg == 0) {
715                         va.f.reg = 7;
716                         ar_bspstore = va.l;
717                 }
718                 va.l = ar_bsp;
719                 if (va.f.reg == 0) {
720                         va.f.reg = 7;
721                         ar_bsp = va.l;
722                 }
723         }
724
725         /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
726          * have been copied to the old stack, the old stack may fail the
727          * validation tests below.  So ia64_old_stack() must restore the dirty
728          * registers from the new stack.  The old and new bspstore probably
729          * have different alignments, so loadrs calculated on the old bsp
730          * cannot be used to restore from the new bsp.  Calculate a suitable
731          * loadrs for the new stack and save it in the new pt_regs, where
732          * ia64_old_stack() can get it.
733          */
734         old_bspstore = (u64 *)ar_bspstore;
735         old_bsp = (u64 *)ar_bsp;
736         slots = ia64_rse_num_regs(old_bspstore, old_bsp);
737         new_bspstore = (u64 *)((u64)current + IA64_RBS_OFFSET);
738         new_bsp = ia64_rse_skip_regs(new_bspstore, slots);
739         regs->loadrs = (new_bsp - new_bspstore) * 8 << 16;
740
741         /* Verify the previous stack state before we change it */
742         if (user_mode(regs)) {
743                 msg = "occurred in user space";
744                 /* previous_current is guaranteed to be valid when the task was
745                  * in user space, so ...
746                  */
747                 ia64_mca_modify_comm(previous_current);
748                 goto no_mod;
749         }
750         if (r13 != sos->prev_IA64_KR_CURRENT) {
751                 msg = "inconsistent previous current and r13";
752                 goto no_mod;
753         }
754         if ((r12 - r13) >= KERNEL_STACK_SIZE) {
755                 msg = "inconsistent r12 and r13";
756                 goto no_mod;
757         }
758         if ((ar_bspstore - r13) >= KERNEL_STACK_SIZE) {
759                 msg = "inconsistent ar.bspstore and r13";
760                 goto no_mod;
761         }
762         va.p = old_bspstore;
763         if (va.f.reg < 5) {
764                 msg = "old_bspstore is in the wrong region";
765                 goto no_mod;
766         }
767         if ((ar_bsp - r13) >= KERNEL_STACK_SIZE) {
768                 msg = "inconsistent ar.bsp and r13";
769                 goto no_mod;
770         }
771         size += (ia64_rse_skip_regs(old_bspstore, slots) - old_bspstore) * 8;
772         if (ar_bspstore + size > r12) {
773                 msg = "no room for blocked state";
774                 goto no_mod;
775         }
776
777         ia64_mca_modify_comm(previous_current);
778
779         /* Make the original task look blocked.  First stack a struct pt_regs,
780          * describing the state at the time of interrupt.  mca_asm.S built a
781          * partial pt_regs, copy it and fill in the blanks using minstate.
782          */
783         p = (char *)r12 - sizeof(*regs);
784         old_regs = (struct pt_regs *)p;
785         memcpy(old_regs, regs, sizeof(*regs));
786         /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
787          * pmsa_{xip,xpsr,xfs}
788          */
789         if (ia64_psr(regs)->ic) {
790                 old_regs->cr_iip = ms->pmsa_iip;
791                 old_regs->cr_ipsr = ms->pmsa_ipsr;
792                 old_regs->cr_ifs = ms->pmsa_ifs;
793         } else {
794                 old_regs->cr_iip = ms->pmsa_xip;
795                 old_regs->cr_ipsr = ms->pmsa_xpsr;
796                 old_regs->cr_ifs = ms->pmsa_xfs;
797         }
798         old_regs->pr = ms->pmsa_pr;
799         old_regs->b0 = ms->pmsa_br0;
800         old_regs->loadrs = loadrs;
801         old_regs->ar_rsc = ms->pmsa_rsc;
802         old_unat = old_regs->ar_unat;
803         copy_reg(&ms->pmsa_gr[1-1], ms->pmsa_nat_bits, &old_regs->r1, &old_unat);
804         copy_reg(&ms->pmsa_gr[2-1], ms->pmsa_nat_bits, &old_regs->r2, &old_unat);
805         copy_reg(&ms->pmsa_gr[3-1], ms->pmsa_nat_bits, &old_regs->r3, &old_unat);
806         copy_reg(&ms->pmsa_gr[8-1], ms->pmsa_nat_bits, &old_regs->r8, &old_unat);
807         copy_reg(&ms->pmsa_gr[9-1], ms->pmsa_nat_bits, &old_regs->r9, &old_unat);
808         copy_reg(&ms->pmsa_gr[10-1], ms->pmsa_nat_bits, &old_regs->r10, &old_unat);
809         copy_reg(&ms->pmsa_gr[11-1], ms->pmsa_nat_bits, &old_regs->r11, &old_unat);
810         copy_reg(&ms->pmsa_gr[12-1], ms->pmsa_nat_bits, &old_regs->r12, &old_unat);
811         copy_reg(&ms->pmsa_gr[13-1], ms->pmsa_nat_bits, &old_regs->r13, &old_unat);
812         copy_reg(&ms->pmsa_gr[14-1], ms->pmsa_nat_bits, &old_regs->r14, &old_unat);
813         copy_reg(&ms->pmsa_gr[15-1], ms->pmsa_nat_bits, &old_regs->r15, &old_unat);
814         if (ia64_psr(old_regs)->bn)
815                 bank = ms->pmsa_bank1_gr;
816         else
817                 bank = ms->pmsa_bank0_gr;
818         copy_reg(&bank[16-16], ms->pmsa_nat_bits, &old_regs->r16, &old_unat);
819         copy_reg(&bank[17-16], ms->pmsa_nat_bits, &old_regs->r17, &old_unat);
820         copy_reg(&bank[18-16], ms->pmsa_nat_bits, &old_regs->r18, &old_unat);
821         copy_reg(&bank[19-16], ms->pmsa_nat_bits, &old_regs->r19, &old_unat);
822         copy_reg(&bank[20-16], ms->pmsa_nat_bits, &old_regs->r20, &old_unat);
823         copy_reg(&bank[21-16], ms->pmsa_nat_bits, &old_regs->r21, &old_unat);
824         copy_reg(&bank[22-16], ms->pmsa_nat_bits, &old_regs->r22, &old_unat);
825         copy_reg(&bank[23-16], ms->pmsa_nat_bits, &old_regs->r23, &old_unat);
826         copy_reg(&bank[24-16], ms->pmsa_nat_bits, &old_regs->r24, &old_unat);
827         copy_reg(&bank[25-16], ms->pmsa_nat_bits, &old_regs->r25, &old_unat);
828         copy_reg(&bank[26-16], ms->pmsa_nat_bits, &old_regs->r26, &old_unat);
829         copy_reg(&bank[27-16], ms->pmsa_nat_bits, &old_regs->r27, &old_unat);
830         copy_reg(&bank[28-16], ms->pmsa_nat_bits, &old_regs->r28, &old_unat);
831         copy_reg(&bank[29-16], ms->pmsa_nat_bits, &old_regs->r29, &old_unat);
832         copy_reg(&bank[30-16], ms->pmsa_nat_bits, &old_regs->r30, &old_unat);
833         copy_reg(&bank[31-16], ms->pmsa_nat_bits, &old_regs->r31, &old_unat);
834
835         /* Next stack a struct switch_stack.  mca_asm.S built a partial
836          * switch_stack, copy it and fill in the blanks using pt_regs and
837          * minstate.
838          *
839          * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
840          * ar.pfs is set to 0.
841          *
842          * unwind.c::unw_unwind() does special processing for interrupt frames.
843          * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
844          * is clear then unw_unwind() does _not_ adjust bsp over pt_regs.  Not
845          * that this is documented, of course.  Set PRED_NON_SYSCALL in the
846          * switch_stack on the original stack so it will unwind correctly when
847          * unwind.c reads pt_regs.
848          *
849          * thread.ksp is updated to point to the synthesized switch_stack.
850          */
851         p -= sizeof(struct switch_stack);
852         old_sw = (struct switch_stack *)p;
853         memcpy(old_sw, sw, sizeof(*sw));
854         old_sw->caller_unat = old_unat;
855         old_sw->ar_fpsr = old_regs->ar_fpsr;
856         copy_reg(&ms->pmsa_gr[4-1], ms->pmsa_nat_bits, &old_sw->r4, &old_unat);
857         copy_reg(&ms->pmsa_gr[5-1], ms->pmsa_nat_bits, &old_sw->r5, &old_unat);
858         copy_reg(&ms->pmsa_gr[6-1], ms->pmsa_nat_bits, &old_sw->r6, &old_unat);
859         copy_reg(&ms->pmsa_gr[7-1], ms->pmsa_nat_bits, &old_sw->r7, &old_unat);
860         old_sw->b0 = (u64)ia64_leave_kernel;
861         old_sw->b1 = ms->pmsa_br1;
862         old_sw->ar_pfs = 0;
863         old_sw->ar_unat = old_unat;
864         old_sw->pr = old_regs->pr | (1UL << PRED_NON_SYSCALL);
865         previous_current->thread.ksp = (u64)p - 16;
866
867         /* Finally copy the original stack's registers back to its RBS.
868          * Registers from ar.bspstore through ar.bsp at the time of the event
869          * are in the current RBS, copy them back to the original stack.  The
870          * copy must be done register by register because the original bspstore
871          * and the current one have different alignments, so the saved RNAT
872          * data occurs at different places.
873          *
874          * mca_asm does cover, so the old_bsp already includes all registers at
875          * the time of MCA/INIT.  It also does flushrs, so all registers before
876          * this function have been written to backing store on the MCA/INIT
877          * stack.
878          */
879         new_rnat = ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore));
880         old_rnat = regs->ar_rnat;
881         while (slots--) {
882                 if (ia64_rse_is_rnat_slot(new_bspstore)) {
883                         new_rnat = ia64_get_rnat(new_bspstore++);
884                 }
885                 if (ia64_rse_is_rnat_slot(old_bspstore)) {
886                         *old_bspstore++ = old_rnat;
887                         old_rnat = 0;
888                 }
889                 nat = (new_rnat >> ia64_rse_slot_num(new_bspstore)) & 1UL;
890                 old_rnat &= ~(1UL << ia64_rse_slot_num(old_bspstore));
891                 old_rnat |= (nat << ia64_rse_slot_num(old_bspstore));
892                 *old_bspstore++ = *new_bspstore++;
893         }
894         old_sw->ar_bspstore = (unsigned long)old_bspstore;
895         old_sw->ar_rnat = old_rnat;
896
897         sos->prev_task = previous_current;
898         return previous_current;
899
900 no_mod:
901         printk(KERN_INFO "cpu %d, %s %s, original stack not modified\n",
902                         smp_processor_id(), type, msg);
903         return previous_current;
904 }
905
906 /* The monarch/slave interaction is based on monarch_cpu and requires that all
907  * slaves have entered rendezvous before the monarch leaves.  If any cpu has
908  * not entered rendezvous yet then wait a bit.  The assumption is that any
909  * slave that has not rendezvoused after a reasonable time is never going to do
910  * so.  In this context, slave includes cpus that respond to the MCA rendezvous
911  * interrupt, as well as cpus that receive the INIT slave event.
912  */
913
914 static void
915 ia64_wait_for_slaves(int monarch)
916 {
917         int c, wait = 0, missing = 0;
918         for_each_online_cpu(c) {
919                 if (c == monarch)
920                         continue;
921                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
922                         udelay(1000);           /* short wait first */
923                         wait = 1;
924                         break;
925                 }
926         }
927         if (!wait)
928                 goto all_in;
929         for_each_online_cpu(c) {
930                 if (c == monarch)
931                         continue;
932                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE) {
933                         udelay(5*1000000);      /* wait 5 seconds for slaves (arbitrary) */
934                         if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
935                                 missing = 1;
936                         break;
937                 }
938         }
939         if (!missing)
940                 goto all_in;
941         printk(KERN_INFO "OS MCA slave did not rendezvous on cpu");
942         for_each_online_cpu(c) {
943                 if (c == monarch)
944                         continue;
945                 if (ia64_mc_info.imi_rendez_checkin[c] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE)
946                         printk(" %d", c);
947         }
948         printk("\n");
949         return;
950
951 all_in:
952         printk(KERN_INFO "All OS MCA slaves have reached rendezvous\n");
953         return;
954 }
955
956 /*
957  * ia64_mca_handler
958  *
959  *      This is uncorrectable machine check handler called from OS_MCA
960  *      dispatch code which is in turn called from SAL_CHECK().
961  *      This is the place where the core of OS MCA handling is done.
962  *      Right now the logs are extracted and displayed in a well-defined
963  *      format. This handler code is supposed to be run only on the
964  *      monarch processor. Once the monarch is done with MCA handling
965  *      further MCA logging is enabled by clearing logs.
966  *      Monarch also has the duty of sending wakeup-IPIs to pull the
967  *      slave processors out of rendezvous spinloop.
968  */
969 void
970 ia64_mca_handler(struct pt_regs *regs, struct switch_stack *sw,
971                  struct ia64_sal_os_state *sos)
972 {
973         pal_processor_state_info_t *psp = (pal_processor_state_info_t *)
974                 &sos->proc_state_param;
975         int recover, cpu = smp_processor_id();
976         task_t *previous_current;
977
978         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
979         console_loglevel = 15;  /* make sure printks make it to console */
980         printk(KERN_INFO "Entered OS MCA handler. PSP=%lx cpu=%d monarch=%ld\n",
981                 sos->proc_state_param, cpu, sos->monarch);
982
983         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "MCA");
984         monarch_cpu = cpu;
985         if (notify_die(DIE_MCA_MONARCH_ENTER, "MCA", regs, 0, 0, 0)
986                         == NOTIFY_STOP)
987                 ia64_mca_spin(__FUNCTION__);
988         ia64_wait_for_slaves(cpu);
989
990         /* Wakeup all the processors which are spinning in the rendezvous loop.
991          * They will leave SAL, then spin in the OS with interrupts disabled
992          * until this monarch cpu leaves the MCA handler.  That gets control
993          * back to the OS so we can backtrace the other cpus, backtrace when
994          * spinning in SAL does not work.
995          */
996         ia64_mca_wakeup_all();
997         if (notify_die(DIE_MCA_MONARCH_PROCESS, "MCA", regs, 0, 0, 0)
998                         == NOTIFY_STOP)
999                 ia64_mca_spin(__FUNCTION__);
1000
1001         /* Get the MCA error record and log it */
1002         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA);
1003
1004         /* TLB error is only exist in this SAL error record */
1005         recover = (psp->tc && !(psp->cc || psp->bc || psp->rc || psp->uc))
1006         /* other error recovery */
1007            || (ia64_mca_ucmc_extension
1008                 && ia64_mca_ucmc_extension(
1009                         IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA),
1010                         sos));
1011
1012         if (recover) {
1013                 sal_log_record_header_t *rh = IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA);
1014                 rh->severity = sal_log_severity_corrected;
1015                 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA);
1016                 sos->os_status = IA64_MCA_CORRECTED;
1017         }
1018         if (notify_die(DIE_MCA_MONARCH_LEAVE, "MCA", regs, 0, 0, recover)
1019                         == NOTIFY_STOP)
1020                 ia64_mca_spin(__FUNCTION__);
1021
1022         set_curr_task(cpu, previous_current);
1023         monarch_cpu = -1;
1024 }
1025
1026 static DECLARE_WORK(cmc_disable_work, ia64_mca_cmc_vector_disable_keventd, NULL);
1027 static DECLARE_WORK(cmc_enable_work, ia64_mca_cmc_vector_enable_keventd, NULL);
1028
1029 /*
1030  * ia64_mca_cmc_int_handler
1031  *
1032  *  This is corrected machine check interrupt handler.
1033  *      Right now the logs are extracted and displayed in a well-defined
1034  *      format.
1035  *
1036  * Inputs
1037  *      interrupt number
1038  *      client data arg ptr
1039  *      saved registers ptr
1040  *
1041  * Outputs
1042  *      None
1043  */
1044 static irqreturn_t
1045 ia64_mca_cmc_int_handler(int cmc_irq, void *arg, struct pt_regs *ptregs)
1046 {
1047         static unsigned long    cmc_history[CMC_HISTORY_LENGTH];
1048         static int              index;
1049         static DEFINE_SPINLOCK(cmc_history_lock);
1050
1051         IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1052                        __FUNCTION__, cmc_irq, smp_processor_id());
1053
1054         /* SAL spec states this should run w/ interrupts enabled */
1055         local_irq_enable();
1056
1057         /* Get the CMC error record and log it */
1058         ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC);
1059
1060         spin_lock(&cmc_history_lock);
1061         if (!cmc_polling_enabled) {
1062                 int i, count = 1; /* we know 1 happened now */
1063                 unsigned long now = jiffies;
1064
1065                 for (i = 0; i < CMC_HISTORY_LENGTH; i++) {
1066                         if (now - cmc_history[i] <= HZ)
1067                                 count++;
1068                 }
1069
1070                 IA64_MCA_DEBUG(KERN_INFO "CMC threshold %d/%d\n", count, CMC_HISTORY_LENGTH);
1071                 if (count >= CMC_HISTORY_LENGTH) {
1072
1073                         cmc_polling_enabled = 1;
1074                         spin_unlock(&cmc_history_lock);
1075                         /* If we're being hit with CMC interrupts, we won't
1076                          * ever execute the schedule_work() below.  Need to
1077                          * disable CMC interrupts on this processor now.
1078                          */
1079                         ia64_mca_cmc_vector_disable(NULL);
1080                         schedule_work(&cmc_disable_work);
1081
1082                         /*
1083                          * Corrected errors will still be corrected, but
1084                          * make sure there's a log somewhere that indicates
1085                          * something is generating more than we can handle.
1086                          */
1087                         printk(KERN_WARNING "WARNING: Switching to polling CMC handler; error records may be lost\n");
1088
1089                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1090
1091                         /* lock already released, get out now */
1092                         return IRQ_HANDLED;
1093                 } else {
1094                         cmc_history[index++] = now;
1095                         if (index == CMC_HISTORY_LENGTH)
1096                                 index = 0;
1097                 }
1098         }
1099         spin_unlock(&cmc_history_lock);
1100         return IRQ_HANDLED;
1101 }
1102
1103 /*
1104  *  ia64_mca_cmc_int_caller
1105  *
1106  *      Triggered by sw interrupt from CMC polling routine.  Calls
1107  *      real interrupt handler and either triggers a sw interrupt
1108  *      on the next cpu or does cleanup at the end.
1109  *
1110  * Inputs
1111  *      interrupt number
1112  *      client data arg ptr
1113  *      saved registers ptr
1114  * Outputs
1115  *      handled
1116  */
1117 static irqreturn_t
1118 ia64_mca_cmc_int_caller(int cmc_irq, void *arg, struct pt_regs *ptregs)
1119 {
1120         static int start_count = -1;
1121         unsigned int cpuid;
1122
1123         cpuid = smp_processor_id();
1124
1125         /* If first cpu, update count */
1126         if (start_count == -1)
1127                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CMC);
1128
1129         ia64_mca_cmc_int_handler(cmc_irq, arg, ptregs);
1130
1131         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1132
1133         if (cpuid < NR_CPUS) {
1134                 platform_send_ipi(cpuid, IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1135         } else {
1136                 /* If no log record, switch out of polling mode */
1137                 if (start_count == IA64_LOG_COUNT(SAL_INFO_TYPE_CMC)) {
1138
1139                         printk(KERN_WARNING "Returning to interrupt driven CMC handler\n");
1140                         schedule_work(&cmc_enable_work);
1141                         cmc_polling_enabled = 0;
1142
1143                 } else {
1144
1145                         mod_timer(&cmc_poll_timer, jiffies + CMC_POLL_INTERVAL);
1146                 }
1147
1148                 start_count = -1;
1149         }
1150
1151         return IRQ_HANDLED;
1152 }
1153
1154 /*
1155  *  ia64_mca_cmc_poll
1156  *
1157  *      Poll for Corrected Machine Checks (CMCs)
1158  *
1159  * Inputs   :   dummy(unused)
1160  * Outputs  :   None
1161  *
1162  */
1163 static void
1164 ia64_mca_cmc_poll (unsigned long dummy)
1165 {
1166         /* Trigger a CMC interrupt cascade  */
1167         platform_send_ipi(first_cpu(cpu_online_map), IA64_CMCP_VECTOR, IA64_IPI_DM_INT, 0);
1168 }
1169
1170 /*
1171  *  ia64_mca_cpe_int_caller
1172  *
1173  *      Triggered by sw interrupt from CPE polling routine.  Calls
1174  *      real interrupt handler and either triggers a sw interrupt
1175  *      on the next cpu or does cleanup at the end.
1176  *
1177  * Inputs
1178  *      interrupt number
1179  *      client data arg ptr
1180  *      saved registers ptr
1181  * Outputs
1182  *      handled
1183  */
1184 #ifdef CONFIG_ACPI
1185
1186 static irqreturn_t
1187 ia64_mca_cpe_int_caller(int cpe_irq, void *arg, struct pt_regs *ptregs)
1188 {
1189         static int start_count = -1;
1190         static int poll_time = MIN_CPE_POLL_INTERVAL;
1191         unsigned int cpuid;
1192
1193         cpuid = smp_processor_id();
1194
1195         /* If first cpu, update count */
1196         if (start_count == -1)
1197                 start_count = IA64_LOG_COUNT(SAL_INFO_TYPE_CPE);
1198
1199         ia64_mca_cpe_int_handler(cpe_irq, arg, ptregs);
1200
1201         for (++cpuid ; cpuid < NR_CPUS && !cpu_online(cpuid) ; cpuid++);
1202
1203         if (cpuid < NR_CPUS) {
1204                 platform_send_ipi(cpuid, IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1205         } else {
1206                 /*
1207                  * If a log was recorded, increase our polling frequency,
1208                  * otherwise, backoff or return to interrupt mode.
1209                  */
1210                 if (start_count != IA64_LOG_COUNT(SAL_INFO_TYPE_CPE)) {
1211                         poll_time = max(MIN_CPE_POLL_INTERVAL, poll_time / 2);
1212                 } else if (cpe_vector < 0) {
1213                         poll_time = min(MAX_CPE_POLL_INTERVAL, poll_time * 2);
1214                 } else {
1215                         poll_time = MIN_CPE_POLL_INTERVAL;
1216
1217                         printk(KERN_WARNING "Returning to interrupt driven CPE handler\n");
1218                         enable_irq(local_vector_to_irq(IA64_CPE_VECTOR));
1219                         cpe_poll_enabled = 0;
1220                 }
1221
1222                 if (cpe_poll_enabled)
1223                         mod_timer(&cpe_poll_timer, jiffies + poll_time);
1224                 start_count = -1;
1225         }
1226
1227         return IRQ_HANDLED;
1228 }
1229
1230 /*
1231  *  ia64_mca_cpe_poll
1232  *
1233  *      Poll for Corrected Platform Errors (CPEs), trigger interrupt
1234  *      on first cpu, from there it will trickle through all the cpus.
1235  *
1236  * Inputs   :   dummy(unused)
1237  * Outputs  :   None
1238  *
1239  */
1240 static void
1241 ia64_mca_cpe_poll (unsigned long dummy)
1242 {
1243         /* Trigger a CPE interrupt cascade  */
1244         platform_send_ipi(first_cpu(cpu_online_map), IA64_CPEP_VECTOR, IA64_IPI_DM_INT, 0);
1245 }
1246
1247 #endif /* CONFIG_ACPI */
1248
1249 static int
1250 default_monarch_init_process(struct notifier_block *self, unsigned long val, void *data)
1251 {
1252         int c;
1253         struct task_struct *g, *t;
1254         if (val != DIE_INIT_MONARCH_PROCESS)
1255                 return NOTIFY_DONE;
1256         printk(KERN_ERR "Processes interrupted by INIT -");
1257         for_each_online_cpu(c) {
1258                 struct ia64_sal_os_state *s;
1259                 t = __va(__per_cpu_mca[c] + IA64_MCA_CPU_INIT_STACK_OFFSET);
1260                 s = (struct ia64_sal_os_state *)((char *)t + MCA_SOS_OFFSET);
1261                 g = s->prev_task;
1262                 if (g) {
1263                         if (g->pid)
1264                                 printk(" %d", g->pid);
1265                         else
1266                                 printk(" %d (cpu %d task 0x%p)", g->pid, task_cpu(g), g);
1267                 }
1268         }
1269         printk("\n\n");
1270         if (read_trylock(&tasklist_lock)) {
1271                 do_each_thread (g, t) {
1272                         printk("\nBacktrace of pid %d (%s)\n", t->pid, t->comm);
1273                         show_stack(t, NULL);
1274                 } while_each_thread (g, t);
1275                 read_unlock(&tasklist_lock);
1276         }
1277         return NOTIFY_DONE;
1278 }
1279
1280 /*
1281  * C portion of the OS INIT handler
1282  *
1283  * Called from ia64_os_init_dispatch
1284  *
1285  * Inputs: pointer to pt_regs where processor info was saved.  SAL/OS state for
1286  * this event.  This code is used for both monarch and slave INIT events, see
1287  * sos->monarch.
1288  *
1289  * All INIT events switch to the INIT stack and change the previous process to
1290  * blocked status.  If one of the INIT events is the monarch then we are
1291  * probably processing the nmi button/command.  Use the monarch cpu to dump all
1292  * the processes.  The slave INIT events all spin until the monarch cpu
1293  * returns.  We can also get INIT slave events for MCA, in which case the MCA
1294  * process is the monarch.
1295  */
1296
1297 void
1298 ia64_init_handler(struct pt_regs *regs, struct switch_stack *sw,
1299                   struct ia64_sal_os_state *sos)
1300 {
1301         static atomic_t slaves;
1302         static atomic_t monarchs;
1303         task_t *previous_current;
1304         int cpu = smp_processor_id();
1305
1306         oops_in_progress = 1;   /* FIXME: make printk NMI/MCA/INIT safe */
1307         console_loglevel = 15;  /* make sure printks make it to console */
1308
1309         printk(KERN_INFO "Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1310                 sos->proc_state_param, cpu, sos->monarch);
1311         salinfo_log_wakeup(SAL_INFO_TYPE_INIT, NULL, 0, 0);
1312
1313         previous_current = ia64_mca_modify_original_stack(regs, sw, sos, "INIT");
1314         sos->os_status = IA64_INIT_RESUME;
1315
1316         /* FIXME: Workaround for broken proms that drive all INIT events as
1317          * slaves.  The last slave that enters is promoted to be a monarch.
1318          * Remove this code in September 2006, that gives platforms a year to
1319          * fix their proms and get their customers updated.
1320          */
1321         if (!sos->monarch && atomic_add_return(1, &slaves) == num_online_cpus()) {
1322                 printk(KERN_WARNING "%s: Promoting cpu %d to monarch.\n",
1323                        __FUNCTION__, cpu);
1324                 atomic_dec(&slaves);
1325                 sos->monarch = 1;
1326         }
1327
1328         /* FIXME: Workaround for broken proms that drive all INIT events as
1329          * monarchs.  Second and subsequent monarchs are demoted to slaves.
1330          * Remove this code in September 2006, that gives platforms a year to
1331          * fix their proms and get their customers updated.
1332          */
1333         if (sos->monarch && atomic_add_return(1, &monarchs) > 1) {
1334                 printk(KERN_WARNING "%s: Demoting cpu %d to slave.\n",
1335                                __FUNCTION__, cpu);
1336                 atomic_dec(&monarchs);
1337                 sos->monarch = 0;
1338         }
1339
1340         if (!sos->monarch) {
1341                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_INIT;
1342                 while (monarch_cpu == -1)
1343                        cpu_relax();     /* spin until monarch enters */
1344                 if (notify_die(DIE_INIT_SLAVE_ENTER, "INIT", regs, 0, 0, 0)
1345                                 == NOTIFY_STOP)
1346                         ia64_mca_spin(__FUNCTION__);
1347                 if (notify_die(DIE_INIT_SLAVE_PROCESS, "INIT", regs, 0, 0, 0)
1348                                 == NOTIFY_STOP)
1349                         ia64_mca_spin(__FUNCTION__);
1350                 while (monarch_cpu != -1)
1351                        cpu_relax();     /* spin until monarch leaves */
1352                 if (notify_die(DIE_INIT_SLAVE_LEAVE, "INIT", regs, 0, 0, 0)
1353                                 == NOTIFY_STOP)
1354                         ia64_mca_spin(__FUNCTION__);
1355                 printk("Slave on cpu %d returning to normal service.\n", cpu);
1356                 set_curr_task(cpu, previous_current);
1357                 ia64_mc_info.imi_rendez_checkin[cpu] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1358                 atomic_dec(&slaves);
1359                 return;
1360         }
1361
1362         monarch_cpu = cpu;
1363         if (notify_die(DIE_INIT_MONARCH_ENTER, "INIT", regs, 0, 0, 0)
1364                         == NOTIFY_STOP)
1365                 ia64_mca_spin(__FUNCTION__);
1366
1367         /*
1368          * Wait for a bit.  On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1369          * generated via the BMC's command-line interface, but since the console is on the
1370          * same serial line, the user will need some time to switch out of the BMC before
1371          * the dump begins.
1372          */
1373         printk("Delaying for 5 seconds...\n");
1374         udelay(5*1000000);
1375         ia64_wait_for_slaves(cpu);
1376         /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1377          * to default_monarch_init_process() above and just print all the
1378          * tasks.
1379          */
1380         if (notify_die(DIE_INIT_MONARCH_PROCESS, "INIT", regs, 0, 0, 0)
1381                         == NOTIFY_STOP)
1382                 ia64_mca_spin(__FUNCTION__);
1383         if (notify_die(DIE_INIT_MONARCH_LEAVE, "INIT", regs, 0, 0, 0)
1384                         == NOTIFY_STOP)
1385                 ia64_mca_spin(__FUNCTION__);
1386         printk("\nINIT dump complete.  Monarch on cpu %d returning to normal service.\n", cpu);
1387         atomic_dec(&monarchs);
1388         set_curr_task(cpu, previous_current);
1389         monarch_cpu = -1;
1390         return;
1391 }
1392
1393 static int __init
1394 ia64_mca_disable_cpe_polling(char *str)
1395 {
1396         cpe_poll_enabled = 0;
1397         return 1;
1398 }
1399
1400 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling);
1401
1402 static struct irqaction cmci_irqaction = {
1403         .handler =      ia64_mca_cmc_int_handler,
1404         .flags =        SA_INTERRUPT,
1405         .name =         "cmc_hndlr"
1406 };
1407
1408 static struct irqaction cmcp_irqaction = {
1409         .handler =      ia64_mca_cmc_int_caller,
1410         .flags =        SA_INTERRUPT,
1411         .name =         "cmc_poll"
1412 };
1413
1414 static struct irqaction mca_rdzv_irqaction = {
1415         .handler =      ia64_mca_rendez_int_handler,
1416         .flags =        SA_INTERRUPT,
1417         .name =         "mca_rdzv"
1418 };
1419
1420 static struct irqaction mca_wkup_irqaction = {
1421         .handler =      ia64_mca_wakeup_int_handler,
1422         .flags =        SA_INTERRUPT,
1423         .name =         "mca_wkup"
1424 };
1425
1426 #ifdef CONFIG_ACPI
1427 static struct irqaction mca_cpe_irqaction = {
1428         .handler =      ia64_mca_cpe_int_handler,
1429         .flags =        SA_INTERRUPT,
1430         .name =         "cpe_hndlr"
1431 };
1432
1433 static struct irqaction mca_cpep_irqaction = {
1434         .handler =      ia64_mca_cpe_int_caller,
1435         .flags =        SA_INTERRUPT,
1436         .name =         "cpe_poll"
1437 };
1438 #endif /* CONFIG_ACPI */
1439
1440 /* Minimal format of the MCA/INIT stacks.  The pseudo processes that run on
1441  * these stacks can never sleep, they cannot return from the kernel to user
1442  * space, they do not appear in a normal ps listing.  So there is no need to
1443  * format most of the fields.
1444  */
1445
1446 static void
1447 format_mca_init_stack(void *mca_data, unsigned long offset,
1448                 const char *type, int cpu)
1449 {
1450         struct task_struct *p = (struct task_struct *)((char *)mca_data + offset);
1451         struct thread_info *ti;
1452         memset(p, 0, KERNEL_STACK_SIZE);
1453         ti = task_thread_info(p);
1454         ti->flags = _TIF_MCA_INIT;
1455         ti->preempt_count = 1;
1456         ti->task = p;
1457         ti->cpu = cpu;
1458         p->thread_info = ti;
1459         p->state = TASK_UNINTERRUPTIBLE;
1460         __set_bit(cpu, &p->cpus_allowed);
1461         INIT_LIST_HEAD(&p->tasks);
1462         p->parent = p->real_parent = p->group_leader = p;
1463         INIT_LIST_HEAD(&p->children);
1464         INIT_LIST_HEAD(&p->sibling);
1465         strncpy(p->comm, type, sizeof(p->comm)-1);
1466 }
1467
1468 /* Do per-CPU MCA-related initialization.  */
1469
1470 void __devinit
1471 ia64_mca_cpu_init(void *cpu_data)
1472 {
1473         void *pal_vaddr;
1474         static int first_time = 1;
1475
1476         if (first_time) {
1477                 void *mca_data;
1478                 int cpu;
1479
1480                 first_time = 0;
1481                 mca_data = alloc_bootmem(sizeof(struct ia64_mca_cpu)
1482                                          * NR_CPUS + KERNEL_STACK_SIZE);
1483                 mca_data = (void *)(((unsigned long)mca_data +
1484                                         KERNEL_STACK_SIZE - 1) &
1485                                 (-KERNEL_STACK_SIZE));
1486                 for (cpu = 0; cpu < NR_CPUS; cpu++) {
1487                         format_mca_init_stack(mca_data,
1488                                         offsetof(struct ia64_mca_cpu, mca_stack),
1489                                         "MCA", cpu);
1490                         format_mca_init_stack(mca_data,
1491                                         offsetof(struct ia64_mca_cpu, init_stack),
1492                                         "INIT", cpu);
1493                         __per_cpu_mca[cpu] = __pa(mca_data);
1494                         mca_data += sizeof(struct ia64_mca_cpu);
1495                 }
1496         }
1497
1498         /*
1499          * The MCA info structure was allocated earlier and its
1500          * physical address saved in __per_cpu_mca[cpu].  Copy that
1501          * address * to ia64_mca_data so we can access it as a per-CPU
1502          * variable.
1503          */
1504         __get_cpu_var(ia64_mca_data) = __per_cpu_mca[smp_processor_id()];
1505
1506         /*
1507          * Stash away a copy of the PTE needed to map the per-CPU page.
1508          * We may need it during MCA recovery.
1509          */
1510         __get_cpu_var(ia64_mca_per_cpu_pte) =
1511                 pte_val(mk_pte_phys(__pa(cpu_data), PAGE_KERNEL));
1512
1513         /*
1514          * Also, stash away a copy of the PAL address and the PTE
1515          * needed to map it.
1516          */
1517         pal_vaddr = efi_get_pal_addr();
1518         if (!pal_vaddr)
1519                 return;
1520         __get_cpu_var(ia64_mca_pal_base) =
1521                 GRANULEROUNDDOWN((unsigned long) pal_vaddr);
1522         __get_cpu_var(ia64_mca_pal_pte) = pte_val(mk_pte_phys(__pa(pal_vaddr),
1523                                                               PAGE_KERNEL));
1524 }
1525
1526 /*
1527  * ia64_mca_init
1528  *
1529  *  Do all the system level mca specific initialization.
1530  *
1531  *      1. Register spinloop and wakeup request interrupt vectors
1532  *
1533  *      2. Register OS_MCA handler entry point
1534  *
1535  *      3. Register OS_INIT handler entry point
1536  *
1537  *  4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1538  *
1539  *  Note that this initialization is done very early before some kernel
1540  *  services are available.
1541  *
1542  *  Inputs  :   None
1543  *
1544  *  Outputs :   None
1545  */
1546 void __init
1547 ia64_mca_init(void)
1548 {
1549         ia64_fptr_t *init_hldlr_ptr_monarch = (ia64_fptr_t *)ia64_os_init_dispatch_monarch;
1550         ia64_fptr_t *init_hldlr_ptr_slave = (ia64_fptr_t *)ia64_os_init_dispatch_slave;
1551         ia64_fptr_t *mca_hldlr_ptr = (ia64_fptr_t *)ia64_os_mca_dispatch;
1552         int i;
1553         s64 rc;
1554         struct ia64_sal_retval isrv;
1555         u64 timeout = IA64_MCA_RENDEZ_TIMEOUT;  /* platform specific */
1556         static struct notifier_block default_init_monarch_nb = {
1557                 .notifier_call = default_monarch_init_process,
1558                 .priority = 0/* we need to notified last */
1559         };
1560
1561         IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__);
1562
1563         /* Clear the Rendez checkin flag for all cpus */
1564         for(i = 0 ; i < NR_CPUS; i++)
1565                 ia64_mc_info.imi_rendez_checkin[i] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE;
1566
1567         /*
1568          * Register the rendezvous spinloop and wakeup mechanism with SAL
1569          */
1570
1571         /* Register the rendezvous interrupt vector with SAL */
1572         while (1) {
1573                 isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT,
1574                                               SAL_MC_PARAM_MECHANISM_INT,
1575                                               IA64_MCA_RENDEZ_VECTOR,
1576                                               timeout,
1577                                               SAL_MC_PARAM_RZ_ALWAYS);
1578                 rc = isrv.status;
1579                 if (rc == 0)
1580                         break;
1581                 if (rc == -2) {
1582                         printk(KERN_INFO "Increasing MCA rendezvous timeout from "
1583                                 "%ld to %ld milliseconds\n", timeout, isrv.v0);
1584                         timeout = isrv.v0;
1585                         continue;
1586                 }
1587                 printk(KERN_ERR "Failed to register rendezvous interrupt "
1588                        "with SAL (status %ld)\n", rc);
1589                 return;
1590         }
1591
1592         /* Register the wakeup interrupt vector with SAL */
1593         isrv = ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP,
1594                                       SAL_MC_PARAM_MECHANISM_INT,
1595                                       IA64_MCA_WAKEUP_VECTOR,
1596                                       0, 0);
1597         rc = isrv.status;
1598         if (rc) {
1599                 printk(KERN_ERR "Failed to register wakeup interrupt with SAL "
1600                        "(status %ld)\n", rc);
1601                 return;
1602         }
1603
1604         IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__);
1605
1606         ia64_mc_info.imi_mca_handler        = ia64_tpa(mca_hldlr_ptr->fp);
1607         /*
1608          * XXX - disable SAL checksum by setting size to 0; should be
1609          *      ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1610          */
1611         ia64_mc_info.imi_mca_handler_size       = 0;
1612
1613         /* Register the os mca handler with SAL */
1614         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_MCA,
1615                                        ia64_mc_info.imi_mca_handler,
1616                                        ia64_tpa(mca_hldlr_ptr->gp),
1617                                        ia64_mc_info.imi_mca_handler_size,
1618                                        0, 0, 0)))
1619         {
1620                 printk(KERN_ERR "Failed to register OS MCA handler with SAL "
1621                        "(status %ld)\n", rc);
1622                 return;
1623         }
1624
1625         IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__,
1626                        ia64_mc_info.imi_mca_handler, ia64_tpa(mca_hldlr_ptr->gp));
1627
1628         /*
1629          * XXX - disable SAL checksum by setting size to 0, should be
1630          * size of the actual init handler in mca_asm.S.
1631          */
1632         ia64_mc_info.imi_monarch_init_handler           = ia64_tpa(init_hldlr_ptr_monarch->fp);
1633         ia64_mc_info.imi_monarch_init_handler_size      = 0;
1634         ia64_mc_info.imi_slave_init_handler             = ia64_tpa(init_hldlr_ptr_slave->fp);
1635         ia64_mc_info.imi_slave_init_handler_size        = 0;
1636
1637         IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__,
1638                        ia64_mc_info.imi_monarch_init_handler);
1639
1640         /* Register the os init handler with SAL */
1641         if ((rc = ia64_sal_set_vectors(SAL_VECTOR_OS_INIT,
1642                                        ia64_mc_info.imi_monarch_init_handler,
1643                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1644                                        ia64_mc_info.imi_monarch_init_handler_size,
1645                                        ia64_mc_info.imi_slave_init_handler,
1646                                        ia64_tpa(ia64_getreg(_IA64_REG_GP)),
1647                                        ia64_mc_info.imi_slave_init_handler_size)))
1648         {
1649                 printk(KERN_ERR "Failed to register m/s INIT handlers with SAL "
1650                        "(status %ld)\n", rc);
1651                 return;
1652         }
1653         if (register_die_notifier(&default_init_monarch_nb)) {
1654                 printk(KERN_ERR "Failed to register default monarch INIT process\n");
1655                 return;
1656         }
1657
1658         IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__);
1659
1660         /*
1661          *  Configure the CMCI/P vector and handler. Interrupts for CMC are
1662          *  per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1663          */
1664         register_percpu_irq(IA64_CMC_VECTOR, &cmci_irqaction);
1665         register_percpu_irq(IA64_CMCP_VECTOR, &cmcp_irqaction);
1666         ia64_mca_cmc_vector_setup();       /* Setup vector on BSP */
1667
1668         /* Setup the MCA rendezvous interrupt vector */
1669         register_percpu_irq(IA64_MCA_RENDEZ_VECTOR, &mca_rdzv_irqaction);
1670
1671         /* Setup the MCA wakeup interrupt vector */
1672         register_percpu_irq(IA64_MCA_WAKEUP_VECTOR, &mca_wkup_irqaction);
1673
1674 #ifdef CONFIG_ACPI
1675         /* Setup the CPEI/P handler */
1676         register_percpu_irq(IA64_CPEP_VECTOR, &mca_cpep_irqaction);
1677 #endif
1678
1679         /* Initialize the areas set aside by the OS to buffer the
1680          * platform/processor error states for MCA/INIT/CMC
1681          * handling.
1682          */
1683         ia64_log_init(SAL_INFO_TYPE_MCA);
1684         ia64_log_init(SAL_INFO_TYPE_INIT);
1685         ia64_log_init(SAL_INFO_TYPE_CMC);
1686         ia64_log_init(SAL_INFO_TYPE_CPE);
1687
1688         mca_init = 1;
1689         printk(KERN_INFO "MCA related initialization done\n");
1690 }
1691
1692 /*
1693  * ia64_mca_late_init
1694  *
1695  *      Opportunity to setup things that require initialization later
1696  *      than ia64_mca_init.  Setup a timer to poll for CPEs if the
1697  *      platform doesn't support an interrupt driven mechanism.
1698  *
1699  *  Inputs  :   None
1700  *  Outputs :   Status
1701  */
1702 static int __init
1703 ia64_mca_late_init(void)
1704 {
1705         if (!mca_init)
1706                 return 0;
1707
1708         /* Setup the CMCI/P vector and handler */
1709         init_timer(&cmc_poll_timer);
1710         cmc_poll_timer.function = ia64_mca_cmc_poll;
1711
1712         /* Unmask/enable the vector */
1713         cmc_polling_enabled = 0;
1714         schedule_work(&cmc_enable_work);
1715
1716         IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__);
1717
1718 #ifdef CONFIG_ACPI
1719         /* Setup the CPEI/P vector and handler */
1720         cpe_vector = acpi_request_vector(ACPI_INTERRUPT_CPEI);
1721         init_timer(&cpe_poll_timer);
1722         cpe_poll_timer.function = ia64_mca_cpe_poll;
1723
1724         {
1725                 irq_desc_t *desc;
1726                 unsigned int irq;
1727
1728                 if (cpe_vector >= 0) {
1729                         /* If platform supports CPEI, enable the irq. */
1730                         cpe_poll_enabled = 0;
1731                         for (irq = 0; irq < NR_IRQS; ++irq)
1732                                 if (irq_to_vector(irq) == cpe_vector) {
1733                                         desc = irq_descp(irq);
1734                                         desc->status |= IRQ_PER_CPU;
1735                                         setup_irq(irq, &mca_cpe_irqaction);
1736                                         ia64_cpe_irq = irq;
1737                                 }
1738                         ia64_mca_register_cpev(cpe_vector);
1739                         IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__);
1740                 } else {
1741                         /* If platform doesn't support CPEI, get the timer going. */
1742                         if (cpe_poll_enabled) {
1743                                 ia64_mca_cpe_poll(0UL);
1744                                 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__);
1745                         }
1746                 }
1747         }
1748 #endif
1749
1750         return 0;
1751 }
1752
1753 device_initcall(ia64_mca_late_init);