arch/i386/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  */
   9
  10 #include <linux/init.h>
  11 #include <linux/notifier.h>
  12 #include <linux/smp.h>
  13 #include <linux/oprofile.h>
  14 #include <linux/sysdev.h>
  15 #include <linux/slab.h>
  16 #include <linux/moduleparam.h>
  17 #include <linux/kdebug.h>
  18 #include <asm/nmi.h>
  19 #include <asm/msr.h>
  20 #include <asm/apic.h>
  21
  22 #include "op_counter.h"
  23 #include "op_x86_model.h"
  24
  25 static struct op_x86_model_spec const * model;
  26 static struct op_msrs cpu_msrs[NR_CPUS];
  27 static unsigned long saved_lvtpc[NR_CPUS];
  28
  29 static int nmi_start(void);
  30 static void nmi_stop(void);
  31
  32 /* 0 == registered but off, 1 == registered and on */
  33 static int nmi_enabled = 0;
  34
  35 #ifdef CONFIG_PM
  36
  37 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
  38 {
  39         if (nmi_enabled == 1)
  40                 nmi_stop();
  41         return 0;
  42 }
  43
  44
  45 static int nmi_resume(struct sys_device *dev)
  46 {
  47         if (nmi_enabled == 1)
  48                 nmi_start();
  49         return 0;
  50 }
  51
  52
  53 static struct sysdev_class oprofile_sysclass = {
  54         set_kset_name("oprofile"),
  55         .resume         = nmi_resume,
  56         .suspend        = nmi_suspend,
  57 };
  58
  59
  60 static struct sys_device device_oprofile = {
  61         .id     = 0,
  62         .cls    = &oprofile_sysclass,
  63 };
  64
  65
  66 static int __init init_sysfs(void)
  67 {
  68         int error;
  69         if (!(error = sysdev_class_register(&oprofile_sysclass)))
  70                 error = sysdev_register(&device_oprofile);
  71         return error;
  72 }
  73
  74
  75 static void exit_sysfs(void)
  76 {
  77         sysdev_unregister(&device_oprofile);
  78         sysdev_class_unregister(&oprofile_sysclass);
  79 }
  80
  81 #else
  82 #define init_sysfs() do { } while (0)
  83 #define exit_sysfs() do { } while (0)
  84 #endif /* CONFIG_PM */
  85
  86 static int profile_exceptions_notify(struct notifier_block *self,
  87                                      unsigned long val, void *data)
  88 {
  89         struct die_args *args = (struct die_args *)data;
  90         int ret = NOTIFY_DONE;
  91         int cpu = smp_processor_id();
  92
  93         switch(val) {
  94         case DIE_NMI:
  95                 if (model->check_ctrs(args->regs, &cpu_msrs[cpu]))
  96                         ret = NOTIFY_STOP;
  97                 break;
  98         default:
  99                 break;
 100         }
 101         return ret;
 102 }
 103
 104 static void nmi_cpu_save_registers(struct op_msrs * msrs)
 105 {
 106         unsigned int const nr_ctrs = model->num_counters;
 107         unsigned int const nr_ctrls = model->num_controls;
 108         struct op_msr * counters = msrs->counters;
 109         struct op_msr * controls = msrs->controls;
 110         unsigned int i;
 111
 112         for (i = 0; i < nr_ctrs; ++i) {
 113                 if (counters[i].addr){
 114                         rdmsr(counters[i].addr,
 115                                 counters[i].saved.low,
 116                                 counters[i].saved.high);
 117                 }
 118         }
 119
 120         for (i = 0; i < nr_ctrls; ++i) {
 121                 if (controls[i].addr){
 122                         rdmsr(controls[i].addr,
 123                                 controls[i].saved.low,
 124                                 controls[i].saved.high);
 125                 }
 126         }
 127 }
 128
 129
 130 static void nmi_save_registers(void * dummy)
 131 {
 132         int cpu = smp_processor_id();
 133         struct op_msrs * msrs = &cpu_msrs[cpu];
 134         nmi_cpu_save_registers(msrs);
 135 }
 136
 137
 138 static void free_msrs(void)
 139 {
 140         int i;
 141         for_each_possible_cpu(i) {
 142                 kfree(cpu_msrs[i].counters);
 143                 cpu_msrs[i].counters = NULL;
 144                 kfree(cpu_msrs[i].controls);
 145                 cpu_msrs[i].controls = NULL;
 146         }
 147 }
 148
 149
 150 static int allocate_msrs(void)
 151 {
 152         int success = 1;
 153         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 154         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 155
 156         int i;
 157         for_each_online_cpu(i) {
 158                 cpu_msrs[i].counters = kmalloc(counters_size, GFP_KERNEL);
 159                 if (!cpu_msrs[i].counters) {
 160                         success = 0;
 161                         break;
 162                 }
 163                 cpu_msrs[i].controls = kmalloc(controls_size, GFP_KERNEL);
 164                 if (!cpu_msrs[i].controls) {
 165                         success = 0;
 166                         break;
 167                 }
 168         }
 169
 170         if (!success)
 171                 free_msrs();
 172
 173         return success;
 174 }
 175
 176
 177 static void nmi_cpu_setup(void * dummy)
 178 {
 179         int cpu = smp_processor_id();
 180         struct op_msrs * msrs = &cpu_msrs[cpu];
 181         spin_lock(&oprofilefs_lock);
 182         model->setup_ctrs(msrs);
 183         spin_unlock(&oprofilefs_lock);
 184         saved_lvtpc[cpu] = apic_read(APIC_LVTPC);
 185         apic_write(APIC_LVTPC, APIC_DM_NMI);
 186 }
 187
 188 static struct notifier_block profile_exceptions_nb = {
 189         .notifier_call = profile_exceptions_notify,
 190         .next = NULL,
 191         .priority = 0
 192 };
 193
 194 static int nmi_setup(void)
 195 {
 196         int err=0;
 197         int cpu;
 198
 199         if (!allocate_msrs())
 200                 return -ENOMEM;
 201
 202         if ((err = register_die_notifier(&profile_exceptions_nb))){
 203                 free_msrs();
 204                 return err;
 205         }
 206
 207         /* We need to serialize save and setup for HT because the subset
 208          * of msrs are distinct for save and setup operations
 209          */
 210
 211         /* Assume saved/restored counters are the same on all CPUs */
 212         model->fill_in_addresses(&cpu_msrs[0]);
 213         for_each_possible_cpu (cpu) {
 214                 if (cpu != 0)
 215                         cpu_msrs[cpu] = cpu_msrs[0];
 216         }
 217         on_each_cpu(nmi_save_registers, NULL, 0, 1);
 218         on_each_cpu(nmi_cpu_setup, NULL, 0, 1);
 219         nmi_enabled = 1;
 220         return 0;
 221 }
 222
 223
 224 static void nmi_restore_registers(struct op_msrs * msrs)
 225 {
 226         unsigned int const nr_ctrs = model->num_counters;
 227         unsigned int const nr_ctrls = model->num_controls;
 228         struct op_msr * counters = msrs->counters;
 229         struct op_msr * controls = msrs->controls;
 230         unsigned int i;
 231
 232         for (i = 0; i < nr_ctrls; ++i) {
 233                 if (controls[i].addr){
 234                         wrmsr(controls[i].addr,
 235                                 controls[i].saved.low,
 236                                 controls[i].saved.high);
 237                 }
 238         }
 239
 240         for (i = 0; i < nr_ctrs; ++i) {
 241                 if (counters[i].addr){
 242                         wrmsr(counters[i].addr,
 243                                 counters[i].saved.low,
 244                                 counters[i].saved.high);
 245                 }
 246         }
 247 }
 248
 249
 250 static void nmi_cpu_shutdown(void * dummy)
 251 {
 252         unsigned int v;
 253         int cpu = smp_processor_id();
 254         struct op_msrs * msrs = &cpu_msrs[cpu];
 255
 256         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 257          * mode and vector nr combination can be illegal. That's by design: on
 258          * power on apic lvt contain a zero vector nr which are legal only for
 259          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 260          */
 261         v = apic_read(APIC_LVTERR);
 262         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 263         apic_write(APIC_LVTPC, saved_lvtpc[cpu]);
 264         apic_write(APIC_LVTERR, v);
 265         nmi_restore_registers(msrs);
 266         model->shutdown(msrs);
 267 }
 268
 269
 270 static void nmi_shutdown(void)
 271 {
 272         nmi_enabled = 0;
 273         on_each_cpu(nmi_cpu_shutdown, NULL, 0, 1);
 274         unregister_die_notifier(&profile_exceptions_nb);
 275         free_msrs();
 276 }
 277
 278
 279 static void nmi_cpu_start(void * dummy)
 280 {
 281         struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
 282         model->start(msrs);
 283 }
 284
 285
 286 static int nmi_start(void)
 287 {
 288         on_each_cpu(nmi_cpu_start, NULL, 0, 1);
 289         return 0;
 290 }
 291
 292
 293 static void nmi_cpu_stop(void * dummy)
 294 {
 295         struct op_msrs const * msrs = &cpu_msrs[smp_processor_id()];
 296         model->stop(msrs);
 297 }
 298
 299
 300 static void nmi_stop(void)
 301 {
 302         on_each_cpu(nmi_cpu_stop, NULL, 0, 1);
 303 }
 304
 305
 306 struct op_counter_config counter_config[OP_MAX_COUNTER];
 307
 308 static int nmi_create_files(struct super_block * sb, struct dentry * root)
 309 {
 310         unsigned int i;
 311
 312         for (i = 0; i < model->num_counters; ++i) {
 313                 struct dentry * dir;
 314                 char buf[4];
 315
 316                 /* quick little hack to _not_ expose a counter if it is not
 317                  * available for use.  This should protect userspace app.
 318                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 319                  *        sequentially in their struct assignment).
 320                  */
 321                 if (unlikely(!avail_to_resrv_perfctr_nmi_bit(i)))
 322                         continue;
 323
 324                 snprintf(buf,  sizeof(buf), "%d", i);
 325                 dir = oprofilefs_mkdir(sb, root, buf);
 326                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 327                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 328                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 329                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 330                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 331                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 332         }
 333
 334         return 0;
 335 }
 336
 337 static int p4force;
 338 module_param(p4force, int, 0);
 339
 340 static int __init p4_init(char ** cpu_type)
 341 {
 342         __u8 cpu_model = boot_cpu_data.x86_model;
 343
 344         if (!p4force && (cpu_model > 6 || cpu_model == 5))
 345                 return 0;
 346
 347 #ifndef CONFIG_SMP
 348         *cpu_type = "i386/p4";
 349         model = &op_p4_spec;
 350         return 1;
 351 #else
 352         switch (smp_num_siblings) {
 353                 case 1:
 354                         *cpu_type = "i386/p4";
 355                         model = &op_p4_spec;
 356                         return 1;
 357
 358                 case 2:
 359                         *cpu_type = "i386/p4-ht";
 360                         model = &op_p4_ht2_spec;
 361                         return 1;
 362         }
 363 #endif
 364
 365         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 366         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 367         return 0;
 368 }
 369
 370
 371 static int __init ppro_init(char ** cpu_type)
 372 {
 373         __u8 cpu_model = boot_cpu_data.x86_model;
 374
 375         if (cpu_model == 14)
 376                 *cpu_type = "i386/core";
 377         else if (cpu_model == 15)
 378                 *cpu_type = "i386/core_2";
 379         else if (cpu_model > 0xd)
 380                 return 0;
 381         else if (cpu_model == 9) {
 382                 *cpu_type = "i386/p6_mobile";
 383         } else if (cpu_model > 5) {
 384                 *cpu_type = "i386/piii";
 385         } else if (cpu_model > 2) {
 386                 *cpu_type = "i386/pii";
 387         } else {
 388                 *cpu_type = "i386/ppro";
 389         }
 390
 391         model = &op_ppro_spec;
 392         return 1;
 393 }
 394
 395 /* in order to get sysfs right */
 396 static int using_nmi;
 397
 398 int __init op_nmi_init(struct oprofile_operations *ops)
 399 {
 400         __u8 vendor = boot_cpu_data.x86_vendor;
 401         __u8 family = boot_cpu_data.x86;
 402         char *cpu_type;
 403
 404         if (!cpu_has_apic)
 405                 return -ENODEV;
 406
 407         switch (vendor) {
 408                 case X86_VENDOR_AMD:
 409                         /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 410
 411                         switch (family) {
 412                         default:
 413                                 return -ENODEV;
 414                         case 6:
 415                                 model = &op_athlon_spec;
 416                                 cpu_type = "i386/athlon";
 417                                 break;
 418                         case 0xf:
 419                                 model = &op_athlon_spec;
 420                                 /* Actually it could be i386/hammer too, but give
 421                                    user space an consistent name. */
 422                                 cpu_type = "x86-64/hammer";
 423                                 break;
 424                         case 0x10:
 425                                 model = &op_athlon_spec;
 426                                 cpu_type = "x86-64/family10";
 427                                 break;
 428                         }
 429                         break;
 430
 431                 case X86_VENDOR_INTEL:
 432                         switch (family) {
 433                                 /* Pentium IV */
 434                                 case 0xf:
 435                                         if (!p4_init(&cpu_type))
 436                                                 return -ENODEV;
 437                                         break;
 438
 439                                 /* A P6-class processor */
 440                                 case 6:
 441                                         if (!ppro_init(&cpu_type))
 442                                                 return -ENODEV;
 443                                         break;
 444
 445                                 default:
 446                                         return -ENODEV;
 447                         }
 448                         break;
 449
 450                 default:
 451                         return -ENODEV;
 452         }
 453
 454         init_sysfs();
 455         using_nmi = 1;
 456         ops->create_files = nmi_create_files;
 457         ops->setup = nmi_setup;
 458         ops->shutdown = nmi_shutdown;
 459         ops->start = nmi_start;
 460         ops->stop = nmi_stop;
 461         ops->cpu_type = cpu_type;
 462         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 463         return 0;
 464 }
 465
 466
 467 void op_nmi_exit(void)
 468 {
 469         if (using_nmi)
 470                 exit_sysfs();
 471 }