arch/i386/mach-visws/visws_apic.c

   1 /*
   2  *      linux/arch/i386/mach-visws/visws_apic.c
   3  *
   4  *      Copyright (C) 1999 Bent Hagemark, Ingo Molnar
   5  *
   6  *  SGI Visual Workstation interrupt controller
   7  *
   8  *  The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
   9  *  which serves as the main interrupt controller in the system.  Non-legacy
  10  *  hardware in the system uses this controller directly.  Legacy devices
  11  *  are connected to the PIIX4 which in turn has its 8259(s) connected to
  12  *  a of the Cobalt APIC entry.
  13  *
  14  *  09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
  15  *
  16  *  25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
  17  */
  18
  19 #include <linux/kernel_stat.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/smp_lock.h>
  22 #include <linux/init.h>
  23
  24 #include <asm/io.h>
  25 #include <asm/apic.h>
  26 #include <asm/i8259.h>
  27
  28 #include "cobalt.h"
  29 #include "irq_vectors.h"
  30
  31
  32 static DEFINE_SPINLOCK(cobalt_lock);
  33
  34 /*
  35  * Set the given Cobalt APIC Redirection Table entry to point
  36  * to the given IDT vector/index.
  37  */
  38 static inline void co_apic_set(int entry, int irq)
  39 {
  40         co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
  41         co_apic_write(CO_APIC_HI(entry), 0);
  42 }
  43
  44 /*
  45  * Cobalt (IO)-APIC functions to handle PCI devices.
  46  */
  47 static inline int co_apic_ide0_hack(void)
  48 {
  49         extern char visws_board_type;
  50         extern char visws_board_rev;
  51
  52         if (visws_board_type == VISWS_320 && visws_board_rev == 5)
  53                 return 5;
  54         return CO_APIC_IDE0;
  55 }
  56
  57 static int is_co_apic(unsigned int irq)
  58 {
  59         if (IS_CO_APIC(irq))
  60                 return CO_APIC(irq);
  61
  62         switch (irq) {
  63                 case 0: return CO_APIC_CPU;
  64                 case CO_IRQ_IDE0: return co_apic_ide0_hack();
  65                 case CO_IRQ_IDE1: return CO_APIC_IDE1;
  66                 default: return -1;
  67         }
  68 }
  69
  70
  71 /*
  72  * This is the SGI Cobalt (IO-)APIC:
  73  */
  74
  75 static void enable_cobalt_irq(unsigned int irq)
  76 {
  77         co_apic_set(is_co_apic(irq), irq);
  78 }
  79
  80 static void disable_cobalt_irq(unsigned int irq)
  81 {
  82         int entry = is_co_apic(irq);
  83
  84         co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
  85         co_apic_read(CO_APIC_LO(entry));
  86 }
  87
  88 /*
  89  * "irq" really just serves to identify the device.  Here is where we
  90  * map this to the Cobalt APIC entry where it's physically wired.
  91  * This is called via request_irq -> setup_irq -> irq_desc->startup()
  92  */
  93 static unsigned int startup_cobalt_irq(unsigned int irq)
  94 {
  95         unsigned long flags;
  96
  97         spin_lock_irqsave(&cobalt_lock, flags);
  98         if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
  99                 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
 100         enable_cobalt_irq(irq);
 101         spin_unlock_irqrestore(&cobalt_lock, flags);
 102         return 0;
 103 }
 104
 105 static void ack_cobalt_irq(unsigned int irq)
 106 {
 107         unsigned long flags;
 108
 109         spin_lock_irqsave(&cobalt_lock, flags);
 110         disable_cobalt_irq(irq);
 111         apic_write(APIC_EOI, APIC_EIO_ACK);
 112         spin_unlock_irqrestore(&cobalt_lock, flags);
 113 }
 114
 115 static void end_cobalt_irq(unsigned int irq)
 116 {
 117         unsigned long flags;
 118
 119         spin_lock_irqsave(&cobalt_lock, flags);
 120         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
 121                 enable_cobalt_irq(irq);
 122         spin_unlock_irqrestore(&cobalt_lock, flags);
 123 }
 124
 125 static struct hw_interrupt_type cobalt_irq_type = {
 126         .typename =     "Cobalt-APIC",
 127         .startup =      startup_cobalt_irq,
 128         .shutdown =     disable_cobalt_irq,
 129         .enable =       enable_cobalt_irq,
 130         .disable =      disable_cobalt_irq,
 131         .ack =          ack_cobalt_irq,
 132         .end =          end_cobalt_irq,
 133 };
 134
 135
 136 /*
 137  * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
 138  * -- not the manner expected by the code in i8259.c.
 139  *
 140  * there is a 'master' physical interrupt source that gets sent to
 141  * the CPU. But in the chipset there are various 'virtual' interrupts
 142  * waiting to be handled. We represent this to Linux through a 'master'
 143  * interrupt controller type, and through a special virtual interrupt-
 144  * controller. Device drivers only see the virtual interrupt sources.
 145  */
 146 static unsigned int startup_piix4_master_irq(unsigned int irq)
 147 {
 148         init_8259A(0);
 149
 150         return startup_cobalt_irq(irq);
 151 }
 152
 153 static void end_piix4_master_irq(unsigned int irq)
 154 {
 155         unsigned long flags;
 156
 157         spin_lock_irqsave(&cobalt_lock, flags);
 158         enable_cobalt_irq(irq);
 159         spin_unlock_irqrestore(&cobalt_lock, flags);
 160 }
 161
 162 static struct hw_interrupt_type piix4_master_irq_type = {
 163         .typename =     "PIIX4-master",
 164         .startup =      startup_piix4_master_irq,
 165         .ack =          ack_cobalt_irq,
 166         .end =          end_piix4_master_irq,
 167 };
 168
 169
 170 static struct hw_interrupt_type piix4_virtual_irq_type = {
 171         .typename =     "PIIX4-virtual",
 172         .startup =      startup_8259A_irq,
 173         .shutdown =     disable_8259A_irq,
 174         .enable =       enable_8259A_irq,
 175         .disable =      disable_8259A_irq,
 176 };
 177
 178
 179 /*
 180  * PIIX4-8259 master/virtual functions to handle interrupt requests
 181  * from legacy devices: floppy, parallel, serial, rtc.
 182  *
 183  * None of these get Cobalt APIC entries, neither do they have IDT
 184  * entries. These interrupts are purely virtual and distributed from
 185  * the 'master' interrupt source: CO_IRQ_8259.
 186  *
 187  * When the 8259 interrupts its handler figures out which of these
 188  * devices is interrupting and dispatches to its handler.
 189  *
 190  * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
 191  * enable_irq gets the right irq. This 'master' irq is never directly
 192  * manipulated by any driver.
 193  */
 194 static irqreturn_t piix4_master_intr(int irq, void *dev_id)
 195 {
 196         int realirq;
 197         irq_desc_t *desc;
 198         unsigned long flags;
 199
 200         spin_lock_irqsave(&i8259A_lock, flags);
 201
 202         /* Find out what's interrupting in the PIIX4 master 8259 */
 203         outb(0x0c, 0x20);               /* OCW3 Poll command */
 204         realirq = inb(0x20);
 205
 206         /*
 207          * Bit 7 == 0 means invalid/spurious
 208          */
 209         if (unlikely(!(realirq & 0x80)))
 210                 goto out_unlock;
 211
 212         realirq &= 7;
 213
 214         if (unlikely(realirq == 2)) {
 215                 outb(0x0c, 0xa0);
 216                 realirq = inb(0xa0);
 217
 218                 if (unlikely(!(realirq & 0x80)))
 219                         goto out_unlock;
 220
 221                 realirq = (realirq & 7) + 8;
 222         }
 223
 224         /* mask and ack interrupt */
 225         cached_irq_mask |= 1 << realirq;
 226         if (unlikely(realirq > 7)) {
 227                 inb(0xa1);
 228                 outb(cached_slave_mask, 0xa1);
 229                 outb(0x60 + (realirq & 7), 0xa0);
 230                 outb(0x60 + 2, 0x20);
 231         } else {
 232                 inb(0x21);
 233                 outb(cached_master_mask, 0x21);
 234                 outb(0x60 + realirq, 0x20);
 235         }
 236
 237         spin_unlock_irqrestore(&i8259A_lock, flags);
 238
 239         desc = irq_desc + realirq;
 240
 241         /*
 242          * handle this 'virtual interrupt' as a Cobalt one now.
 243          */
 244         kstat_cpu(smp_processor_id()).irqs[realirq]++;
 245
 246         if (likely(desc->action != NULL))
 247                 handle_IRQ_event(realirq, desc->action);
 248
 249         if (!(desc->status & IRQ_DISABLED))
 250                 enable_8259A_irq(realirq);
 251
 252         return IRQ_HANDLED;
 253
 254 out_unlock:
 255         spin_unlock_irqrestore(&i8259A_lock, flags);
 256         return IRQ_NONE;
 257 }
 258
 259 static struct irqaction master_action = {
 260         .handler =      piix4_master_intr,
 261         .name =         "PIIX4-8259",
 262 };
 263
 264 static struct irqaction cascade_action = {
 265         .handler =      no_action,
 266         .name =         "cascade",
 267 };
 268
 269
 270 void init_VISWS_APIC_irqs(void)
 271 {
 272         int i;
 273
 274         for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
 275                 irq_desc[i].status = IRQ_DISABLED;
 276                 irq_desc[i].action = 0;
 277                 irq_desc[i].depth = 1;
 278
 279                 if (i == 0) {
 280                         irq_desc[i].chip = &cobalt_irq_type;
 281                 }
 282                 else if (i == CO_IRQ_IDE0) {
 283                         irq_desc[i].chip = &cobalt_irq_type;
 284                 }
 285                 else if (i == CO_IRQ_IDE1) {
 286                         irq_desc[i].chip = &cobalt_irq_type;
 287                 }
 288                 else if (i == CO_IRQ_8259) {
 289                         irq_desc[i].chip = &piix4_master_irq_type;
 290                 }
 291                 else if (i < CO_IRQ_APIC0) {
 292                         irq_desc[i].chip = &piix4_virtual_irq_type;
 293                 }
 294                 else if (IS_CO_APIC(i)) {
 295                         irq_desc[i].chip = &cobalt_irq_type;
 296                 }
 297         }
 298
 299         setup_irq(CO_IRQ_8259, &master_action);
 300         setup_irq(2, &cascade_action);
 301 }