arch/i386/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/compiler.h>
  33 #include <linux/acpi.h>
  34 #include <linux/module.h>
  35 #include <linux/sysdev.h>
  36
  37 #include <asm/io.h>
  38 #include <asm/smp.h>
  39 #include <asm/desc.h>
  40 #include <asm/timer.h>
  41 #include <asm/i8259.h>
  42
  43 #include <mach_apic.h>
  44
  45 #include "io_ports.h"
  46
  47 int (*ioapic_renumber_irq)(int ioapic, int irq);
  48 atomic_t irq_mis_count;
  49
  50 static DEFINE_SPINLOCK(ioapic_lock);
  51
  52 /*
  53  *      Is the SiS APIC rmw bug present ?
  54  *      -1 = don't know, 0 = no, 1 = yes
  55  */
  56 int sis_apic_bug = -1;
  57
  58 /*
  59  * # of IRQ routing registers
  60  */
  61 int nr_ioapic_registers[MAX_IO_APICS];
  62
  63 /*
  64  * Rough estimation of how many shared IRQs there are, can
  65  * be changed anytime.
  66  */
  67 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  68 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  69
  70 /*
  71  * This is performance-critical, we want to do it O(1)
  72  *
  73  * the indexing order of this array favors 1:1 mappings
  74  * between pins and IRQs.
  75  */
  76
  77 static struct irq_pin_list {
  78         int apic, pin, next;
  79 } irq_2_pin[PIN_MAP_SIZE];
  80
  81 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  82 #ifdef CONFIG_PCI_MSI
  83 #define vector_to_irq(vector)   \
  84         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  85 #else
  86 #define vector_to_irq(vector)   (vector)
  87 #endif
  88
  89 /*
  90  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  91  * shared ISA-space IRQs, so we have to support them. We are super
  92  * fast in the common case, and fast for shared ISA-space IRQs.
  93  */
  94 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  95 {
  96         static int first_free_entry = NR_IRQS;
  97         struct irq_pin_list *entry = irq_2_pin + irq;
  98
  99         while (entry->next)
 100                 entry = irq_2_pin + entry->next;
 101
 102         if (entry->pin != -1) {
 103                 entry->next = first_free_entry;
 104                 entry = irq_2_pin + entry->next;
 105                 if (++first_free_entry >= PIN_MAP_SIZE)
 106                         panic("io_apic.c: whoops");
 107         }
 108         entry->apic = apic;
 109         entry->pin = pin;
 110 }
 111
 112 /*
 113  * Reroute an IRQ to a different pin.
 114  */
 115 static void __init replace_pin_at_irq(unsigned int irq,
 116                                       int oldapic, int oldpin,
 117                                       int newapic, int newpin)
 118 {
 119         struct irq_pin_list *entry = irq_2_pin + irq;
 120
 121         while (1) {
 122                 if (entry->apic == oldapic && entry->pin == oldpin) {
 123                         entry->apic = newapic;
 124                         entry->pin = newpin;
 125                 }
 126                 if (!entry->next)
 127                         break;
 128                 entry = irq_2_pin + entry->next;
 129         }
 130 }
 131
 132 static void __modify_IO_APIC_irq (unsigned int irq, unsigned long enable, unsigned long disable)
 133 {
 134         struct irq_pin_list *entry = irq_2_pin + irq;
 135         unsigned int pin, reg;
 136
 137         for (;;) {
 138                 pin = entry->pin;
 139                 if (pin == -1)
 140                         break;
 141                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 142                 reg &= ~disable;
 143                 reg |= enable;
 144                 io_apic_modify(entry->apic, 0x10 + pin*2, reg);
 145                 if (!entry->next)
 146                         break;
 147                 entry = irq_2_pin + entry->next;
 148         }
 149 }
 150
 151 /* mask = 1 */
 152 static void __mask_IO_APIC_irq (unsigned int irq)
 153 {
 154         __modify_IO_APIC_irq(irq, 0x00010000, 0);
 155 }
 156
 157 /* mask = 0 */
 158 static void __unmask_IO_APIC_irq (unsigned int irq)
 159 {
 160         __modify_IO_APIC_irq(irq, 0, 0x00010000);
 161 }
 162
 163 /* mask = 1, trigger = 0 */
 164 static void __mask_and_edge_IO_APIC_irq (unsigned int irq)
 165 {
 166         __modify_IO_APIC_irq(irq, 0x00010000, 0x00008000);
 167 }
 168
 169 /* mask = 0, trigger = 1 */
 170 static void __unmask_and_level_IO_APIC_irq (unsigned int irq)
 171 {
 172         __modify_IO_APIC_irq(irq, 0x00008000, 0x00010000);
 173 }
 174
 175 static void mask_IO_APIC_irq (unsigned int irq)
 176 {
 177         unsigned long flags;
 178
 179         spin_lock_irqsave(&ioapic_lock, flags);
 180         __mask_IO_APIC_irq(irq);
 181         spin_unlock_irqrestore(&ioapic_lock, flags);
 182 }
 183
 184 static void unmask_IO_APIC_irq (unsigned int irq)
 185 {
 186         unsigned long flags;
 187
 188         spin_lock_irqsave(&ioapic_lock, flags);
 189         __unmask_IO_APIC_irq(irq);
 190         spin_unlock_irqrestore(&ioapic_lock, flags);
 191 }
 192
 193 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 194 {
 195         struct IO_APIC_route_entry entry;
 196         unsigned long flags;
 197
 198         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 199         spin_lock_irqsave(&ioapic_lock, flags);
 200         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 201         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 202         spin_unlock_irqrestore(&ioapic_lock, flags);
 203         if (entry.delivery_mode == dest_SMI)
 204                 return;
 205
 206         /*
 207          * Disable it in the IO-APIC irq-routing table:
 208          */
 209         memset(&entry, 0, sizeof(entry));
 210         entry.mask = 1;
 211         spin_lock_irqsave(&ioapic_lock, flags);
 212         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 213         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 214         spin_unlock_irqrestore(&ioapic_lock, flags);
 215 }
 216
 217 static void clear_IO_APIC (void)
 218 {
 219         int apic, pin;
 220
 221         for (apic = 0; apic < nr_ioapics; apic++)
 222                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 223                         clear_IO_APIC_pin(apic, pin);
 224 }
 225
 226 #ifdef CONFIG_SMP
 227 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t cpumask)
 228 {
 229         unsigned long flags;
 230         int pin;
 231         struct irq_pin_list *entry = irq_2_pin + irq;
 232         unsigned int apicid_value;
 233         cpumask_t tmp;
 234
 235         cpus_and(tmp, cpumask, cpu_online_map);
 236         if (cpus_empty(tmp))
 237                 tmp = TARGET_CPUS;
 238
 239         cpus_and(cpumask, tmp, CPU_MASK_ALL);
 240
 241         apicid_value = cpu_mask_to_apicid(cpumask);
 242         /* Prepare to do the io_apic_write */
 243         apicid_value = apicid_value << 24;
 244         spin_lock_irqsave(&ioapic_lock, flags);
 245         for (;;) {
 246                 pin = entry->pin;
 247                 if (pin == -1)
 248                         break;
 249                 io_apic_write(entry->apic, 0x10 + 1 + pin*2, apicid_value);
 250                 if (!entry->next)
 251                         break;
 252                 entry = irq_2_pin + entry->next;
 253         }
 254         set_irq_info(irq, cpumask);
 255         spin_unlock_irqrestore(&ioapic_lock, flags);
 256 }
 257
 258 #if defined(CONFIG_IRQBALANCE)
 259 # include <asm/processor.h>     /* kernel_thread() */
 260 # include <linux/kernel_stat.h> /* kstat */
 261 # include <linux/slab.h>                /* kmalloc() */
 262 # include <linux/timer.h>       /* time_after() */
 263
 264 # ifdef CONFIG_BALANCED_IRQ_DEBUG
 265 #  define TDprintk(x...) do { printk("<%ld:%s:%d>: ", jiffies, __FILE__, __LINE__); printk(x); } while (0)
 266 #  define Dprintk(x...) do { TDprintk(x); } while (0)
 267 # else
 268 #  define TDprintk(x...)
 269 #  define Dprintk(x...)
 270 # endif
 271
 272
 273 #define IRQBALANCE_CHECK_ARCH -999
 274 static int irqbalance_disabled = IRQBALANCE_CHECK_ARCH;
 275 static int physical_balance = 0;
 276
 277 static struct irq_cpu_info {
 278         unsigned long * last_irq;
 279         unsigned long * irq_delta;
 280         unsigned long irq;
 281 } irq_cpu_data[NR_CPUS];
 282
 283 #define CPU_IRQ(cpu)            (irq_cpu_data[cpu].irq)
 284 #define LAST_CPU_IRQ(cpu,irq)   (irq_cpu_data[cpu].last_irq[irq])
 285 #define IRQ_DELTA(cpu,irq)      (irq_cpu_data[cpu].irq_delta[irq])
 286
 287 #define IDLE_ENOUGH(cpu,now) \
 288         (idle_cpu(cpu) && ((now) - per_cpu(irq_stat, (cpu)).idle_timestamp > 1))
 289
 290 #define IRQ_ALLOWED(cpu, allowed_mask)  cpu_isset(cpu, allowed_mask)
 291
 292 #define CPU_TO_PACKAGEINDEX(i) (first_cpu(cpu_sibling_map[i]))
 293
 294 #define MAX_BALANCED_IRQ_INTERVAL       (5*HZ)
 295 #define MIN_BALANCED_IRQ_INTERVAL       (HZ/2)
 296 #define BALANCED_IRQ_MORE_DELTA         (HZ/10)
 297 #define BALANCED_IRQ_LESS_DELTA         (HZ)
 298
 299 static long balanced_irq_interval = MAX_BALANCED_IRQ_INTERVAL;
 300
 301 static unsigned long move(int curr_cpu, cpumask_t allowed_mask,
 302                         unsigned long now, int direction)
 303 {
 304         int search_idle = 1;
 305         int cpu = curr_cpu;
 306
 307         goto inside;
 308
 309         do {
 310                 if (unlikely(cpu == curr_cpu))
 311                         search_idle = 0;
 312 inside:
 313                 if (direction == 1) {
 314                         cpu++;
 315                         if (cpu >= NR_CPUS)
 316                                 cpu = 0;
 317                 } else {
 318                         cpu--;
 319                         if (cpu == -1)
 320                                 cpu = NR_CPUS-1;
 321                 }
 322         } while (!cpu_online(cpu) || !IRQ_ALLOWED(cpu,allowed_mask) ||
 323                         (search_idle && !IDLE_ENOUGH(cpu,now)));
 324
 325         return cpu;
 326 }
 327
 328 static inline void balance_irq(int cpu, int irq)
 329 {
 330         unsigned long now = jiffies;
 331         cpumask_t allowed_mask;
 332         unsigned int new_cpu;
 333
 334         if (irqbalance_disabled)
 335                 return;
 336
 337         cpus_and(allowed_mask, cpu_online_map, irq_affinity[irq]);
 338         new_cpu = move(cpu, allowed_mask, now, 1);
 339         if (cpu != new_cpu) {
 340                 set_pending_irq(irq, cpumask_of_cpu(new_cpu));
 341         }
 342 }
 343
 344 static inline void rotate_irqs_among_cpus(unsigned long useful_load_threshold)
 345 {
 346         int i, j;
 347         Dprintk("Rotating IRQs among CPUs.\n");
 348         for (i = 0; i < NR_CPUS; i++) {
 349                 for (j = 0; cpu_online(i) && (j < NR_IRQS); j++) {
 350                         if (!irq_desc[j].action)
 351                                 continue;
 352                         /* Is it a significant load ?  */
 353                         if (IRQ_DELTA(CPU_TO_PACKAGEINDEX(i),j) <
 354                                                 useful_load_threshold)
 355                                 continue;
 356                         balance_irq(i, j);
 357                 }
 358         }
 359         balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 360                 balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 361         return;
 362 }
 363
 364 static void do_irq_balance(void)
 365 {
 366         int i, j;
 367         unsigned long max_cpu_irq = 0, min_cpu_irq = (~0);
 368         unsigned long move_this_load = 0;
 369         int max_loaded = 0, min_loaded = 0;
 370         int load;
 371         unsigned long useful_load_threshold = balanced_irq_interval + 10;
 372         int selected_irq;
 373         int tmp_loaded, first_attempt = 1;
 374         unsigned long tmp_cpu_irq;
 375         unsigned long imbalance = 0;
 376         cpumask_t allowed_mask, target_cpu_mask, tmp;
 377
 378         for (i = 0; i < NR_CPUS; i++) {
 379                 int package_index;
 380                 CPU_IRQ(i) = 0;
 381                 if (!cpu_online(i))
 382                         continue;
 383                 package_index = CPU_TO_PACKAGEINDEX(i);
 384                 for (j = 0; j < NR_IRQS; j++) {
 385                         unsigned long value_now, delta;
 386                         /* Is this an active IRQ? */
 387                         if (!irq_desc[j].action)
 388                                 continue;
 389                         if ( package_index == i )
 390                                 IRQ_DELTA(package_index,j) = 0;
 391                         /* Determine the total count per processor per IRQ */
 392                         value_now = (unsigned long) kstat_cpu(i).irqs[j];
 393
 394                         /* Determine the activity per processor per IRQ */
 395                         delta = value_now - LAST_CPU_IRQ(i,j);
 396
 397                         /* Update last_cpu_irq[][] for the next time */
 398                         LAST_CPU_IRQ(i,j) = value_now;
 399
 400                         /* Ignore IRQs whose rate is less than the clock */
 401                         if (delta < useful_load_threshold)
 402                                 continue;
 403                         /* update the load for the processor or package total */
 404                         IRQ_DELTA(package_index,j) += delta;
 405
 406                         /* Keep track of the higher numbered sibling as well */
 407                         if (i != package_index)
 408                                 CPU_IRQ(i) += delta;
 409                         /*
 410                          * We have sibling A and sibling B in the package
 411                          *
 412                          * cpu_irq[A] = load for cpu A + load for cpu B
 413                          * cpu_irq[B] = load for cpu B
 414                          */
 415                         CPU_IRQ(package_index) += delta;
 416                 }
 417         }
 418         /* Find the least loaded processor package */
 419         for (i = 0; i < NR_CPUS; i++) {
 420                 if (!cpu_online(i))
 421                         continue;
 422                 if (i != CPU_TO_PACKAGEINDEX(i))
 423                         continue;
 424                 if (min_cpu_irq > CPU_IRQ(i)) {
 425                         min_cpu_irq = CPU_IRQ(i);
 426                         min_loaded = i;
 427                 }
 428         }
 429         max_cpu_irq = ULONG_MAX;
 430
 431 tryanothercpu:
 432         /* Look for heaviest loaded processor.
 433          * We may come back to get the next heaviest loaded processor.
 434          * Skip processors with trivial loads.
 435          */
 436         tmp_cpu_irq = 0;
 437         tmp_loaded = -1;
 438         for (i = 0; i < NR_CPUS; i++) {
 439                 if (!cpu_online(i))
 440                         continue;
 441                 if (i != CPU_TO_PACKAGEINDEX(i))
 442                         continue;
 443                 if (max_cpu_irq <= CPU_IRQ(i))
 444                         continue;
 445                 if (tmp_cpu_irq < CPU_IRQ(i)) {
 446                         tmp_cpu_irq = CPU_IRQ(i);
 447                         tmp_loaded = i;
 448                 }
 449         }
 450
 451         if (tmp_loaded == -1) {
 452          /* In the case of small number of heavy interrupt sources,
 453           * loading some of the cpus too much. We use Ingo's original
 454           * approach to rotate them around.
 455           */
 456                 if (!first_attempt && imbalance >= useful_load_threshold) {
 457                         rotate_irqs_among_cpus(useful_load_threshold);
 458                         return;
 459                 }
 460                 goto not_worth_the_effort;
 461         }
 462
 463         first_attempt = 0;              /* heaviest search */
 464         max_cpu_irq = tmp_cpu_irq;      /* load */
 465         max_loaded = tmp_loaded;        /* processor */
 466         imbalance = (max_cpu_irq - min_cpu_irq) / 2;
 467
 468         Dprintk("max_loaded cpu = %d\n", max_loaded);
 469         Dprintk("min_loaded cpu = %d\n", min_loaded);
 470         Dprintk("max_cpu_irq load = %ld\n", max_cpu_irq);
 471         Dprintk("min_cpu_irq load = %ld\n", min_cpu_irq);
 472         Dprintk("load imbalance = %lu\n", imbalance);
 473
 474         /* if imbalance is less than approx 10% of max load, then
 475          * observe diminishing returns action. - quit
 476          */
 477         if (imbalance < (max_cpu_irq >> 3)) {
 478                 Dprintk("Imbalance too trivial\n");
 479                 goto not_worth_the_effort;
 480         }
 481
 482 tryanotherirq:
 483         /* if we select an IRQ to move that can't go where we want, then
 484          * see if there is another one to try.
 485          */
 486         move_this_load = 0;
 487         selected_irq = -1;
 488         for (j = 0; j < NR_IRQS; j++) {
 489                 /* Is this an active IRQ? */
 490                 if (!irq_desc[j].action)
 491                         continue;
 492                 if (imbalance <= IRQ_DELTA(max_loaded,j))
 493                         continue;
 494                 /* Try to find the IRQ that is closest to the imbalance
 495                  * without going over.
 496                  */
 497                 if (move_this_load < IRQ_DELTA(max_loaded,j)) {
 498                         move_this_load = IRQ_DELTA(max_loaded,j);
 499                         selected_irq = j;
 500                 }
 501         }
 502         if (selected_irq == -1) {
 503                 goto tryanothercpu;
 504         }
 505
 506         imbalance = move_this_load;
 507
 508         /* For physical_balance case, we accumlated both load
 509          * values in the one of the siblings cpu_irq[],
 510          * to use the same code for physical and logical processors
 511          * as much as possible.
 512          *
 513          * NOTE: the cpu_irq[] array holds the sum of the load for
 514          * sibling A and sibling B in the slot for the lowest numbered
 515          * sibling (A), _AND_ the load for sibling B in the slot for
 516          * the higher numbered sibling.
 517          *
 518          * We seek the least loaded sibling by making the comparison
 519          * (A+B)/2 vs B
 520          */
 521         load = CPU_IRQ(min_loaded) >> 1;
 522         for_each_cpu_mask(j, cpu_sibling_map[min_loaded]) {
 523                 if (load > CPU_IRQ(j)) {
 524                         /* This won't change cpu_sibling_map[min_loaded] */
 525                         load = CPU_IRQ(j);
 526                         min_loaded = j;
 527                 }
 528         }
 529
 530         cpus_and(allowed_mask, cpu_online_map, irq_affinity[selected_irq]);
 531         target_cpu_mask = cpumask_of_cpu(min_loaded);
 532         cpus_and(tmp, target_cpu_mask, allowed_mask);
 533
 534         if (!cpus_empty(tmp)) {
 535
 536                 Dprintk("irq = %d moved to cpu = %d\n",
 537                                 selected_irq, min_loaded);
 538                 /* mark for change destination */
 539                 set_pending_irq(selected_irq, cpumask_of_cpu(min_loaded));
 540
 541                 /* Since we made a change, come back sooner to
 542                  * check for more variation.
 543                  */
 544                 balanced_irq_interval = max((long)MIN_BALANCED_IRQ_INTERVAL,
 545                         balanced_irq_interval - BALANCED_IRQ_LESS_DELTA);
 546                 return;
 547         }
 548         goto tryanotherirq;
 549
 550 not_worth_the_effort:
 551         /*
 552          * if we did not find an IRQ to move, then adjust the time interval
 553          * upward
 554          */
 555         balanced_irq_interval = min((long)MAX_BALANCED_IRQ_INTERVAL,
 556                 balanced_irq_interval + BALANCED_IRQ_MORE_DELTA);
 557         Dprintk("IRQ worth rotating not found\n");
 558         return;
 559 }
 560
 561 static int balanced_irq(void *unused)
 562 {
 563         int i;
 564         unsigned long prev_balance_time = jiffies;
 565         long time_remaining = balanced_irq_interval;
 566
 567         daemonize("kirqd");
 568
 569         /* push everything to CPU 0 to give us a starting point.  */
 570         for (i = 0 ; i < NR_IRQS ; i++) {
 571                 pending_irq_cpumask[i] = cpumask_of_cpu(0);
 572                 set_pending_irq(i, cpumask_of_cpu(0));
 573         }
 574
 575         for ( ; ; ) {
 576                 time_remaining = schedule_timeout_interruptible(time_remaining);
 577                 try_to_freeze();
 578                 if (time_after(jiffies,
 579                                 prev_balance_time+balanced_irq_interval)) {
 580                         preempt_disable();
 581                         do_irq_balance();
 582                         prev_balance_time = jiffies;
 583                         time_remaining = balanced_irq_interval;
 584                         preempt_enable();
 585                 }
 586         }
 587         return 0;
 588 }
 589
 590 static int __init balanced_irq_init(void)
 591 {
 592         int i;
 593         struct cpuinfo_x86 *c;
 594         cpumask_t tmp;
 595
 596         cpus_shift_right(tmp, cpu_online_map, 2);
 597         c = &boot_cpu_data;
 598         /* When not overwritten by the command line ask subarchitecture. */
 599         if (irqbalance_disabled == IRQBALANCE_CHECK_ARCH)
 600                 irqbalance_disabled = NO_BALANCE_IRQ;
 601         if (irqbalance_disabled)
 602                 return 0;
 603
 604          /* disable irqbalance completely if there is only one processor online */
 605         if (num_online_cpus() < 2) {
 606                 irqbalance_disabled = 1;
 607                 return 0;
 608         }
 609         /*
 610          * Enable physical balance only if more than 1 physical processor
 611          * is present
 612          */
 613         if (smp_num_siblings > 1 && !cpus_empty(tmp))
 614                 physical_balance = 1;
 615
 616         for (i = 0; i < NR_CPUS; i++) {
 617                 if (!cpu_online(i))
 618                         continue;
 619                 irq_cpu_data[i].irq_delta = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 620                 irq_cpu_data[i].last_irq = kmalloc(sizeof(unsigned long) * NR_IRQS, GFP_KERNEL);
 621                 if (irq_cpu_data[i].irq_delta == NULL || irq_cpu_data[i].last_irq == NULL) {
 622                         printk(KERN_ERR "balanced_irq_init: out of memory");
 623                         goto failed;
 624                 }
 625                 memset(irq_cpu_data[i].irq_delta,0,sizeof(unsigned long) * NR_IRQS);
 626                 memset(irq_cpu_data[i].last_irq,0,sizeof(unsigned long) * NR_IRQS);
 627         }
 628
 629         printk(KERN_INFO "Starting balanced_irq\n");
 630         if (kernel_thread(balanced_irq, NULL, CLONE_KERNEL) >= 0)
 631                 return 0;
 632         else
 633                 printk(KERN_ERR "balanced_irq_init: failed to spawn balanced_irq");
 634 failed:
 635         for (i = 0; i < NR_CPUS; i++) {
 636                 kfree(irq_cpu_data[i].irq_delta);
 637                 kfree(irq_cpu_data[i].last_irq);
 638         }
 639         return 0;
 640 }
 641
 642 int __init irqbalance_disable(char *str)
 643 {
 644         irqbalance_disabled = 1;
 645         return 0;
 646 }
 647
 648 __setup("noirqbalance", irqbalance_disable);
 649
 650 late_initcall(balanced_irq_init);
 651 #endif /* CONFIG_IRQBALANCE */
 652 #endif /* CONFIG_SMP */
 653
 654 #ifndef CONFIG_SMP
 655 void fastcall send_IPI_self(int vector)
 656 {
 657         unsigned int cfg;
 658
 659         /*
 660          * Wait for idle.
 661          */
 662         apic_wait_icr_idle();
 663         cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
 664         /*
 665          * Send the IPI. The write to APIC_ICR fires this off.
 666          */
 667         apic_write_around(APIC_ICR, cfg);
 668 }
 669 #endif /* !CONFIG_SMP */
 670
 671
 672 /*
 673  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 674  * specific CPU-side IRQs.
 675  */
 676
 677 #define MAX_PIRQS 8
 678 static int pirq_entries [MAX_PIRQS];
 679 static int pirqs_enabled;
 680 int skip_ioapic_setup;
 681
 682 static int __init ioapic_setup(char *str)
 683 {
 684         skip_ioapic_setup = 1;
 685         return 1;
 686 }
 687
 688 __setup("noapic", ioapic_setup);
 689
 690 static int __init ioapic_pirq_setup(char *str)
 691 {
 692         int i, max;
 693         int ints[MAX_PIRQS+1];
 694
 695         get_options(str, ARRAY_SIZE(ints), ints);
 696
 697         for (i = 0; i < MAX_PIRQS; i++)
 698                 pirq_entries[i] = -1;
 699
 700         pirqs_enabled = 1;
 701         apic_printk(APIC_VERBOSE, KERN_INFO
 702                         "PIRQ redirection, working around broken MP-BIOS.\n");
 703         max = MAX_PIRQS;
 704         if (ints[0] < MAX_PIRQS)
 705                 max = ints[0];
 706
 707         for (i = 0; i < max; i++) {
 708                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 709                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 710                 /*
 711                  * PIRQs are mapped upside down, usually.
 712                  */
 713                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 714         }
 715         return 1;
 716 }
 717
 718 __setup("pirq=", ioapic_pirq_setup);
 719
 720 /*
 721  * Find the IRQ entry number of a certain pin.
 722  */
 723 static int find_irq_entry(int apic, int pin, int type)
 724 {
 725         int i;
 726
 727         for (i = 0; i < mp_irq_entries; i++)
 728                 if (mp_irqs[i].mpc_irqtype == type &&
 729                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 730                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 731                     mp_irqs[i].mpc_dstirq == pin)
 732                         return i;
 733
 734         return -1;
 735 }
 736
 737 /*
 738  * Find the pin to which IRQ[irq] (ISA) is connected
 739  */
 740 static int find_isa_irq_pin(int irq, int type)
 741 {
 742         int i;
 743
 744         for (i = 0; i < mp_irq_entries; i++) {
 745                 int lbus = mp_irqs[i].mpc_srcbus;
 746
 747                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 748                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 749                      mp_bus_id_to_type[lbus] == MP_BUS_MCA ||
 750                      mp_bus_id_to_type[lbus] == MP_BUS_NEC98
 751                     ) &&
 752                     (mp_irqs[i].mpc_irqtype == type) &&
 753                     (mp_irqs[i].mpc_srcbusirq == irq))
 754
 755                         return mp_irqs[i].mpc_dstirq;
 756         }
 757         return -1;
 758 }
 759
 760 /*
 761  * Find a specific PCI IRQ entry.
 762  * Not an __init, possibly needed by modules
 763  */
 764 static int pin_2_irq(int idx, int apic, int pin);
 765
 766 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 767 {
 768         int apic, i, best_guess = -1;
 769
 770         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, "
 771                 "slot:%d, pin:%d.\n", bus, slot, pin);
 772         if (mp_bus_id_to_pci_bus[bus] == -1) {
 773                 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 774                 return -1;
 775         }
 776         for (i = 0; i < mp_irq_entries; i++) {
 777                 int lbus = mp_irqs[i].mpc_srcbus;
 778
 779                 for (apic = 0; apic < nr_ioapics; apic++)
 780                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 781                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 782                                 break;
 783
 784                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 785                     !mp_irqs[i].mpc_irqtype &&
 786                     (bus == lbus) &&
 787                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 788                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 789
 790                         if (!(apic || IO_APIC_IRQ(irq)))
 791                                 continue;
 792
 793                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 794                                 return irq;
 795                         /*
 796                          * Use the first all-but-pin matching entry as a
 797                          * best-guess fuzzy result for broken mptables.
 798                          */
 799                         if (best_guess < 0)
 800                                 best_guess = irq;
 801                 }
 802         }
 803         return best_guess;
 804 }
 805 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
 806
 807 /*
 808  * This function currently is only a helper for the i386 smp boot process where
 809  * we need to reprogram the ioredtbls to cater for the cpus which have come online
 810  * so mask in all cases should simply be TARGET_CPUS
 811  */
 812 #ifdef CONFIG_SMP
 813 void __init setup_ioapic_dest(void)
 814 {
 815         int pin, ioapic, irq, irq_entry;
 816
 817         if (skip_ioapic_setup == 1)
 818                 return;
 819
 820         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
 821                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
 822                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
 823                         if (irq_entry == -1)
 824                                 continue;
 825                         irq = pin_2_irq(irq_entry, ioapic, pin);
 826                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
 827                 }
 828
 829         }
 830 }
 831 #endif
 832
 833 /*
 834  * EISA Edge/Level control register, ELCR
 835  */
 836 static int EISA_ELCR(unsigned int irq)
 837 {
 838         if (irq < 16) {
 839                 unsigned int port = 0x4d0 + (irq >> 3);
 840                 return (inb(port) >> (irq & 7)) & 1;
 841         }
 842         apic_printk(APIC_VERBOSE, KERN_INFO
 843                         "Broken MPtable reports ISA irq %d\n", irq);
 844         return 0;
 845 }
 846
 847 /* EISA interrupts are always polarity zero and can be edge or level
 848  * trigger depending on the ELCR value.  If an interrupt is listed as
 849  * EISA conforming in the MP table, that means its trigger type must
 850  * be read in from the ELCR */
 851
 852 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 853 #define default_EISA_polarity(idx)      (0)
 854
 855 /* ISA interrupts are always polarity zero edge triggered,
 856  * when listed as conforming in the MP table. */
 857
 858 #define default_ISA_trigger(idx)        (0)
 859 #define default_ISA_polarity(idx)       (0)
 860
 861 /* PCI interrupts are always polarity one level triggered,
 862  * when listed as conforming in the MP table. */
 863
 864 #define default_PCI_trigger(idx)        (1)
 865 #define default_PCI_polarity(idx)       (1)
 866
 867 /* MCA interrupts are always polarity zero level triggered,
 868  * when listed as conforming in the MP table. */
 869
 870 #define default_MCA_trigger(idx)        (1)
 871 #define default_MCA_polarity(idx)       (0)
 872
 873 /* NEC98 interrupts are always polarity zero edge triggered,
 874  * when listed as conforming in the MP table. */
 875
 876 #define default_NEC98_trigger(idx)     (0)
 877 #define default_NEC98_polarity(idx)    (0)
 878
 879 static int __init MPBIOS_polarity(int idx)
 880 {
 881         int bus = mp_irqs[idx].mpc_srcbus;
 882         int polarity;
 883
 884         /*
 885          * Determine IRQ line polarity (high active or low active):
 886          */
 887         switch (mp_irqs[idx].mpc_irqflag & 3)
 888         {
 889                 case 0: /* conforms, ie. bus-type dependent polarity */
 890                 {
 891                         switch (mp_bus_id_to_type[bus])
 892                         {
 893                                 case MP_BUS_ISA: /* ISA pin */
 894                                 {
 895                                         polarity = default_ISA_polarity(idx);
 896                                         break;
 897                                 }
 898                                 case MP_BUS_EISA: /* EISA pin */
 899                                 {
 900                                         polarity = default_EISA_polarity(idx);
 901                                         break;
 902                                 }
 903                                 case MP_BUS_PCI: /* PCI pin */
 904                                 {
 905                                         polarity = default_PCI_polarity(idx);
 906                                         break;
 907                                 }
 908                                 case MP_BUS_MCA: /* MCA pin */
 909                                 {
 910                                         polarity = default_MCA_polarity(idx);
 911                                         break;
 912                                 }
 913                                 case MP_BUS_NEC98: /* NEC 98 pin */
 914                                 {
 915                                         polarity = default_NEC98_polarity(idx);
 916                                         break;
 917                                 }
 918                                 default:
 919                                 {
 920                                         printk(KERN_WARNING "broken BIOS!!\n");
 921                                         polarity = 1;
 922                                         break;
 923                                 }
 924                         }
 925                         break;
 926                 }
 927                 case 1: /* high active */
 928                 {
 929                         polarity = 0;
 930                         break;
 931                 }
 932                 case 2: /* reserved */
 933                 {
 934                         printk(KERN_WARNING "broken BIOS!!\n");
 935                         polarity = 1;
 936                         break;
 937                 }
 938                 case 3: /* low active */
 939                 {
 940                         polarity = 1;
 941                         break;
 942                 }
 943                 default: /* invalid */
 944                 {
 945                         printk(KERN_WARNING "broken BIOS!!\n");
 946                         polarity = 1;
 947                         break;
 948                 }
 949         }
 950         return polarity;
 951 }
 952
 953 static int MPBIOS_trigger(int idx)
 954 {
 955         int bus = mp_irqs[idx].mpc_srcbus;
 956         int trigger;
 957
 958         /*
 959          * Determine IRQ trigger mode (edge or level sensitive):
 960          */
 961         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 962         {
 963                 case 0: /* conforms, ie. bus-type dependent */
 964                 {
 965                         switch (mp_bus_id_to_type[bus])
 966                         {
 967                                 case MP_BUS_ISA: /* ISA pin */
 968                                 {
 969                                         trigger = default_ISA_trigger(idx);
 970                                         break;
 971                                 }
 972                                 case MP_BUS_EISA: /* EISA pin */
 973                                 {
 974                                         trigger = default_EISA_trigger(idx);
 975                                         break;
 976                                 }
 977                                 case MP_BUS_PCI: /* PCI pin */
 978                                 {
 979                                         trigger = default_PCI_trigger(idx);
 980                                         break;
 981                                 }
 982                                 case MP_BUS_MCA: /* MCA pin */
 983                                 {
 984                                         trigger = default_MCA_trigger(idx);
 985                                         break;
 986                                 }
 987                                 case MP_BUS_NEC98: /* NEC 98 pin */
 988                                 {
 989                                         trigger = default_NEC98_trigger(idx);
 990                                         break;
 991                                 }
 992                                 default:
 993                                 {
 994                                         printk(KERN_WARNING "broken BIOS!!\n");
 995                                         trigger = 1;
 996                                         break;
 997                                 }
 998                         }
 999                         break;
1000                 }
1001                 case 1: /* edge */
1002                 {
1003                         trigger = 0;
1004                         break;
1005                 }
1006                 case 2: /* reserved */
1007                 {
1008                         printk(KERN_WARNING "broken BIOS!!\n");
1009                         trigger = 1;
1010                         break;
1011                 }
1012                 case 3: /* level */
1013                 {
1014                         trigger = 1;
1015                         break;
1016                 }
1017                 default: /* invalid */
1018                 {
1019                         printk(KERN_WARNING "broken BIOS!!\n");
1020                         trigger = 0;
1021                         break;
1022                 }
1023         }
1024         return trigger;
1025 }
1026
1027 static inline int irq_polarity(int idx)
1028 {
1029         return MPBIOS_polarity(idx);
1030 }
1031
1032 static inline int irq_trigger(int idx)
1033 {
1034         return MPBIOS_trigger(idx);
1035 }
1036
1037 static int pin_2_irq(int idx, int apic, int pin)
1038 {
1039         int irq, i;
1040         int bus = mp_irqs[idx].mpc_srcbus;
1041
1042         /*
1043          * Debugging check, we are in big trouble if this message pops up!
1044          */
1045         if (mp_irqs[idx].mpc_dstirq != pin)
1046                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1047
1048         switch (mp_bus_id_to_type[bus])
1049         {
1050                 case MP_BUS_ISA: /* ISA pin */
1051                 case MP_BUS_EISA:
1052                 case MP_BUS_MCA:
1053                 case MP_BUS_NEC98:
1054                 {
1055                         irq = mp_irqs[idx].mpc_srcbusirq;
1056                         break;
1057                 }
1058                 case MP_BUS_PCI: /* PCI pin */
1059                 {
1060                         /*
1061                          * PCI IRQs are mapped in order
1062                          */
1063                         i = irq = 0;
1064                         while (i < apic)
1065                                 irq += nr_ioapic_registers[i++];
1066                         irq += pin;
1067
1068                         /*
1069                          * For MPS mode, so far only needed by ES7000 platform
1070                          */
1071                         if (ioapic_renumber_irq)
1072                                 irq = ioapic_renumber_irq(apic, irq);
1073
1074                         break;
1075                 }
1076                 default:
1077                 {
1078                         printk(KERN_ERR "unknown bus type %d.\n",bus);
1079                         irq = 0;
1080                         break;
1081                 }
1082         }
1083
1084         /*
1085          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1086          */
1087         if ((pin >= 16) && (pin <= 23)) {
1088                 if (pirq_entries[pin-16] != -1) {
1089                         if (!pirq_entries[pin-16]) {
1090                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1091                                                 "disabling PIRQ%d\n", pin-16);
1092                         } else {
1093                                 irq = pirq_entries[pin-16];
1094                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1095                                                 "using PIRQ%d -> IRQ %d\n",
1096                                                 pin-16, irq);
1097                         }
1098                 }
1099         }
1100         return irq;
1101 }
1102
1103 static inline int IO_APIC_irq_trigger(int irq)
1104 {
1105         int apic, idx, pin;
1106
1107         for (apic = 0; apic < nr_ioapics; apic++) {
1108                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1109                         idx = find_irq_entry(apic,pin,mp_INT);
1110                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
1111                                 return irq_trigger(idx);
1112                 }
1113         }
1114         /*
1115          * nonexistent IRQs are edge default
1116          */
1117         return 0;
1118 }
1119
1120 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
1121 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
1122
1123 int assign_irq_vector(int irq)
1124 {
1125         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
1126
1127         BUG_ON(irq >= NR_IRQ_VECTORS);
1128         if (irq != AUTO_ASSIGN && IO_APIC_VECTOR(irq) > 0)
1129                 return IO_APIC_VECTOR(irq);
1130 next:
1131         current_vector += 8;
1132         if (current_vector == SYSCALL_VECTOR)
1133                 goto next;
1134
1135         if (current_vector >= FIRST_SYSTEM_VECTOR) {
1136                 offset++;
1137                 if (!(offset%8))
1138                         return -ENOSPC;
1139                 current_vector = FIRST_DEVICE_VECTOR + offset;
1140         }
1141
1142         vector_irq[current_vector] = irq;
1143         if (irq != AUTO_ASSIGN)
1144                 IO_APIC_VECTOR(irq) = current_vector;
1145
1146         return current_vector;
1147 }
1148
1149 static struct hw_interrupt_type ioapic_level_type;
1150 static struct hw_interrupt_type ioapic_edge_type;
1151
1152 #define IOAPIC_AUTO     -1
1153 #define IOAPIC_EDGE     0
1154 #define IOAPIC_LEVEL    1
1155
1156 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
1157 {
1158         if (use_pci_vector() && !platform_legacy_irq(irq)) {
1159                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1160                                 trigger == IOAPIC_LEVEL)
1161                         irq_desc[vector].handler = &ioapic_level_type;
1162                 else
1163                         irq_desc[vector].handler = &ioapic_edge_type;
1164                 set_intr_gate(vector, interrupt[vector]);
1165         } else  {
1166                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1167                                 trigger == IOAPIC_LEVEL)
1168                         irq_desc[irq].handler = &ioapic_level_type;
1169                 else
1170                         irq_desc[irq].handler = &ioapic_edge_type;
1171                 set_intr_gate(vector, interrupt[irq]);
1172         }
1173 }
1174
1175 static void __init setup_IO_APIC_irqs(void)
1176 {
1177         struct IO_APIC_route_entry entry;
1178         int apic, pin, idx, irq, first_notcon = 1, vector;
1179         unsigned long flags;
1180
1181         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1182
1183         for (apic = 0; apic < nr_ioapics; apic++) {
1184         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1185
1186                 /*
1187                  * add it to the IO-APIC irq-routing table:
1188                  */
1189                 memset(&entry,0,sizeof(entry));
1190
1191                 entry.delivery_mode = INT_DELIVERY_MODE;
1192                 entry.dest_mode = INT_DEST_MODE;
1193                 entry.mask = 0;                         /* enable IRQ */
1194                 entry.dest.logical.logical_dest =
1195                                         cpu_mask_to_apicid(TARGET_CPUS);
1196
1197                 idx = find_irq_entry(apic,pin,mp_INT);
1198                 if (idx == -1) {
1199                         if (first_notcon) {
1200                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1201                                                 " IO-APIC (apicid-pin) %d-%d",
1202                                                 mp_ioapics[apic].mpc_apicid,
1203                                                 pin);
1204                                 first_notcon = 0;
1205                         } else
1206                                 apic_printk(APIC_VERBOSE, ", %d-%d",
1207                                         mp_ioapics[apic].mpc_apicid, pin);
1208                         continue;
1209                 }
1210
1211                 entry.trigger = irq_trigger(idx);
1212                 entry.polarity = irq_polarity(idx);
1213
1214                 if (irq_trigger(idx)) {
1215                         entry.trigger = 1;
1216                         entry.mask = 1;
1217                 }
1218
1219                 irq = pin_2_irq(idx, apic, pin);
1220                 /*
1221                  * skip adding the timer int on secondary nodes, which causes
1222                  * a small but painful rift in the time-space continuum
1223                  */
1224                 if (multi_timer_check(apic, irq))
1225                         continue;
1226                 else
1227                         add_pin_to_irq(irq, apic, pin);
1228
1229                 if (!apic && !IO_APIC_IRQ(irq))
1230                         continue;
1231
1232                 if (IO_APIC_IRQ(irq)) {
1233                         vector = assign_irq_vector(irq);
1234                         entry.vector = vector;
1235                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
1236
1237                         if (!apic && (irq < 16))
1238                                 disable_8259A_irq(irq);
1239                 }
1240                 spin_lock_irqsave(&ioapic_lock, flags);
1241                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
1242                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
1243                 set_native_irq_info(irq, TARGET_CPUS);
1244                 spin_unlock_irqrestore(&ioapic_lock, flags);
1245         }
1246         }
1247
1248         if (!first_notcon)
1249                 apic_printk(APIC_VERBOSE, " not connected.\n");
1250 }
1251
1252 /*
1253  * Set up the 8259A-master output pin:
1254  */
1255 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
1256 {
1257         struct IO_APIC_route_entry entry;
1258         unsigned long flags;
1259
1260         memset(&entry,0,sizeof(entry));
1261
1262         disable_8259A_irq(0);
1263
1264         /* mask LVT0 */
1265         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1266
1267         /*
1268          * We use logical delivery to get the timer IRQ
1269          * to the first CPU.
1270          */
1271         entry.dest_mode = INT_DEST_MODE;
1272         entry.mask = 0;                                 /* unmask IRQ now */
1273         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1274         entry.delivery_mode = INT_DELIVERY_MODE;
1275         entry.polarity = 0;
1276         entry.trigger = 0;
1277         entry.vector = vector;
1278
1279         /*
1280          * The timer IRQ doesn't have to know that behind the
1281          * scene we have a 8259A-master in AEOI mode ...
1282          */
1283         irq_desc[0].handler = &ioapic_edge_type;
1284
1285         /*
1286          * Add it to the IO-APIC irq-routing table:
1287          */
1288         spin_lock_irqsave(&ioapic_lock, flags);
1289         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1290         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1291         spin_unlock_irqrestore(&ioapic_lock, flags);
1292
1293         enable_8259A_irq(0);
1294 }
1295
1296 static inline void UNEXPECTED_IO_APIC(void)
1297 {
1298 }
1299
1300 void __init print_IO_APIC(void)
1301 {
1302         int apic, i;
1303         union IO_APIC_reg_00 reg_00;
1304         union IO_APIC_reg_01 reg_01;
1305         union IO_APIC_reg_02 reg_02;
1306         union IO_APIC_reg_03 reg_03;
1307         unsigned long flags;
1308
1309         if (apic_verbosity == APIC_QUIET)
1310                 return;
1311
1312         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1313         for (i = 0; i < nr_ioapics; i++)
1314                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1315                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
1316
1317         /*
1318          * We are a bit conservative about what we expect.  We have to
1319          * know about every hardware change ASAP.
1320          */
1321         printk(KERN_INFO "testing the IO APIC.......................\n");
1322
1323         for (apic = 0; apic < nr_ioapics; apic++) {
1324
1325         spin_lock_irqsave(&ioapic_lock, flags);
1326         reg_00.raw = io_apic_read(apic, 0);
1327         reg_01.raw = io_apic_read(apic, 1);
1328         if (reg_01.bits.version >= 0x10)
1329                 reg_02.raw = io_apic_read(apic, 2);
1330         if (reg_01.bits.version >= 0x20)
1331                 reg_03.raw = io_apic_read(apic, 3);
1332         spin_unlock_irqrestore(&ioapic_lock, flags);
1333
1334         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
1335         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1336         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1337         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1338         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1339         if (reg_00.bits.ID >= get_physical_broadcast())
1340                 UNEXPECTED_IO_APIC();
1341         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
1342                 UNEXPECTED_IO_APIC();
1343
1344         printk(KERN_DEBUG ".... register #01: %08X\n", reg_01.raw);
1345         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1346         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
1347                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
1348                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
1349                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
1350                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
1351                 (reg_01.bits.entries != 0x2E) &&
1352                 (reg_01.bits.entries != 0x3F)
1353         )
1354                 UNEXPECTED_IO_APIC();
1355
1356         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1357         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1358         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
1359                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
1360                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
1361                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
1362                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
1363         )
1364                 UNEXPECTED_IO_APIC();
1365         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
1366                 UNEXPECTED_IO_APIC();
1367
1368         /*
1369          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1370          * but the value of reg_02 is read as the previous read register
1371          * value, so ignore it if reg_02 == reg_01.
1372          */
1373         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1374                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1375                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1376                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
1377                         UNEXPECTED_IO_APIC();
1378         }
1379
1380         /*
1381          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1382          * or reg_03, but the value of reg_0[23] is read as the previous read
1383          * register value, so ignore it if reg_03 == reg_0[12].
1384          */
1385         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1386             reg_03.raw != reg_01.raw) {
1387                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1388                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1389                 if (reg_03.bits.__reserved_1)
1390                         UNEXPECTED_IO_APIC();
1391         }
1392
1393         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1394
1395         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
1396                           " Stat Dest Deli Vect:   \n");
1397
1398         for (i = 0; i <= reg_01.bits.entries; i++) {
1399                 struct IO_APIC_route_entry entry;
1400
1401                 spin_lock_irqsave(&ioapic_lock, flags);
1402                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
1403                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
1404                 spin_unlock_irqrestore(&ioapic_lock, flags);
1405
1406                 printk(KERN_DEBUG " %02x %03X %02X  ",
1407                         i,
1408                         entry.dest.logical.logical_dest,
1409                         entry.dest.physical.physical_dest
1410                 );
1411
1412                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1413                         entry.mask,
1414                         entry.trigger,
1415                         entry.irr,
1416                         entry.polarity,
1417                         entry.delivery_status,
1418                         entry.dest_mode,
1419                         entry.delivery_mode,
1420                         entry.vector
1421                 );
1422         }
1423         }
1424         if (use_pci_vector())
1425                 printk(KERN_INFO "Using vector-based indexing\n");
1426         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1427         for (i = 0; i < NR_IRQS; i++) {
1428                 struct irq_pin_list *entry = irq_2_pin + i;
1429                 if (entry->pin < 0)
1430                         continue;
1431                 if (use_pci_vector() && !platform_legacy_irq(i))
1432                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
1433                 else
1434                         printk(KERN_DEBUG "IRQ%d ", i);
1435                 for (;;) {
1436                         printk("-> %d:%d", entry->apic, entry->pin);
1437                         if (!entry->next)
1438                                 break;
1439                         entry = irq_2_pin + entry->next;
1440                 }
1441                 printk("\n");
1442         }
1443
1444         printk(KERN_INFO ".................................... done.\n");
1445
1446         return;
1447 }
1448
1449 #if 0
1450
1451 static void print_APIC_bitfield (int base)
1452 {
1453         unsigned int v;
1454         int i, j;
1455
1456         if (apic_verbosity == APIC_QUIET)
1457                 return;
1458
1459         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1460         for (i = 0; i < 8; i++) {
1461                 v = apic_read(base + i*0x10);
1462                 for (j = 0; j < 32; j++) {
1463                         if (v & (1<<j))
1464                                 printk("1");
1465                         else
1466                                 printk("0");
1467                 }
1468                 printk("\n");
1469         }
1470 }
1471
1472 void /*__init*/ print_local_APIC(void * dummy)
1473 {
1474         unsigned int v, ver, maxlvt;
1475
1476         if (apic_verbosity == APIC_QUIET)
1477                 return;
1478
1479         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1480                 smp_processor_id(), hard_smp_processor_id());
1481         v = apic_read(APIC_ID);
1482         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1483         v = apic_read(APIC_LVR);
1484         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1485         ver = GET_APIC_VERSION(v);
1486         maxlvt = get_maxlvt();
1487
1488         v = apic_read(APIC_TASKPRI);
1489         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1490
1491         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1492                 v = apic_read(APIC_ARBPRI);
1493                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1494                         v & APIC_ARBPRI_MASK);
1495                 v = apic_read(APIC_PROCPRI);
1496                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1497         }
1498
1499         v = apic_read(APIC_EOI);
1500         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1501         v = apic_read(APIC_RRR);
1502         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1503         v = apic_read(APIC_LDR);
1504         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1505         v = apic_read(APIC_DFR);
1506         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1507         v = apic_read(APIC_SPIV);
1508         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1509
1510         printk(KERN_DEBUG "... APIC ISR field:\n");
1511         print_APIC_bitfield(APIC_ISR);
1512         printk(KERN_DEBUG "... APIC TMR field:\n");
1513         print_APIC_bitfield(APIC_TMR);
1514         printk(KERN_DEBUG "... APIC IRR field:\n");
1515         print_APIC_bitfield(APIC_IRR);
1516
1517         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1518                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1519                         apic_write(APIC_ESR, 0);
1520                 v = apic_read(APIC_ESR);
1521                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1522         }
1523
1524         v = apic_read(APIC_ICR);
1525         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1526         v = apic_read(APIC_ICR2);
1527         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1528
1529         v = apic_read(APIC_LVTT);
1530         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1531
1532         if (maxlvt > 3) {                       /* PC is LVT#4. */
1533                 v = apic_read(APIC_LVTPC);
1534                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1535         }
1536         v = apic_read(APIC_LVT0);
1537         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1538         v = apic_read(APIC_LVT1);
1539         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1540
1541         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1542                 v = apic_read(APIC_LVTERR);
1543                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1544         }
1545
1546         v = apic_read(APIC_TMICT);
1547         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1548         v = apic_read(APIC_TMCCT);
1549         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1550         v = apic_read(APIC_TDCR);
1551         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1552         printk("\n");
1553 }
1554
1555 void print_all_local_APICs (void)
1556 {
1557         on_each_cpu(print_local_APIC, NULL, 1, 1);
1558 }
1559
1560 void /*__init*/ print_PIC(void)
1561 {
1562         unsigned int v;
1563         unsigned long flags;
1564
1565         if (apic_verbosity == APIC_QUIET)
1566                 return;
1567
1568         printk(KERN_DEBUG "\nprinting PIC contents\n");
1569
1570         spin_lock_irqsave(&i8259A_lock, flags);
1571
1572         v = inb(0xa1) << 8 | inb(0x21);
1573         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1574
1575         v = inb(0xa0) << 8 | inb(0x20);
1576         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1577
1578         outb(0x0b,0xa0);
1579         outb(0x0b,0x20);
1580         v = inb(0xa0) << 8 | inb(0x20);
1581         outb(0x0a,0xa0);
1582         outb(0x0a,0x20);
1583
1584         spin_unlock_irqrestore(&i8259A_lock, flags);
1585
1586         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1587
1588         v = inb(0x4d1) << 8 | inb(0x4d0);
1589         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1590 }
1591
1592 #endif  /*  0  */
1593
1594 static void __init enable_IO_APIC(void)
1595 {
1596         union IO_APIC_reg_01 reg_01;
1597         int i;
1598         unsigned long flags;
1599
1600         for (i = 0; i < PIN_MAP_SIZE; i++) {
1601                 irq_2_pin[i].pin = -1;
1602                 irq_2_pin[i].next = 0;
1603         }
1604         if (!pirqs_enabled)
1605                 for (i = 0; i < MAX_PIRQS; i++)
1606                         pirq_entries[i] = -1;
1607
1608         /*
1609          * The number of IO-APIC IRQ registers (== #pins):
1610          */
1611         for (i = 0; i < nr_ioapics; i++) {
1612                 spin_lock_irqsave(&ioapic_lock, flags);
1613                 reg_01.raw = io_apic_read(i, 1);
1614                 spin_unlock_irqrestore(&ioapic_lock, flags);
1615                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1616         }
1617
1618         /*
1619          * Do not trust the IO-APIC being empty at bootup
1620          */
1621         clear_IO_APIC();
1622 }
1623
1624 /*
1625  * Not an __init, needed by the reboot code
1626  */
1627 void disable_IO_APIC(void)
1628 {
1629         int pin;
1630         /*
1631          * Clear the IO-APIC before rebooting:
1632          */
1633         clear_IO_APIC();
1634
1635         /*
1636          * If the i8259 is routed through an IOAPIC
1637          * Put that IOAPIC in virtual wire mode
1638          * so legacy interrupts can be delivered.
1639          */
1640         pin = find_isa_irq_pin(0, mp_ExtINT);
1641         if (pin != -1) {
1642                 struct IO_APIC_route_entry entry;
1643                 unsigned long flags;
1644
1645                 memset(&entry, 0, sizeof(entry));
1646                 entry.mask            = 0; /* Enabled */
1647                 entry.trigger         = 0; /* Edge */
1648                 entry.irr             = 0;
1649                 entry.polarity        = 0; /* High */
1650                 entry.delivery_status = 0;
1651                 entry.dest_mode       = 0; /* Physical */
1652                 entry.delivery_mode   = 7; /* ExtInt */
1653                 entry.vector          = 0;
1654                 entry.dest.physical.physical_dest = 0;
1655
1656
1657                 /*
1658                  * Add it to the IO-APIC irq-routing table:
1659                  */
1660                 spin_lock_irqsave(&ioapic_lock, flags);
1661                 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1662                 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1663                 spin_unlock_irqrestore(&ioapic_lock, flags);
1664         }
1665         disconnect_bsp_APIC(pin != -1);
1666 }
1667
1668 /*
1669  * function to set the IO-APIC physical IDs based on the
1670  * values stored in the MPC table.
1671  *
1672  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1673  */
1674
1675 #ifndef CONFIG_X86_NUMAQ
1676 static void __init setup_ioapic_ids_from_mpc(void)
1677 {
1678         union IO_APIC_reg_00 reg_00;
1679         physid_mask_t phys_id_present_map;
1680         int apic;
1681         int i;
1682         unsigned char old_id;
1683         unsigned long flags;
1684
1685         /*
1686          * Don't check I/O APIC IDs for xAPIC systems.  They have
1687          * no meaning without the serial APIC bus.
1688          */
1689         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
1690                 return;
1691         /*
1692          * This is broken; anything with a real cpu count has to
1693          * circumvent this idiocy regardless.
1694          */
1695         phys_id_present_map = ioapic_phys_id_map(phys_cpu_present_map);
1696
1697         /*
1698          * Set the IOAPIC ID to the value stored in the MPC table.
1699          */
1700         for (apic = 0; apic < nr_ioapics; apic++) {
1701
1702                 /* Read the register 0 value */
1703                 spin_lock_irqsave(&ioapic_lock, flags);
1704                 reg_00.raw = io_apic_read(apic, 0);
1705                 spin_unlock_irqrestore(&ioapic_lock, flags);
1706
1707                 old_id = mp_ioapics[apic].mpc_apicid;
1708
1709                 if (mp_ioapics[apic].mpc_apicid >= get_physical_broadcast()) {
1710                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1711                                 apic, mp_ioapics[apic].mpc_apicid);
1712                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1713                                 reg_00.bits.ID);
1714                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1715                 }
1716
1717                 /*
1718                  * Sanity check, is the ID really free? Every APIC in a
1719                  * system must have a unique ID or we get lots of nice
1720                  * 'stuck on smp_invalidate_needed IPI wait' messages.
1721                  */
1722                 if (check_apicid_used(phys_id_present_map,
1723                                         mp_ioapics[apic].mpc_apicid)) {
1724                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1725                                 apic, mp_ioapics[apic].mpc_apicid);
1726                         for (i = 0; i < get_physical_broadcast(); i++)
1727                                 if (!physid_isset(i, phys_id_present_map))
1728                                         break;
1729                         if (i >= get_physical_broadcast())
1730                                 panic("Max APIC ID exceeded!\n");
1731                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1732                                 i);
1733                         physid_set(i, phys_id_present_map);
1734                         mp_ioapics[apic].mpc_apicid = i;
1735                 } else {
1736                         physid_mask_t tmp;
1737                         tmp = apicid_to_cpu_present(mp_ioapics[apic].mpc_apicid);
1738                         apic_printk(APIC_VERBOSE, "Setting %d in the "
1739                                         "phys_id_present_map\n",
1740                                         mp_ioapics[apic].mpc_apicid);
1741                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
1742                 }
1743
1744
1745                 /*
1746                  * We need to adjust the IRQ routing table
1747                  * if the ID changed.
1748                  */
1749                 if (old_id != mp_ioapics[apic].mpc_apicid)
1750                         for (i = 0; i < mp_irq_entries; i++)
1751                                 if (mp_irqs[i].mpc_dstapic == old_id)
1752                                         mp_irqs[i].mpc_dstapic
1753                                                 = mp_ioapics[apic].mpc_apicid;
1754
1755                 /*
1756                  * Read the right value from the MPC table and
1757                  * write it into the ID register.
1758                  */
1759                 apic_printk(APIC_VERBOSE, KERN_INFO
1760                         "...changing IO-APIC physical APIC ID to %d ...",
1761                         mp_ioapics[apic].mpc_apicid);
1762
1763                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1764                 spin_lock_irqsave(&ioapic_lock, flags);
1765                 io_apic_write(apic, 0, reg_00.raw);
1766                 spin_unlock_irqrestore(&ioapic_lock, flags);
1767
1768                 /*
1769                  * Sanity check
1770                  */
1771                 spin_lock_irqsave(&ioapic_lock, flags);
1772                 reg_00.raw = io_apic_read(apic, 0);
1773                 spin_unlock_irqrestore(&ioapic_lock, flags);
1774                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1775                         printk("could not set ID!\n");
1776                 else
1777                         apic_printk(APIC_VERBOSE, " ok.\n");
1778         }
1779 }
1780 #else
1781 static void __init setup_ioapic_ids_from_mpc(void) { }
1782 #endif
1783
1784 /*
1785  * There is a nasty bug in some older SMP boards, their mptable lies
1786  * about the timer IRQ. We do the following to work around the situation:
1787  *
1788  *      - timer IRQ defaults to IO-APIC IRQ
1789  *      - if this function detects that timer IRQs are defunct, then we fall
1790  *        back to ISA timer IRQs
1791  */
1792 static int __init timer_irq_works(void)
1793 {
1794         unsigned long t1 = jiffies;
1795
1796         local_irq_enable();
1797         /* Let ten ticks pass... */
1798         mdelay((10 * 1000) / HZ);
1799
1800         /*
1801          * Expect a few ticks at least, to be sure some possible
1802          * glue logic does not lock up after one or two first
1803          * ticks in a non-ExtINT mode.  Also the local APIC
1804          * might have cached one ExtINT interrupt.  Finally, at
1805          * least one tick may be lost due to delays.
1806          */
1807         if (jiffies - t1 > 4)
1808                 return 1;
1809
1810         return 0;
1811 }
1812
1813 /*
1814  * In the SMP+IOAPIC case it might happen that there are an unspecified
1815  * number of pending IRQ events unhandled. These cases are very rare,
1816  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1817  * better to do it this way as thus we do not have to be aware of
1818  * 'pending' interrupts in the IRQ path, except at this point.
1819  */
1820 /*
1821  * Edge triggered needs to resend any interrupt
1822  * that was delayed but this is now handled in the device
1823  * independent code.
1824  */
1825
1826 /*
1827  * Starting up a edge-triggered IO-APIC interrupt is
1828  * nasty - we need to make sure that we get the edge.
1829  * If it is already asserted for some reason, we need
1830  * return 1 to indicate that is was pending.
1831  *
1832  * This is not complete - we should be able to fake
1833  * an edge even if it isn't on the 8259A...
1834  */
1835 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1836 {
1837         int was_pending = 0;
1838         unsigned long flags;
1839
1840         spin_lock_irqsave(&ioapic_lock, flags);
1841         if (irq < 16) {
1842                 disable_8259A_irq(irq);
1843                 if (i8259A_irq_pending(irq))
1844                         was_pending = 1;
1845         }
1846         __unmask_IO_APIC_irq(irq);
1847         spin_unlock_irqrestore(&ioapic_lock, flags);
1848
1849         return was_pending;
1850 }
1851
1852 /*
1853  * Once we have recorded IRQ_PENDING already, we can mask the
1854  * interrupt for real. This prevents IRQ storms from unhandled
1855  * devices.
1856  */
1857 static void ack_edge_ioapic_irq(unsigned int irq)
1858 {
1859         move_irq(irq);
1860         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1861                                         == (IRQ_PENDING | IRQ_DISABLED))
1862                 mask_IO_APIC_irq(irq);
1863         ack_APIC_irq();
1864 }
1865
1866 /*
1867  * Level triggered interrupts can just be masked,
1868  * and shutting down and starting up the interrupt
1869  * is the same as enabling and disabling them -- except
1870  * with a startup need to return a "was pending" value.
1871  *
1872  * Level triggered interrupts are special because we
1873  * do not touch any IO-APIC register while handling
1874  * them. We ack the APIC in the end-IRQ handler, not
1875  * in the start-IRQ-handler. Protection against reentrance
1876  * from the same interrupt is still provided, both by the
1877  * generic IRQ layer and by the fact that an unacked local
1878  * APIC does not accept IRQs.
1879  */
1880 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1881 {
1882         unmask_IO_APIC_irq(irq);
1883
1884         return 0; /* don't check for pending */
1885 }
1886
1887 static void end_level_ioapic_irq (unsigned int irq)
1888 {
1889         unsigned long v;
1890         int i;
1891
1892         move_irq(irq);
1893 /*
1894  * It appears there is an erratum which affects at least version 0x11
1895  * of I/O APIC (that's the 82093AA and cores integrated into various
1896  * chipsets).  Under certain conditions a level-triggered interrupt is
1897  * erroneously delivered as edge-triggered one but the respective IRR
1898  * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1899  * message but it will never arrive and further interrupts are blocked
1900  * from the source.  The exact reason is so far unknown, but the
1901  * phenomenon was observed when two consecutive interrupt requests
1902  * from a given source get delivered to the same CPU and the source is
1903  * temporarily disabled in between.
1904  *
1905  * A workaround is to simulate an EOI message manually.  We achieve it
1906  * by setting the trigger mode to edge and then to level when the edge
1907  * trigger mode gets detected in the TMR of a local APIC for a
1908  * level-triggered interrupt.  We mask the source for the time of the
1909  * operation to prevent an edge-triggered interrupt escaping meanwhile.
1910  * The idea is from Manfred Spraul.  --macro
1911  */
1912         i = IO_APIC_VECTOR(irq);
1913
1914         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1915
1916         ack_APIC_irq();
1917
1918         if (!(v & (1 << (i & 0x1f)))) {
1919                 atomic_inc(&irq_mis_count);
1920                 spin_lock(&ioapic_lock);
1921                 __mask_and_edge_IO_APIC_irq(irq);
1922                 __unmask_and_level_IO_APIC_irq(irq);
1923                 spin_unlock(&ioapic_lock);
1924         }
1925 }
1926
1927 #ifdef CONFIG_PCI_MSI
1928 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1929 {
1930         int irq = vector_to_irq(vector);
1931
1932         return startup_edge_ioapic_irq(irq);
1933 }
1934
1935 static void ack_edge_ioapic_vector(unsigned int vector)
1936 {
1937         int irq = vector_to_irq(vector);
1938
1939         move_irq(vector);
1940         ack_edge_ioapic_irq(irq);
1941 }
1942
1943 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1944 {
1945         int irq = vector_to_irq(vector);
1946
1947         return startup_level_ioapic_irq (irq);
1948 }
1949
1950 static void end_level_ioapic_vector (unsigned int vector)
1951 {
1952         int irq = vector_to_irq(vector);
1953
1954         move_irq(vector);
1955         end_level_ioapic_irq(irq);
1956 }
1957
1958 static void mask_IO_APIC_vector (unsigned int vector)
1959 {
1960         int irq = vector_to_irq(vector);
1961
1962         mask_IO_APIC_irq(irq);
1963 }
1964
1965 static void unmask_IO_APIC_vector (unsigned int vector)
1966 {
1967         int irq = vector_to_irq(vector);
1968
1969         unmask_IO_APIC_irq(irq);
1970 }
1971
1972 #ifdef CONFIG_SMP
1973 static void set_ioapic_affinity_vector (unsigned int vector,
1974                                         cpumask_t cpu_mask)
1975 {
1976         int irq = vector_to_irq(vector);
1977
1978         set_native_irq_info(vector, cpu_mask);
1979         set_ioapic_affinity_irq(irq, cpu_mask);
1980 }
1981 #endif
1982 #endif
1983
1984 /*
1985  * Level and edge triggered IO-APIC interrupts need different handling,
1986  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1987  * handled with the level-triggered descriptor, but that one has slightly
1988  * more overhead. Level-triggered interrupts cannot be handled with the
1989  * edge-triggered handler, without risking IRQ storms and other ugly
1990  * races.
1991  */
1992 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1993         .typename       = "IO-APIC-edge",
1994         .startup        = startup_edge_ioapic,
1995         .shutdown       = shutdown_edge_ioapic,
1996         .enable         = enable_edge_ioapic,
1997         .disable        = disable_edge_ioapic,
1998         .ack            = ack_edge_ioapic,
1999         .end            = end_edge_ioapic,
2000 #ifdef CONFIG_SMP
2001         .set_affinity   = set_ioapic_affinity,
2002 #endif
2003 };
2004
2005 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
2006         .typename       = "IO-APIC-level",
2007         .startup        = startup_level_ioapic,
2008         .shutdown       = shutdown_level_ioapic,
2009         .enable         = enable_level_ioapic,
2010         .disable        = disable_level_ioapic,
2011         .ack            = mask_and_ack_level_ioapic,
2012         .end            = end_level_ioapic,
2013 #ifdef CONFIG_SMP
2014         .set_affinity   = set_ioapic_affinity,
2015 #endif
2016 };
2017
2018 static inline void init_IO_APIC_traps(void)
2019 {
2020         int irq;
2021
2022         /*
2023          * NOTE! The local APIC isn't very good at handling
2024          * multiple interrupts at the same interrupt level.
2025          * As the interrupt level is determined by taking the
2026          * vector number and shifting that right by 4, we
2027          * want to spread these out a bit so that they don't
2028          * all fall in the same interrupt level.
2029          *
2030          * Also, we've got to be careful not to trash gate
2031          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2032          */
2033         for (irq = 0; irq < NR_IRQS ; irq++) {
2034                 int tmp = irq;
2035                 if (use_pci_vector()) {
2036                         if (!platform_legacy_irq(tmp))
2037                                 if ((tmp = vector_to_irq(tmp)) == -1)
2038                                         continue;
2039                 }
2040                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
2041                         /*
2042                          * Hmm.. We don't have an entry for this,
2043                          * so default to an old-fashioned 8259
2044                          * interrupt if we can..
2045                          */
2046                         if (irq < 16)
2047                                 make_8259A_irq(irq);
2048                         else
2049                                 /* Strange. Oh, well.. */
2050                                 irq_desc[irq].handler = &no_irq_type;
2051                 }
2052         }
2053 }
2054
2055 static void enable_lapic_irq (unsigned int irq)
2056 {
2057         unsigned long v;
2058
2059         v = apic_read(APIC_LVT0);
2060         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
2061 }
2062
2063 static void disable_lapic_irq (unsigned int irq)
2064 {
2065         unsigned long v;
2066
2067         v = apic_read(APIC_LVT0);
2068         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
2069 }
2070
2071 static void ack_lapic_irq (unsigned int irq)
2072 {
2073         ack_APIC_irq();
2074 }
2075
2076 static void end_lapic_irq (unsigned int i) { /* nothing */ }
2077
2078 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
2079         .typename       = "local-APIC-edge",
2080         .startup        = NULL, /* startup_irq() not used for IRQ0 */
2081         .shutdown       = NULL, /* shutdown_irq() not used for IRQ0 */
2082         .enable         = enable_lapic_irq,
2083         .disable        = disable_lapic_irq,
2084         .ack            = ack_lapic_irq,
2085         .end            = end_lapic_irq
2086 };
2087
2088 static void setup_nmi (void)
2089 {
2090         /*
2091          * Dirty trick to enable the NMI watchdog ...
2092          * We put the 8259A master into AEOI mode and
2093          * unmask on all local APICs LVT0 as NMI.
2094          *
2095          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2096          * is from Maciej W. Rozycki - so we do not have to EOI from
2097          * the NMI handler or the timer interrupt.
2098          */
2099         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2100
2101         on_each_cpu(enable_NMI_through_LVT0, NULL, 1, 1);
2102
2103         apic_printk(APIC_VERBOSE, " done.\n");
2104 }
2105
2106 /*
2107  * This looks a bit hackish but it's about the only one way of sending
2108  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2109  * not support the ExtINT mode, unfortunately.  We need to send these
2110  * cycles as some i82489DX-based boards have glue logic that keeps the
2111  * 8259A interrupt line asserted until INTA.  --macro
2112  */
2113 static inline void unlock_ExtINT_logic(void)
2114 {
2115         int pin, i;
2116         struct IO_APIC_route_entry entry0, entry1;
2117         unsigned char save_control, save_freq_select;
2118         unsigned long flags;
2119
2120         pin = find_isa_irq_pin(8, mp_INT);
2121         if (pin == -1)
2122                 return;
2123
2124         spin_lock_irqsave(&ioapic_lock, flags);
2125         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
2126         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
2127         spin_unlock_irqrestore(&ioapic_lock, flags);
2128         clear_IO_APIC_pin(0, pin);
2129
2130         memset(&entry1, 0, sizeof(entry1));
2131
2132         entry1.dest_mode = 0;                   /* physical delivery */
2133         entry1.mask = 0;                        /* unmask IRQ now */
2134         entry1.dest.physical.physical_dest = hard_smp_processor_id();
2135         entry1.delivery_mode = dest_ExtINT;
2136         entry1.polarity = entry0.polarity;
2137         entry1.trigger = 0;
2138         entry1.vector = 0;
2139
2140         spin_lock_irqsave(&ioapic_lock, flags);
2141         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
2142         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
2143         spin_unlock_irqrestore(&ioapic_lock, flags);
2144
2145         save_control = CMOS_READ(RTC_CONTROL);
2146         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2147         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2148                    RTC_FREQ_SELECT);
2149         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2150
2151         i = 100;
2152         while (i-- > 0) {
2153                 mdelay(10);
2154                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2155                         i -= 10;
2156         }
2157
2158         CMOS_WRITE(save_control, RTC_CONTROL);
2159         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2160         clear_IO_APIC_pin(0, pin);
2161
2162         spin_lock_irqsave(&ioapic_lock, flags);
2163         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
2164         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
2165         spin_unlock_irqrestore(&ioapic_lock, flags);
2166 }
2167
2168 /*
2169  * This code may look a bit paranoid, but it's supposed to cooperate with
2170  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2171  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2172  * fanatically on his truly buggy board.
2173  */
2174 static inline void check_timer(void)
2175 {
2176         int pin1, pin2;
2177         int vector;
2178
2179         /*
2180          * get/set the timer IRQ vector:
2181          */
2182         disable_8259A_irq(0);
2183         vector = assign_irq_vector(0);
2184         set_intr_gate(vector, interrupt[0]);
2185
2186         /*
2187          * Subtle, code in do_timer_interrupt() expects an AEOI
2188          * mode for the 8259A whenever interrupts are routed
2189          * through I/O APICs.  Also IRQ0 has to be enabled in
2190          * the 8259A which implies the virtual wire has to be
2191          * disabled in the local APIC.
2192          */
2193         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2194         init_8259A(1);
2195         timer_ack = 1;
2196         enable_8259A_irq(0);
2197
2198         pin1 = find_isa_irq_pin(0, mp_INT);
2199         pin2 = find_isa_irq_pin(0, mp_ExtINT);
2200
2201         printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
2202
2203         if (pin1 != -1) {
2204                 /*
2205                  * Ok, does IRQ0 through the IOAPIC work?
2206                  */
2207                 unmask_IO_APIC_irq(0);
2208                 if (timer_irq_works()) {
2209                         if (nmi_watchdog == NMI_IO_APIC) {
2210                                 disable_8259A_irq(0);
2211                                 setup_nmi();
2212                                 enable_8259A_irq(0);
2213                         }
2214                         return;
2215                 }
2216                 clear_IO_APIC_pin(0, pin1);
2217                 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
2218         }
2219
2220         printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
2221         if (pin2 != -1) {
2222                 printk("\n..... (found pin %d) ...", pin2);
2223                 /*
2224                  * legacy devices should be connected to IO APIC #0
2225                  */
2226                 setup_ExtINT_IRQ0_pin(pin2, vector);
2227                 if (timer_irq_works()) {
2228                         printk("works.\n");
2229                         if (pin1 != -1)
2230                                 replace_pin_at_irq(0, 0, pin1, 0, pin2);
2231                         else
2232                                 add_pin_to_irq(0, 0, pin2);
2233                         if (nmi_watchdog == NMI_IO_APIC) {
2234                                 setup_nmi();
2235                         }
2236                         return;
2237                 }
2238                 /*
2239                  * Cleanup, just in case ...
2240                  */
2241                 clear_IO_APIC_pin(0, pin2);
2242         }
2243         printk(" failed.\n");
2244
2245         if (nmi_watchdog == NMI_IO_APIC) {
2246                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
2247                 nmi_watchdog = 0;
2248         }
2249
2250         printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
2251
2252         disable_8259A_irq(0);
2253         irq_desc[0].handler = &lapic_irq_type;
2254         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
2255         enable_8259A_irq(0);
2256
2257         if (timer_irq_works()) {
2258                 printk(" works.\n");
2259                 return;
2260         }
2261         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
2262         printk(" failed.\n");
2263
2264         printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
2265
2266         timer_ack = 0;
2267         init_8259A(0);
2268         make_8259A_irq(0);
2269         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
2270
2271         unlock_ExtINT_logic();
2272
2273         if (timer_irq_works()) {
2274                 printk(" works.\n");
2275                 return;
2276         }
2277         printk(" failed :(.\n");
2278         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2279                 "report.  Then try booting with the 'noapic' option");
2280 }
2281
2282 /*
2283  *
2284  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
2285  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
2286  *   Linux doesn't really care, as it's not actually used
2287  *   for any interrupt handling anyway.
2288  */
2289 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
2290
2291 void __init setup_IO_APIC(void)
2292 {
2293         enable_IO_APIC();
2294
2295         if (acpi_ioapic)
2296                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
2297         else
2298                 io_apic_irqs = ~PIC_IRQS;
2299
2300         printk("ENABLING IO-APIC IRQs\n");
2301
2302         /*
2303          * Set up IO-APIC IRQ routing.
2304          */
2305         if (!acpi_ioapic)
2306                 setup_ioapic_ids_from_mpc();
2307         sync_Arb_IDs();
2308         setup_IO_APIC_irqs();
2309         init_IO_APIC_traps();
2310         check_timer();
2311         if (!acpi_ioapic)
2312                 print_IO_APIC();
2313 }
2314
2315 /*
2316  *      Called after all the initialization is done. If we didnt find any
2317  *      APIC bugs then we can allow the modify fast path
2318  */
2319
2320 static int __init io_apic_bug_finalize(void)
2321 {
2322         if(sis_apic_bug == -1)
2323                 sis_apic_bug = 0;
2324         return 0;
2325 }
2326
2327 late_initcall(io_apic_bug_finalize);
2328
2329 struct sysfs_ioapic_data {
2330         struct sys_device dev;
2331         struct IO_APIC_route_entry entry[0];
2332 };
2333 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
2334
2335 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
2336 {
2337         struct IO_APIC_route_entry *entry;
2338         struct sysfs_ioapic_data *data;
2339         unsigned long flags;
2340         int i;
2341
2342         data = container_of(dev, struct sysfs_ioapic_data, dev);
2343         entry = data->entry;
2344         spin_lock_irqsave(&ioapic_lock, flags);
2345         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2346                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
2347                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
2348         }
2349         spin_unlock_irqrestore(&ioapic_lock, flags);
2350
2351         return 0;
2352 }
2353
2354 static int ioapic_resume(struct sys_device *dev)
2355 {
2356         struct IO_APIC_route_entry *entry;
2357         struct sysfs_ioapic_data *data;
2358         unsigned long flags;
2359         union IO_APIC_reg_00 reg_00;
2360         int i;
2361
2362         data = container_of(dev, struct sysfs_ioapic_data, dev);
2363         entry = data->entry;
2364
2365         spin_lock_irqsave(&ioapic_lock, flags);
2366         reg_00.raw = io_apic_read(dev->id, 0);
2367         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
2368                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
2369                 io_apic_write(dev->id, 0, reg_00.raw);
2370         }
2371         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
2372                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
2373                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
2374         }
2375         spin_unlock_irqrestore(&ioapic_lock, flags);
2376
2377         return 0;
2378 }
2379
2380 static struct sysdev_class ioapic_sysdev_class = {
2381         set_kset_name("ioapic"),
2382         .suspend = ioapic_suspend,
2383         .resume = ioapic_resume,
2384 };
2385
2386 static int __init ioapic_init_sysfs(void)
2387 {
2388         struct sys_device * dev;
2389         int i, size, error = 0;
2390
2391         error = sysdev_class_register(&ioapic_sysdev_class);
2392         if (error)
2393                 return error;
2394
2395         for (i = 0; i < nr_ioapics; i++ ) {
2396                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
2397                         * sizeof(struct IO_APIC_route_entry);
2398                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
2399                 if (!mp_ioapic_data[i]) {
2400                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2401                         continue;
2402                 }
2403                 memset(mp_ioapic_data[i], 0, size);
2404                 dev = &mp_ioapic_data[i]->dev;
2405                 dev->id = i;
2406                 dev->cls = &ioapic_sysdev_class;
2407                 error = sysdev_register(dev);
2408                 if (error) {
2409                         kfree(mp_ioapic_data[i]);
2410                         mp_ioapic_data[i] = NULL;
2411                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
2412                         continue;
2413                 }
2414         }
2415
2416         return 0;
2417 }
2418
2419 device_initcall(ioapic_init_sysfs);
2420
2421 /* --------------------------------------------------------------------------
2422                           ACPI-based IOAPIC Configuration
2423    -------------------------------------------------------------------------- */
2424
2425 #ifdef CONFIG_ACPI
2426
2427 int __init io_apic_get_unique_id (int ioapic, int apic_id)
2428 {
2429         union IO_APIC_reg_00 reg_00;
2430         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2431         physid_mask_t tmp;
2432         unsigned long flags;
2433         int i = 0;
2434
2435         /*
2436          * The P4 platform supports up to 256 APIC IDs on two separate APIC
2437          * buses (one for LAPICs, one for IOAPICs), where predecessors only
2438          * supports up to 16 on one shared APIC bus.
2439          *
2440          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2441          *      advantage of new APIC bus architecture.
2442          */
2443
2444         if (physids_empty(apic_id_map))
2445                 apic_id_map = ioapic_phys_id_map(phys_cpu_present_map);
2446
2447         spin_lock_irqsave(&ioapic_lock, flags);
2448         reg_00.raw = io_apic_read(ioapic, 0);
2449         spin_unlock_irqrestore(&ioapic_lock, flags);
2450
2451         if (apic_id >= get_physical_broadcast()) {
2452                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2453                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
2454                 apic_id = reg_00.bits.ID;
2455         }
2456
2457         /*
2458          * Every APIC in a system must have a unique ID or we get lots of nice
2459          * 'stuck on smp_invalidate_needed IPI wait' messages.
2460          */
2461         if (check_apicid_used(apic_id_map, apic_id)) {
2462
2463                 for (i = 0; i < get_physical_broadcast(); i++) {
2464                         if (!check_apicid_used(apic_id_map, i))
2465                                 break;
2466                 }
2467
2468                 if (i == get_physical_broadcast())
2469                         panic("Max apic_id exceeded!\n");
2470
2471                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2472                         "trying %d\n", ioapic, apic_id, i);
2473
2474                 apic_id = i;
2475         }
2476
2477         tmp = apicid_to_cpu_present(apic_id);
2478         physids_or(apic_id_map, apic_id_map, tmp);
2479
2480         if (reg_00.bits.ID != apic_id) {
2481                 reg_00.bits.ID = apic_id;
2482
2483                 spin_lock_irqsave(&ioapic_lock, flags);
2484                 io_apic_write(ioapic, 0, reg_00.raw);
2485                 reg_00.raw = io_apic_read(ioapic, 0);
2486                 spin_unlock_irqrestore(&ioapic_lock, flags);
2487
2488                 /* Sanity check */
2489                 if (reg_00.bits.ID != apic_id)
2490                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
2491         }
2492
2493         apic_printk(APIC_VERBOSE, KERN_INFO
2494                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2495
2496         return apic_id;
2497 }
2498
2499
2500 int __init io_apic_get_version (int ioapic)
2501 {
2502         union IO_APIC_reg_01    reg_01;
2503         unsigned long flags;
2504
2505         spin_lock_irqsave(&ioapic_lock, flags);
2506         reg_01.raw = io_apic_read(ioapic, 1);
2507         spin_unlock_irqrestore(&ioapic_lock, flags);
2508
2509         return reg_01.bits.version;
2510 }
2511
2512
2513 int __init io_apic_get_redir_entries (int ioapic)
2514 {
2515         union IO_APIC_reg_01    reg_01;
2516         unsigned long flags;
2517
2518         spin_lock_irqsave(&ioapic_lock, flags);
2519         reg_01.raw = io_apic_read(ioapic, 1);
2520         spin_unlock_irqrestore(&ioapic_lock, flags);
2521
2522         return reg_01.bits.entries;
2523 }
2524
2525
2526 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
2527 {
2528         struct IO_APIC_route_entry entry;
2529         unsigned long flags;
2530
2531         if (!IO_APIC_IRQ(irq)) {
2532                 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2533                         ioapic);
2534                 return -EINVAL;
2535         }
2536
2537         /*
2538          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
2539          * Note that we mask (disable) IRQs now -- these get enabled when the
2540          * corresponding device driver registers for this IRQ.
2541          */
2542
2543         memset(&entry,0,sizeof(entry));
2544
2545         entry.delivery_mode = INT_DELIVERY_MODE;
2546         entry.dest_mode = INT_DEST_MODE;
2547         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
2548         entry.trigger = edge_level;
2549         entry.polarity = active_high_low;
2550         entry.mask  = 1;
2551
2552         /*
2553          * IRQs < 16 are already in the irq_2_pin[] map
2554          */
2555         if (irq >= 16)
2556                 add_pin_to_irq(irq, ioapic, pin);
2557
2558         entry.vector = assign_irq_vector(irq);
2559
2560         apic_printk(APIC_DEBUG, KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry "
2561                 "(%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i)\n", ioapic,
2562                 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
2563                 edge_level, active_high_low);
2564
2565         ioapic_register_intr(irq, entry.vector, edge_level);
2566
2567         if (!ioapic && (irq < 16))
2568                 disable_8259A_irq(irq);
2569
2570         spin_lock_irqsave(&ioapic_lock, flags);
2571         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
2572         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
2573         set_native_irq_info(use_pci_vector() ? entry.vector : irq, TARGET_CPUS);
2574         spin_unlock_irqrestore(&ioapic_lock, flags);
2575
2576         return 0;
2577 }
2578
2579 #endif /* CONFIG_ACPI */