arch/i386/kernel/cpu/intel.c

   1 #include <linux/config.h>
   2 #include <linux/init.h>
   3 #include <linux/kernel.h>
   4
   5 #include <linux/string.h>
   6 #include <linux/bitops.h>
   7 #include <linux/smp.h>
   8 #include <linux/thread_info.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/msr.h>
  12 #include <asm/uaccess.h>
  13
  14 #include "cpu.h"
  15
  16 #ifdef CONFIG_X86_LOCAL_APIC
  17 #include <asm/mpspec.h>
  18 #include <asm/apic.h>
  19 #include <mach_apic.h>
  20 #endif
  21
  22 extern int trap_init_f00f_bug(void);
  23
  24 #ifdef CONFIG_X86_INTEL_USERCOPY
  25 /*
  26  * Alignment at which movsl is preferred for bulk memory copies.
  27  */
  28 struct movsl_mask movsl_mask __read_mostly;
  29 #endif
  30
  31 void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
  32 {
  33         if (c->x86_vendor != X86_VENDOR_INTEL)
  34                 return;
  35         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  36         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  37                 c->x86_cache_alignment = 128;
  38 }
  39
  40 /*
  41  *      Early probe support logic for ppro memory erratum #50
  42  *
  43  *      This is called before we do cpu ident work
  44  */
  45
  46 int __devinit ppro_with_ram_bug(void)
  47 {
  48         /* Uses data from early_cpu_detect now */
  49         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  50             boot_cpu_data.x86 == 6 &&
  51             boot_cpu_data.x86_model == 1 &&
  52             boot_cpu_data.x86_mask < 8) {
  53                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  54                 return 1;
  55         }
  56         return 0;
  57 }
  58
  59
  60 /*
  61  * P4 Xeon errata 037 workaround.
  62  * Hardware prefetcher may cause stale data to be loaded into the cache.
  63  */
  64 static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
  65 {
  66         unsigned long lo, hi;
  67
  68         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
  69                 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
  70                 if ((lo & (1<<9)) == 0) {
  71                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
  72                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
  73                         lo |= (1<<9);   /* Disable hw prefetching */
  74                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
  75                 }
  76         }
  77 }
  78
  79
  80 /*
  81  * find out the number of processor cores on the die
  82  */
  83 static int __devinit num_cpu_cores(struct cpuinfo_x86 *c)
  84 {
  85         unsigned int eax, ebx, ecx, edx;
  86
  87         if (c->cpuid_level < 4)
  88                 return 1;
  89
  90         /* Intel has a non-standard dependency on %ecx for this CPUID level. */
  91         cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
  92         if (eax & 0x1f)
  93                 return ((eax >> 26) + 1);
  94         else
  95                 return 1;
  96 }
  97
  98 static void __devinit init_intel(struct cpuinfo_x86 *c)
  99 {
 100         unsigned int l2 = 0;
 101         char *p = NULL;
 102
 103 #ifdef CONFIG_X86_F00F_BUG
 104         /*
 105          * All current models of Pentium and Pentium with MMX technology CPUs
 106          * have the F0 0F bug, which lets nonprivileged users lock up the system.
 107          * Note that the workaround only should be initialized once...
 108          */
 109         c->f00f_bug = 0;
 110         if ( c->x86 == 5 ) {
 111                 static int f00f_workaround_enabled = 0;
 112
 113                 c->f00f_bug = 1;
 114                 if ( !f00f_workaround_enabled ) {
 115                         trap_init_f00f_bug();
 116                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 117                         f00f_workaround_enabled = 1;
 118                 }
 119         }
 120 #endif
 121
 122         select_idle_routine(c);
 123         l2 = init_intel_cacheinfo(c);
 124
 125         /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
 126         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 127                 clear_bit(X86_FEATURE_SEP, c->x86_capability);
 128
 129         /* Names for the Pentium II/Celeron processors
 130            detectable only by also checking the cache size.
 131            Dixon is NOT a Celeron. */
 132         if (c->x86 == 6) {
 133                 switch (c->x86_model) {
 134                 case 5:
 135                         if (c->x86_mask == 0) {
 136                                 if (l2 == 0)
 137                                         p = "Celeron (Covington)";
 138                                 else if (l2 == 256)
 139                                         p = "Mobile Pentium II (Dixon)";
 140                         }
 141                         break;
 142
 143                 case 6:
 144                         if (l2 == 128)
 145                                 p = "Celeron (Mendocino)";
 146                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 147                                 p = "Celeron-A";
 148                         break;
 149
 150                 case 8:
 151                         if (l2 == 128)
 152                                 p = "Celeron (Coppermine)";
 153                         break;
 154                 }
 155         }
 156
 157         if ( p )
 158                 strcpy(c->x86_model_id, p);
 159
 160         c->x86_num_cores = num_cpu_cores(c);
 161
 162         detect_ht(c);
 163
 164         /* Work around errata */
 165         Intel_errata_workarounds(c);
 166
 167 #ifdef CONFIG_X86_INTEL_USERCOPY
 168         /*
 169          * Set up the preferred alignment for movsl bulk memory moves
 170          */
 171         switch (c->x86) {
 172         case 4:         /* 486: untested */
 173                 break;
 174         case 5:         /* Old Pentia: untested */
 175                 break;
 176         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 177                 movsl_mask.mask = 7;
 178                 break;
 179         case 15:        /* P4 is OK down to 8-byte alignment */
 180                 movsl_mask.mask = 7;
 181                 break;
 182         }
 183 #endif
 184
 185         if (c->x86 == 15)
 186                 set_bit(X86_FEATURE_P4, c->x86_capability);
 187         if (c->x86 == 6)
 188                 set_bit(X86_FEATURE_P3, c->x86_capability);
 189 }
 190
 191
 192 static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
 193 {
 194         /* Intel PIII Tualatin. This comes in two flavours.
 195          * One has 256kb of cache, the other 512. We have no way
 196          * to determine which, so we use a boottime override
 197          * for the 512kb model, and assume 256 otherwise.
 198          */
 199         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 200                 size = 256;
 201         return size;
 202 }
 203
 204 static struct cpu_dev intel_cpu_dev __devinitdata = {
 205         .c_vendor       = "Intel",
 206         .c_ident        = { "GenuineIntel" },
 207         .c_models = {
 208                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 209                   {
 210                           [0] = "486 DX-25/33",
 211                           [1] = "486 DX-50",
 212                           [2] = "486 SX",
 213                           [3] = "486 DX/2",
 214                           [4] = "486 SL",
 215                           [5] = "486 SX/2",
 216                           [7] = "486 DX/2-WB",
 217                           [8] = "486 DX/4",
 218                           [9] = "486 DX/4-WB"
 219                   }
 220                 },
 221                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 222                   {
 223                           [0] = "Pentium 60/66 A-step",
 224                           [1] = "Pentium 60/66",
 225                           [2] = "Pentium 75 - 200",
 226                           [3] = "OverDrive PODP5V83",
 227                           [4] = "Pentium MMX",
 228                           [7] = "Mobile Pentium 75 - 200",
 229                           [8] = "Mobile Pentium MMX"
 230                   }
 231                 },
 232                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 233                   {
 234                           [0] = "Pentium Pro A-step",
 235                           [1] = "Pentium Pro",
 236                           [3] = "Pentium II (Klamath)",
 237                           [4] = "Pentium II (Deschutes)",
 238                           [5] = "Pentium II (Deschutes)",
 239                           [6] = "Mobile Pentium II",
 240                           [7] = "Pentium III (Katmai)",
 241                           [8] = "Pentium III (Coppermine)",
 242                           [10] = "Pentium III (Cascades)",
 243                           [11] = "Pentium III (Tualatin)",
 244                   }
 245                 },
 246                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 247                   {
 248                           [0] = "Pentium 4 (Unknown)",
 249                           [1] = "Pentium 4 (Willamette)",
 250                           [2] = "Pentium 4 (Northwood)",
 251                           [4] = "Pentium 4 (Foster)",
 252                           [5] = "Pentium 4 (Foster)",
 253                   }
 254                 },
 255         },
 256         .c_init         = init_intel,
 257         .c_identify     = generic_identify,
 258         .c_size_cache   = intel_size_cache,
 259 };
 260
 261 __init int intel_cpu_init(void)
 262 {
 263         cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
 264         return 0;
 265 }
 266
 267 // arch_initcall(intel_cpu_init);
 268