arch/i386/kernel/acpi/cstate.c

   1 /*
   2  * arch/i386/kernel/acpi/cstate.c
   3  *
   4  * Copyright (C) 2005 Intel Corporation
   5  *      Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
   6  *      - Added _PDC for SMP C-states on Intel CPUs
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/init.h>
  12 #include <linux/acpi.h>
  13 #include <linux/cpu.h>
  14
  15 #include <acpi/processor.h>
  16 #include <asm/acpi.h>
  17
  18 /*
  19  * Initialize bm_flags based on the CPU cache properties
  20  * On SMP it depends on cache configuration
  21  * - When cache is not shared among all CPUs, we flush cache
  22  *   before entering C3.
  23  * - When cache is shared among all CPUs, we use bm_check
  24  *   mechanism as in UP case
  25  *
  26  * This routine is called only after all the CPUs are online
  27  */
  28 void acpi_processor_power_init_bm_check(struct acpi_processor_flags *flags,
  29                                         unsigned int cpu)
  30 {
  31         struct cpuinfo_x86 *c = cpu_data + cpu;
  32
  33         flags->bm_check = 0;
  34         if (num_online_cpus() == 1)
  35                 flags->bm_check = 1;
  36         else if (c->x86_vendor == X86_VENDOR_INTEL) {
  37                 /*
  38                  * Today all CPUs that support C3 share cache.
  39                  * TBD: This needs to look at cache shared map, once
  40                  * multi-core detection patch makes to the base.
  41                  */
  42                 flags->bm_check = 1;
  43         }
  44 }
  45 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
  46
  47 /* The code below handles cstate entry with monitor-mwait pair on Intel*/
  48
  49 struct cstate_entry_s {
  50         struct {
  51                 unsigned int eax;
  52                 unsigned int ecx;
  53         } states[ACPI_PROCESSOR_MAX_POWER];
  54 };
  55 static struct cstate_entry_s *cpu_cstate_entry; /* per CPU ptr */
  56
  57 static short mwait_supported[ACPI_PROCESSOR_MAX_POWER];
  58
  59 #define MWAIT_SUBSTATE_MASK     (0xf)
  60 #define MWAIT_SUBSTATE_SIZE     (4)
  61
  62 #define CPUID_MWAIT_LEAF (5)
  63 #define CPUID5_ECX_EXTENSIONS_SUPPORTED (0x1)
  64 #define CPUID5_ECX_INTERRUPT_BREAK      (0x2)
  65
  66 #define MWAIT_ECX_INTERRUPT_BREAK       (0x1)
  67
  68 #define NATIVE_CSTATE_BEYOND_HALT       (2)
  69
  70 int acpi_processor_ffh_cstate_probe(unsigned int cpu,
  71                 struct acpi_processor_cx *cx, struct acpi_power_register *reg)
  72 {
  73         struct cstate_entry_s *percpu_entry;
  74         struct cpuinfo_x86 *c = cpu_data + cpu;
  75
  76         cpumask_t saved_mask;
  77         int retval;
  78         unsigned int eax, ebx, ecx, edx;
  79         unsigned int edx_part;
  80         unsigned int cstate_type; /* C-state type and not ACPI C-state type */
  81         unsigned int num_cstate_subtype;
  82
  83         if (!cpu_cstate_entry || c->cpuid_level < CPUID_MWAIT_LEAF )
  84                 return -1;
  85
  86         if (reg->bit_offset != NATIVE_CSTATE_BEYOND_HALT)
  87                 return -1;
  88
  89         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
  90         percpu_entry->states[cx->index].eax = 0;
  91         percpu_entry->states[cx->index].ecx = 0;
  92
  93         /* Make sure we are running on right CPU */
  94         saved_mask = current->cpus_allowed;
  95         retval = set_cpus_allowed(current, cpumask_of_cpu(cpu));
  96         if (retval)
  97                 return -1;
  98
  99         cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &edx);
 100
 101         /* Check whether this particular cx_type (in CST) is supported or not */
 102         cstate_type = (cx->address >> MWAIT_SUBSTATE_SIZE) + 1;
 103         edx_part = edx >> (cstate_type * MWAIT_SUBSTATE_SIZE);
 104         num_cstate_subtype = edx_part & MWAIT_SUBSTATE_MASK;
 105
 106         retval = 0;
 107         if (num_cstate_subtype < (cx->address & MWAIT_SUBSTATE_MASK)) {
 108                 retval = -1;
 109                 goto out;
 110         }
 111
 112         /* mwait ecx extensions INTERRUPT_BREAK should be supported for C2/C3 */
 113         if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
 114             !(ecx & CPUID5_ECX_INTERRUPT_BREAK)) {
 115                 retval = -1;
 116                 goto out;
 117         }
 118         percpu_entry->states[cx->index].ecx = MWAIT_ECX_INTERRUPT_BREAK;
 119
 120         /* Use the hint in CST */
 121         percpu_entry->states[cx->index].eax = cx->address;
 122
 123         if (!mwait_supported[cstate_type]) {
 124                 mwait_supported[cstate_type] = 1;
 125                 printk(KERN_DEBUG "Monitor-Mwait will be used to enter C-%d "
 126                        "state\n", cx->type);
 127         }
 128
 129 out:
 130         set_cpus_allowed(current, saved_mask);
 131         return retval;
 132 }
 133 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_probe);
 134
 135 void acpi_processor_ffh_cstate_enter(struct acpi_processor_cx *cx)
 136 {
 137         unsigned int cpu = smp_processor_id();
 138         struct cstate_entry_s *percpu_entry;
 139
 140         percpu_entry = per_cpu_ptr(cpu_cstate_entry, cpu);
 141         mwait_idle_with_hints(percpu_entry->states[cx->index].eax,
 142                               percpu_entry->states[cx->index].ecx);
 143 }
 144 EXPORT_SYMBOL_GPL(acpi_processor_ffh_cstate_enter);
 145
 146 static int __init ffh_cstate_init(void)
 147 {
 148         struct cpuinfo_x86 *c = &boot_cpu_data;
 149         if (c->x86_vendor != X86_VENDOR_INTEL)
 150                 return -1;
 151
 152         cpu_cstate_entry = alloc_percpu(struct cstate_entry_s);
 153         return 0;
 154 }
 155
 156 static void __exit ffh_cstate_exit(void)
 157 {
 158         if (cpu_cstate_entry) {
 159                 free_percpu(cpu_cstate_entry);
 160                 cpu_cstate_entry = NULL;
 161         }
 162 }
 163
 164 arch_initcall(ffh_cstate_init);
 165 __exitcall(ffh_cstate_exit);