1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #ifndef __ASM_CSKY_BARRIER_H
5 #define __ASM_CSKY_BARRIER_H
9 #define nop() asm volatile ("nop\n":::"memory")
12 * sync: completion barrier
13 * sync.s: completion barrier and shareable to other cores
14 * sync.i: completion barrier with flush cpu pipeline
15 * sync.is: completion barrier with flush cpu pipeline and shareable to
18 * bar.brwarw: ordering barrier for all load/store instructions before it
19 * bar.brwarws: ordering barrier for all load/store instructions before it
20 * and shareable to other cores
21 * bar.brar: ordering barrier for all load instructions before it
22 * bar.brars: ordering barrier for all load instructions before it
23 * and shareable to other cores
24 * bar.bwaw: ordering barrier for all store instructions before it
25 * bar.bwaws: ordering barrier for all store instructions before it
26 * and shareable to other cores
29 #ifdef CONFIG_CPU_HAS_CACHEV2
30 #define mb() asm volatile ("bar.brwarw\n":::"memory")
31 #define rmb() asm volatile ("bar.brar\n":::"memory")
32 #define wmb() asm volatile ("bar.bwaw\n":::"memory")
35 #define __smp_mb() asm volatile ("bar.brwarws\n":::"memory")
36 #define __smp_rmb() asm volatile ("bar.brars\n":::"memory")
37 #define __smp_wmb() asm volatile ("bar.bwaws\n":::"memory")
38 #endif /* CONFIG_SMP */
40 #define sync_is() asm volatile ("sync.is\n":::"memory")
42 #else /* !CONFIG_CPU_HAS_CACHEV2 */
43 #define mb() asm volatile ("sync\n":::"memory")
46 #include <asm-generic/barrier.h>
48 #endif /* __ASSEMBLY__ */
49 #endif /* __ASM_CSKY_BARRIER_H */