1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
4 #ifndef __ASM_CSKY_CKMMUV2_H
5 #define __ASM_CSKY_CKMMUV2_H
7 #include <abi/reg_ops.h>
8 #include <asm/barrier.h>
10 static inline int read_mmu_index(void)
12 return mfcr("cr<0, 15>");
15 static inline void write_mmu_index(int value)
17 mtcr("cr<0, 15>", value);
20 static inline int read_mmu_entrylo0(void)
22 return mfcr("cr<2, 15>");
25 static inline int read_mmu_entrylo1(void)
27 return mfcr("cr<3, 15>");
30 static inline void write_mmu_pagemask(int value)
32 mtcr("cr<6, 15>", value);
35 static inline int read_mmu_entryhi(void)
37 return mfcr("cr<4, 15>");
40 static inline void write_mmu_entryhi(int value)
42 mtcr("cr<4, 15>", value);
48 static inline void tlb_probe(void)
50 mtcr("cr<8, 15>", 0x80000000);
53 static inline void tlb_read(void)
55 mtcr("cr<8, 15>", 0x40000000);
58 static inline void tlb_invalid_all(void)
60 #ifdef CONFIG_CPU_HAS_TLBI
61 asm volatile("tlbi.alls\n":::"memory");
64 mtcr("cr<8, 15>", 0x04000000);
68 static inline void tlb_invalid_indexed(void)
70 mtcr("cr<8, 15>", 0x02000000);
73 /* setup hardrefil pgd */
74 static inline unsigned long get_pgd(void)
76 return mfcr("cr<29, 15>");
79 static inline void setup_pgd(unsigned long pgd, bool kernel)
82 mtcr("cr<28, 15>", pgd);
84 mtcr("cr<29, 15>", pgd);
87 #endif /* __ASM_CSKY_CKMMUV2_H */