arch/cris/arch-v10/drivers/sync_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Simple synchronous serial port driver for ETRAX 100LX.
   4  *
   5  * Synchronous serial ports are used for continuous streamed data like audio.
   6  * The default setting for this driver is compatible with the STA 013 MP3
   7  * decoder. The driver can easily be tuned to fit other audio encoder/decoders
   8  * and SPI
   9  *
  10  * Copyright (c) 2001-2008 Axis Communications AB
  11  *
  12  * Author: Mikael Starvik, Johan Adolfsson
  13  *
  14  */
  15 #include <linux/module.h>
  16 #include <linux/kernel.h>
  17 #include <linux/types.h>
  18 #include <linux/errno.h>
  19 #include <linux/major.h>
  20 #include <linux/sched/signal.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/poll.h>
  23 #include <linux/init.h>
  24 #include <linux/mutex.h>
  25 #include <linux/timer.h>
  26 #include <linux/wait.h>
  27 #include <asm/irq.h>
  28 #include <asm/dma.h>
  29 #include <asm/io.h>
  30 #include <arch/svinto.h>
  31 #include <linux/uaccess.h>
  32 #include <asm/sync_serial.h>
  33 #include <arch/io_interface_mux.h>
  34
  35 /* The receiver is a bit tricky because of the continuous stream of data.*/
  36 /*                                                                       */
  37 /* Three DMA descriptors are linked together. Each DMA descriptor is     */
  38 /* responsible for port->bufchunk of a common buffer.                    */
  39 /*                                                                       */
  40 /* +---------------------------------------------+                       */
  41 /* |   +----------+   +----------+   +----------+ |                      */
  42 /* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+                      */
  43 /*     +----------+   +----------+   +----------+                        */
  44 /*         |            |              |                                 */
  45 /*         v            v              v                                 */
  46 /*   +-------------------------------------+                             */
  47 /*   |        BUFFER                       |                             */
  48 /*   +-------------------------------------+                             */
  49 /*      |<- data_avail ->|                                               */
  50 /*    readp          writep                                              */
  51 /*                                                                       */
  52 /* If the application keeps up the pace readp will be right after writep.*/
  53 /* If the application can't keep the pace we have to throw away data.    */
  54 /* The idea is that readp should be ready with the data pointed out by   */
  55 /* Descr[i] when the DMA has filled in Descr[i+1].                       */
  56 /* Otherwise we will discard                                             */
  57 /* the rest of the data pointed out by Descr1 and set readp to the start */
  58 /* of Descr2                                                             */
  59
  60 #define SYNC_SERIAL_MAJOR 125
  61
  62 /* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */
  63 /* words can be handled */
  64 #define IN_BUFFER_SIZE 12288
  65 #define IN_DESCR_SIZE 256
  66 #define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE)
  67 #define OUT_BUFFER_SIZE 4096
  68
  69 #define DEFAULT_FRAME_RATE 0
  70 #define DEFAULT_WORD_RATE 7
  71
  72 /* NOTE: Enabling some debug will likely cause overrun or underrun,
  73  * especially if manual mode is use.
  74  */
  75 #define DEBUG(x)
  76 #define DEBUGREAD(x)
  77 #define DEBUGWRITE(x)
  78 #define DEBUGPOLL(x)
  79 #define DEBUGRXINT(x)
  80 #define DEBUGTXINT(x)
  81
  82 /* Define some macros to access ETRAX 100 registers */
  83 #define SETF(var, reg, field, val) \
  84         do { \
  85                 var = (var & ~IO_MASK_(reg##_, field##_)) | \
  86                         IO_FIELD_(reg##_, field##_, val); \
  87         } while (0)
  88
  89 #define SETS(var, reg, field, val) \
  90         do { \
  91                 var = (var & ~IO_MASK_(reg##_, field##_)) | \
  92                         IO_STATE_(reg##_, field##_, _##val); \
  93         } while (0)
  94
  95 struct sync_port {
  96         /* Etrax registers and bits*/
  97         const volatile unsigned *const status;
  98         volatile unsigned *const ctrl_data;
  99         volatile unsigned *const output_dma_first;
 100         volatile unsigned char *const output_dma_cmd;
 101         volatile unsigned char *const output_dma_clr_irq;
 102         volatile unsigned *const input_dma_first;
 103         volatile unsigned char *const input_dma_cmd;
 104         volatile unsigned *const input_dma_descr;
 105         /* 8*4 */
 106         volatile unsigned char *const input_dma_clr_irq;
 107         volatile unsigned *const data_out;
 108         const volatile unsigned *const data_in;
 109         char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
 110         char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
 111         char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */
 112
 113         char output_dma_bit; /* In R_IRQ_MASK2_RD */
 114         /* End of fields initialised in array */
 115         char started; /* 1 if port has been started */
 116         char port_nbr; /* Port 0 or 1 */
 117         char busy; /* 1 if port is busy */
 118
 119         char enabled;  /* 1 if port is enabled */
 120         char use_dma;  /* 1 if port uses dma */
 121         char tr_running;
 122
 123         char init_irqs;
 124
 125         /* Register shadow */
 126         unsigned int ctrl_data_shadow;
 127         /* Remaining bytes for current transfer */
 128         volatile unsigned int out_count;
 129         /* Current position in out_buffer */
 130         unsigned char *outp;
 131         /* 16*4 */
 132         /* Next byte to be read by application */
 133         volatile unsigned char *volatile readp;
 134         /* Next byte to be written by etrax */
 135         volatile unsigned char *volatile writep;
 136
 137         unsigned int in_buffer_size;
 138         unsigned int inbufchunk;
 139         struct etrax_dma_descr out_descr __attribute__ ((aligned(32)));
 140         struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32)));
 141         unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32)));
 142         unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32)));
 143         unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32)));
 144         struct etrax_dma_descr *next_rx_desc;
 145         struct etrax_dma_descr *prev_rx_desc;
 146         int full;
 147
 148         wait_queue_head_t out_wait_q;
 149         wait_queue_head_t in_wait_q;
 150 };
 151
 152
 153 static DEFINE_MUTEX(sync_serial_mutex);
 154 static int etrax_sync_serial_init(void);
 155 static void initialize_port(int portnbr);
 156 static inline int sync_data_avail(struct sync_port *port);
 157
 158 static int sync_serial_open(struct inode *inode, struct file *file);
 159 static int sync_serial_release(struct inode *inode, struct file *file);
 160 static unsigned int sync_serial_poll(struct file *filp, poll_table *wait);
 161
 162 static long sync_serial_ioctl(struct file *file,
 163         unsigned int cmd, unsigned long arg);
 164 static ssize_t sync_serial_write(struct file *file, const char *buf,
 165         size_t count, loff_t *ppos);
 166 static ssize_t sync_serial_read(struct file *file, char *buf,
 167         size_t count, loff_t *ppos);
 168
 169 #if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
 170      defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
 171     (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
 172      defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
 173 #define SYNC_SER_DMA
 174 #endif
 175
 176 static void send_word(struct sync_port *port);
 177 static void start_dma(struct sync_port *port, const char *data, int count);
 178 static void start_dma_in(struct sync_port *port);
 179 #ifdef SYNC_SER_DMA
 180 static irqreturn_t tr_interrupt(int irq, void *dev_id);
 181 static irqreturn_t rx_interrupt(int irq, void *dev_id);
 182 #endif
 183 #if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \
 184      !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \
 185     (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \
 186      !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)))
 187 #define SYNC_SER_MANUAL
 188 #endif
 189 #ifdef SYNC_SER_MANUAL
 190 static irqreturn_t manual_interrupt(int irq, void *dev_id);
 191 #endif
 192
 193 /* The ports */
 194 static struct sync_port ports[] = {
 195         {
 196                 .status                = R_SYNC_SERIAL1_STATUS,
 197                 .ctrl_data             = R_SYNC_SERIAL1_CTRL,
 198                 .output_dma_first      = R_DMA_CH8_FIRST,
 199                 .output_dma_cmd        = R_DMA_CH8_CMD,
 200                 .output_dma_clr_irq    = R_DMA_CH8_CLR_INTR,
 201                 .input_dma_first       = R_DMA_CH9_FIRST,
 202                 .input_dma_cmd         = R_DMA_CH9_CMD,
 203                 .input_dma_descr       = R_DMA_CH9_DESCR,
 204                 .input_dma_clr_irq     = R_DMA_CH9_CLR_INTR,
 205                 .data_out              = R_SYNC_SERIAL1_TR_DATA,
 206                 .data_in               = R_SYNC_SERIAL1_REC_DATA,
 207                 .data_avail_bit        = IO_BITNR(R_IRQ_MASK1_RD, ser1_data),
 208                 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready),
 209                 .input_dma_descr_bit   = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr),
 210                 .output_dma_bit        = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop),
 211                 .init_irqs             = 1,
 212 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
 213                 .use_dma               = 1,
 214 #else
 215                 .use_dma               = 0,
 216 #endif
 217         },
 218         {
 219                 .status                = R_SYNC_SERIAL3_STATUS,
 220                 .ctrl_data             = R_SYNC_SERIAL3_CTRL,
 221                 .output_dma_first      = R_DMA_CH4_FIRST,
 222                 .output_dma_cmd        = R_DMA_CH4_CMD,
 223                 .output_dma_clr_irq    = R_DMA_CH4_CLR_INTR,
 224                 .input_dma_first       = R_DMA_CH5_FIRST,
 225                 .input_dma_cmd         = R_DMA_CH5_CMD,
 226                 .input_dma_descr       = R_DMA_CH5_DESCR,
 227                 .input_dma_clr_irq     = R_DMA_CH5_CLR_INTR,
 228                 .data_out              = R_SYNC_SERIAL3_TR_DATA,
 229                 .data_in               = R_SYNC_SERIAL3_REC_DATA,
 230                 .data_avail_bit        = IO_BITNR(R_IRQ_MASK1_RD, ser3_data),
 231                 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready),
 232                 .input_dma_descr_bit   = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr),
 233                 .output_dma_bit        = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop),
 234                 .init_irqs             = 1,
 235 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
 236                 .use_dma               = 1,
 237 #else
 238                 .use_dma               = 0,
 239 #endif
 240         }
 241 };
 242
 243 /* Register shadows */
 244 static unsigned sync_serial_prescale_shadow;
 245
 246 #define NUMBER_OF_PORTS 2
 247
 248 static const struct file_operations sync_serial_fops = {
 249         .owner          = THIS_MODULE,
 250         .write          = sync_serial_write,
 251         .read           = sync_serial_read,
 252         .poll           = sync_serial_poll,
 253         .unlocked_ioctl = sync_serial_ioctl,
 254         .open           = sync_serial_open,
 255         .release        = sync_serial_release,
 256         .llseek         = noop_llseek,
 257 };
 258
 259 static int __init etrax_sync_serial_init(void)
 260 {
 261         ports[0].enabled = 0;
 262         ports[1].enabled = 0;
 263
 264 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
 265         if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) {
 266                 printk(KERN_CRIT "ETRAX100LX sync_serial: "
 267                         "Could not allocate IO group for port %d\n", 0);
 268                 return -EBUSY;
 269         }
 270 #endif
 271 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
 272         if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) {
 273 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
 274                 cris_free_io_interface(if_sync_serial_1);
 275 #endif
 276                 printk(KERN_CRIT "ETRAX100LX sync_serial: "
 277                         "Could not allocate IO group for port %d\n", 1);
 278                 return -EBUSY;
 279         }
 280 #endif
 281
 282         if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial",
 283                         &sync_serial_fops) < 0) {
 284 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
 285                 cris_free_io_interface(if_sync_serial_3);
 286 #endif
 287 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
 288                 cris_free_io_interface(if_sync_serial_1);
 289 #endif
 290                 printk("unable to get major for synchronous serial port\n");
 291                 return -EBUSY;
 292         }
 293
 294         /* Deselect synchronous serial ports while configuring. */
 295         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
 296         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
 297         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 298
 299         /* Initialize Ports */
 300 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0)
 301         ports[0].enabled = 1;
 302         SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra);
 303         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
 304 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)
 305         ports[0].use_dma = 1;
 306 #else
 307         ports[0].use_dma = 0;
 308 #endif
 309         initialize_port(0);
 310 #endif
 311
 312 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1)
 313         ports[1].enabled = 1;
 314         SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra);
 315         SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
 316 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA)
 317         ports[1].use_dma = 1;
 318 #else
 319         ports[1].use_dma = 0;
 320 #endif
 321         initialize_port(1);
 322 #endif
 323
 324         *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */
 325
 326         /* Set up timing */
 327         *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = (
 328                 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) |
 329                 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) |
 330                 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) |
 331                 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) |
 332                 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) |
 333                 IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate,
 334                         DEFAULT_FRAME_RATE) |
 335                 IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) |
 336                 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal));
 337
 338         /* Select synchronous ports */
 339         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 340
 341         printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n");
 342         return 0;
 343 }
 344
 345 static void __init initialize_port(int portnbr)
 346 {
 347         struct sync_port *port = &ports[portnbr];
 348
 349         DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr));
 350
 351         port->started = 0;
 352         port->port_nbr = portnbr;
 353         port->busy = 0;
 354         port->tr_running = 0;
 355
 356         port->out_count = 0;
 357         port->outp = port->out_buffer;
 358
 359         port->readp = port->flip;
 360         port->writep = port->flip;
 361         port->in_buffer_size = IN_BUFFER_SIZE;
 362         port->inbufchunk = IN_DESCR_SIZE;
 363         port->next_rx_desc = &port->in_descr[0];
 364         port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1];
 365         port->prev_rx_desc->ctrl = d_eol;
 366
 367         init_waitqueue_head(&port->out_wait_q);
 368         init_waitqueue_head(&port->in_wait_q);
 369
 370         port->ctrl_data_shadow =
 371                 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz)   |
 372                 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) |
 373                 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore)       |
 374                 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) |
 375                 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal)  |
 376                 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word)    |
 377                 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on)            |
 378                 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal)    |
 379                 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped)   |
 380                 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb)         |
 381                 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable)  |
 382                 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit)  |
 383                 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8)    |
 384                 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8)     |
 385                 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled)  |
 386                 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg)   |
 387                 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)|
 388                 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)|
 389                 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal)   |
 390                 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) |
 391                 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)|
 392                 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high);
 393
 394         if (port->use_dma)
 395                 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
 396                         dma_enable, on);
 397         else
 398                 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL,
 399                         dma_enable, off);
 400
 401         *port->ctrl_data = port->ctrl_data_shadow;
 402 }
 403
 404 static inline int sync_data_avail(struct sync_port *port)
 405 {
 406         int avail;
 407         unsigned char *start;
 408         unsigned char *end;
 409
 410         start = (unsigned char *)port->readp; /* cast away volatile */
 411         end = (unsigned char *)port->writep;  /* cast away volatile */
 412         /* 0123456789  0123456789
 413          *  -----      -    -----
 414          *  ^rp  ^wp    ^wp ^rp
 415          */
 416         if (end >= start)
 417                 avail = end - start;
 418         else
 419                 avail = port->in_buffer_size - (start - end);
 420         return avail;
 421 }
 422
 423 static inline int sync_data_avail_to_end(struct sync_port *port)
 424 {
 425         int avail;
 426         unsigned char *start;
 427         unsigned char *end;
 428
 429         start = (unsigned char *)port->readp; /* cast away volatile */
 430         end = (unsigned char *)port->writep;  /* cast away volatile */
 431         /* 0123456789  0123456789
 432          *  -----           -----
 433          *  ^rp  ^wp    ^wp ^rp
 434          */
 435
 436         if (end >= start)
 437                 avail = end - start;
 438         else
 439                 avail = port->flip + port->in_buffer_size - start;
 440         return avail;
 441 }
 442
 443
 444 static int sync_serial_open(struct inode *inode, struct file *file)
 445 {
 446         int dev = MINOR(inode->i_rdev);
 447         struct sync_port *port;
 448         int mode;
 449         int err = -EBUSY;
 450
 451         mutex_lock(&sync_serial_mutex);
 452         DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev));
 453
 454         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
 455                 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
 456                 err = -ENODEV;
 457                 goto out;
 458         }
 459         port = &ports[dev];
 460         /* Allow open this device twice (assuming one reader and one writer) */
 461         if (port->busy == 2) {
 462                 DEBUG(printk(KERN_DEBUG "Device is busy.. \n"));
 463                 goto out;
 464         }
 465         if (port->init_irqs) {
 466                 if (port->use_dma) {
 467                         if (port == &ports[0]) {
 468 #ifdef SYNC_SER_DMA
 469                                 if (request_irq(24, tr_interrupt, 0,
 470                                                 "synchronous serial 1 dma tr",
 471                                                 &ports[0])) {
 472                                         printk(KERN_CRIT "Can't alloc "
 473                                                 "sync serial port 1 IRQ");
 474                                         goto out;
 475                                 } else if (request_irq(25, rx_interrupt, 0,
 476                                                 "synchronous serial 1 dma rx",
 477                                                 &ports[0])) {
 478                                         free_irq(24, &port[0]);
 479                                         printk(KERN_CRIT "Can't alloc "
 480                                                 "sync serial port 1 IRQ");
 481                                         goto out;
 482                                 } else if (cris_request_dma(8,
 483                                                 "synchronous serial 1 dma tr",
 484                                                 DMA_VERBOSE_ON_ERROR,
 485                                                 dma_ser1)) {
 486                                         free_irq(24, &port[0]);
 487                                         free_irq(25, &port[0]);
 488                                         printk(KERN_CRIT "Can't alloc "
 489                                                 "sync serial port 1 "
 490                                                 "TX DMA channel");
 491                                         goto out;
 492                                 } else if (cris_request_dma(9,
 493                                                 "synchronous serial 1 dma rec",
 494                                                 DMA_VERBOSE_ON_ERROR,
 495                                                 dma_ser1)) {
 496                                         cris_free_dma(8, NULL);
 497                                         free_irq(24, &port[0]);
 498                                         free_irq(25, &port[0]);
 499                                         printk(KERN_CRIT "Can't alloc "
 500                                                 "sync serial port 1 "
 501                                                 "RX DMA channel");
 502                                         goto out;
 503                                 }
 504 #endif
 505                                 RESET_DMA(8); WAIT_DMA(8);
 506                                 RESET_DMA(9); WAIT_DMA(9);
 507                                 *R_DMA_CH8_CLR_INTR =
 508                                         IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop,
 509                                                 do) |
 510                                         IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr,
 511                                                 do);
 512                                 *R_DMA_CH9_CLR_INTR =
 513                                         IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop,
 514                                                 do) |
 515                                         IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr,
 516                                                 do);
 517                                 *R_IRQ_MASK2_SET =
 518                                         IO_STATE(R_IRQ_MASK2_SET, dma8_eop,
 519                                                 set) |
 520                                         IO_STATE(R_IRQ_MASK2_SET, dma9_descr,
 521                                                 set);
 522                         } else if (port == &ports[1]) {
 523 #ifdef SYNC_SER_DMA
 524                                 if (request_irq(20, tr_interrupt, 0,
 525                                                 "synchronous serial 3 dma tr",
 526                                                 &ports[1])) {
 527                                         printk(KERN_CRIT "Can't alloc "
 528                                                 "sync serial port 3 IRQ");
 529                                         goto out;
 530                                 } else if (request_irq(21, rx_interrupt, 0,
 531                                                 "synchronous serial 3 dma rx",
 532                                                 &ports[1])) {
 533                                         free_irq(20, &ports[1]);
 534                                         printk(KERN_CRIT "Can't alloc "
 535                                                 "sync serial port 3 IRQ");
 536                                         goto out;
 537                                 } else if (cris_request_dma(4,
 538                                                 "synchronous serial 3 dma tr",
 539                                                 DMA_VERBOSE_ON_ERROR,
 540                                                 dma_ser3)) {
 541                                         free_irq(21, &ports[1]);
 542                                         free_irq(20, &ports[1]);
 543                                         printk(KERN_CRIT "Can't alloc "
 544                                                 "sync serial port 3 "
 545                                                 "TX DMA channel");
 546                                         goto out;
 547                                 } else if (cris_request_dma(5,
 548                                                 "synchronous serial 3 dma rec",
 549                                                 DMA_VERBOSE_ON_ERROR,
 550                                                 dma_ser3)) {
 551                                         cris_free_dma(4, NULL);
 552                                         free_irq(21, &ports[1]);
 553                                         free_irq(20, &ports[1]);
 554                                         printk(KERN_CRIT "Can't alloc "
 555                                                 "sync serial port 3 "
 556                                                 "RX DMA channel");
 557                                         goto out;
 558                                 }
 559 #endif
 560                                 RESET_DMA(4); WAIT_DMA(4);
 561                                 RESET_DMA(5); WAIT_DMA(5);
 562                                 *R_DMA_CH4_CLR_INTR =
 563                                         IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop,
 564                                                 do) |
 565                                         IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr,
 566                                                 do);
 567                                 *R_DMA_CH5_CLR_INTR =
 568                                         IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop,
 569                                                 do) |
 570                                         IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr,
 571                                                 do);
 572                                 *R_IRQ_MASK2_SET =
 573                                         IO_STATE(R_IRQ_MASK2_SET, dma4_eop,
 574                                                 set) |
 575                                         IO_STATE(R_IRQ_MASK2_SET, dma5_descr,
 576                                                 set);
 577                         }
 578                         start_dma_in(port);
 579                         port->init_irqs = 0;
 580                 } else { /* !port->use_dma */
 581 #ifdef SYNC_SER_MANUAL
 582                         if (port == &ports[0]) {
 583                                 if (request_irq(8,
 584                                                 manual_interrupt,
 585                                                 IRQF_SHARED,
 586                                                 "synchronous serial manual irq",
 587                                                 &ports[0])) {
 588                                         printk(KERN_CRIT "Can't alloc "
 589                                                 "sync serial manual irq");
 590                                         goto out;
 591                                 }
 592                         } else if (port == &ports[1]) {
 593                                 if (request_irq(8,
 594                                                 manual_interrupt,
 595                                                 IRQF_SHARED,
 596                                                 "synchronous serial manual irq",
 597                                                 &ports[1])) {
 598                                         printk(KERN_CRIT "Can't alloc "
 599                                                 "sync serial manual irq");
 600                                         goto out;
 601                                 }
 602                         }
 603                         port->init_irqs = 0;
 604 #else
 605                         panic("sync_serial: Manual mode not supported.\n");
 606 #endif /* SYNC_SER_MANUAL */
 607                 }
 608         } /* port->init_irqs */
 609
 610         port->busy++;
 611         /* Start port if we use it as input */
 612         mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow);
 613         if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) ||
 614             mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) ||
 615             mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) ||
 616             mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) {
 617                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
 618                         running);
 619                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
 620                         enable);
 621                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
 622                         enable);
 623                 port->started = 1;
 624                 *port->ctrl_data = port->ctrl_data_shadow;
 625                 if (!port->use_dma)
 626                         *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
 627                 DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev));
 628         }
 629         err = 0;
 630
 631 out:
 632         mutex_unlock(&sync_serial_mutex);
 633         return err;
 634 }
 635
 636 static int sync_serial_release(struct inode *inode, struct file *file)
 637 {
 638         int dev = MINOR(inode->i_rdev);
 639         struct sync_port *port;
 640
 641         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
 642                 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
 643                 return -ENODEV;
 644         }
 645         port = &ports[dev];
 646         if (port->busy)
 647                 port->busy--;
 648         if (!port->busy)
 649                 *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) |
 650                                     (1 << port->transmitter_ready_bit));
 651
 652         return 0;
 653 }
 654
 655
 656
 657 static unsigned int sync_serial_poll(struct file *file, poll_table *wait)
 658 {
 659         int dev = MINOR(file_inode(file)->i_rdev);
 660         unsigned int mask = 0;
 661         struct sync_port *port;
 662         DEBUGPOLL(static unsigned int prev_mask = 0);
 663
 664         port = &ports[dev];
 665         poll_wait(file, &port->out_wait_q, wait);
 666         poll_wait(file, &port->in_wait_q, wait);
 667         /* Some room to write */
 668         if (port->out_count < OUT_BUFFER_SIZE)
 669                 mask |=  POLLOUT | POLLWRNORM;
 670         /* At least an inbufchunk of data */
 671         if (sync_data_avail(port) >= port->inbufchunk)
 672                 mask |= POLLIN | POLLRDNORM;
 673
 674         DEBUGPOLL(if (mask != prev_mask)
 675                 printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n",
 676                         mask,
 677                         mask & POLLOUT ? "POLLOUT" : "",
 678                         mask & POLLIN ? "POLLIN" : "");
 679                 prev_mask = mask;
 680         );
 681         return mask;
 682 }
 683
 684 static int sync_serial_ioctl_unlocked(struct file *file,
 685                   unsigned int cmd, unsigned long arg)
 686 {
 687         int return_val = 0;
 688         unsigned long flags;
 689
 690         int dev = MINOR(file_inode(file)->i_rdev);
 691         struct sync_port *port;
 692
 693         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
 694                 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
 695                 return -1;
 696         }
 697         port = &ports[dev];
 698
 699         local_irq_save(flags);
 700         /* Disable port while changing config */
 701         if (dev) {
 702                 if (port->use_dma) {
 703                         RESET_DMA(4); WAIT_DMA(4);
 704                         port->tr_running = 0;
 705                         port->out_count = 0;
 706                         port->outp = port->out_buffer;
 707                         *R_DMA_CH4_CLR_INTR =
 708                                 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) |
 709                                 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do);
 710                 }
 711                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async);
 712         } else {
 713                 if (port->use_dma) {
 714                         RESET_DMA(8); WAIT_DMA(8);
 715                         port->tr_running = 0;
 716                         port->out_count = 0;
 717                         port->outp = port->out_buffer;
 718                         *R_DMA_CH8_CLR_INTR =
 719                                 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) |
 720                                 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do);
 721                 }
 722                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async);
 723         }
 724         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 725         local_irq_restore(flags);
 726
 727         switch (cmd) {
 728         case SSP_SPEED:
 729                 if (GET_SPEED(arg) == CODEC) {
 730                         if (dev)
 731                                 SETS(sync_serial_prescale_shadow,
 732                                         R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
 733                                         codec);
 734                         else
 735                                 SETS(sync_serial_prescale_shadow,
 736                                         R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
 737                                         codec);
 738
 739                         SETF(sync_serial_prescale_shadow,
 740                                 R_SYNC_SERIAL_PRESCALE, prescaler,
 741                                 GET_FREQ(arg));
 742                         SETF(sync_serial_prescale_shadow,
 743                                 R_SYNC_SERIAL_PRESCALE, frame_rate,
 744                                 GET_FRAME_RATE(arg));
 745                         SETF(sync_serial_prescale_shadow,
 746                                 R_SYNC_SERIAL_PRESCALE, word_rate,
 747                                 GET_WORD_RATE(arg));
 748                 } else {
 749                         SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 750                                 tr_baud, GET_SPEED(arg));
 751                         if (dev)
 752                                 SETS(sync_serial_prescale_shadow,
 753                                         R_SYNC_SERIAL_PRESCALE, clk_sel_u3,
 754                                         baudrate);
 755                         else
 756                                 SETS(sync_serial_prescale_shadow,
 757                                         R_SYNC_SERIAL_PRESCALE, clk_sel_u1,
 758                                         baudrate);
 759                 }
 760                 break;
 761         case SSP_MODE:
 762                 if (arg > 5)
 763                         return -EINVAL;
 764                 if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT)
 765                         *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit;
 766                 else if (!port->use_dma)
 767                         *R_IRQ_MASK1_SET = 1 << port->data_avail_bit;
 768                 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg);
 769                 break;
 770         case SSP_FRAME_SYNC:
 771                 if (arg & NORMAL_SYNC)
 772                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 773                                 f_synctype, normal);
 774                 else if (arg & EARLY_SYNC)
 775                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 776                                 f_synctype, early);
 777
 778                 if (arg & BIT_SYNC)
 779                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 780                                 f_syncsize, bit);
 781                 else if (arg & WORD_SYNC)
 782                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 783                                 f_syncsize, word);
 784                 else if (arg & EXTENDED_SYNC)
 785                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 786                                 f_syncsize, extended);
 787
 788                 if (arg & SYNC_ON)
 789                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 790                                 f_sync, on);
 791                 else if (arg & SYNC_OFF)
 792                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 793                                 f_sync, off);
 794
 795                 if (arg & WORD_SIZE_8)
 796                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 797                                 wordsize, size8bit);
 798                 else if (arg & WORD_SIZE_12)
 799                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 800                                 wordsize, size12bit);
 801                 else if (arg & WORD_SIZE_16)
 802                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 803                                 wordsize, size16bit);
 804                 else if (arg & WORD_SIZE_24)
 805                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 806                                 wordsize, size24bit);
 807                 else if (arg & WORD_SIZE_32)
 808                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 809                                 wordsize, size32bit);
 810
 811                 if (arg & BIT_ORDER_MSB)
 812                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 813                                 bitorder, msb);
 814                 else if (arg & BIT_ORDER_LSB)
 815                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 816                                 bitorder, lsb);
 817
 818                 if (arg & FLOW_CONTROL_ENABLE)
 819                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 820                                 flow_ctrl, enabled);
 821                 else if (arg & FLOW_CONTROL_DISABLE)
 822                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 823                                 flow_ctrl, disabled);
 824
 825                 if (arg & CLOCK_NOT_GATED)
 826                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 827                                 clk_mode, normal);
 828                 else if (arg & CLOCK_GATED)
 829                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 830                                 clk_mode, gated);
 831
 832                 break;
 833         case SSP_IPOLARITY:
 834                 /* NOTE!! negedge is considered NORMAL */
 835                 if (arg & CLOCK_NORMAL)
 836                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 837                                 clk_polarity, neg);
 838                 else if (arg & CLOCK_INVERT)
 839                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 840                                 clk_polarity, pos);
 841
 842                 if (arg & FRAME_NORMAL)
 843                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 844                                 frame_polarity, normal);
 845                 else if (arg & FRAME_INVERT)
 846                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 847                                 frame_polarity, inverted);
 848
 849                 if (arg & STATUS_NORMAL)
 850                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 851                                 status_polarity, normal);
 852                 else if (arg & STATUS_INVERT)
 853                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 854                                 status_polarity, inverted);
 855                 break;
 856         case SSP_OPOLARITY:
 857                 if (arg & CLOCK_NORMAL)
 858                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 859                                 clk_driver, normal);
 860                 else if (arg & CLOCK_INVERT)
 861                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 862                                 clk_driver, inverted);
 863
 864                 if (arg & FRAME_NORMAL)
 865                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 866                                 frame_driver, normal);
 867                 else if (arg & FRAME_INVERT)
 868                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 869                                 frame_driver, inverted);
 870
 871                 if (arg & STATUS_NORMAL)
 872                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 873                                 status_driver, normal);
 874                 else if (arg & STATUS_INVERT)
 875                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 876                                 status_driver, inverted);
 877                 break;
 878         case SSP_SPI:
 879                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl,
 880                         disabled);
 881                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder,
 882                         msb);
 883                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize,
 884                         size8bit);
 885                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on);
 886                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize,
 887                         word);
 888                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype,
 889                         normal);
 890                 if (arg & SPI_SLAVE) {
 891                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 892                                 frame_polarity, inverted);
 893                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 894                                 clk_polarity, neg);
 895                         SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 896                                 mode, SLAVE_INPUT);
 897                 } else {
 898                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 899                                 frame_driver, inverted);
 900                         SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 901                                 clk_driver, inverted);
 902                         SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL,
 903                                 mode, MASTER_OUTPUT);
 904                 }
 905                 break;
 906         case SSP_INBUFCHUNK:
 907 #if 0
 908                 if (arg > port->in_buffer_size/NUM_IN_DESCR)
 909                         return -EINVAL;
 910                 port->inbufchunk = arg;
 911                 /* Make sure in_buffer_size is a multiple of inbufchunk */
 912                 port->in_buffer_size =
 913                         (port->in_buffer_size/port->inbufchunk) *
 914                         port->inbufchunk;
 915                 DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n",
 916                         port->inbufchunk, port->in_buffer_size));
 917                 if (port->use_dma) {
 918                         if (port->port_nbr == 0) {
 919                                 RESET_DMA(9);
 920                                 WAIT_DMA(9);
 921                         } else {
 922                                 RESET_DMA(5);
 923                                 WAIT_DMA(5);
 924                         }
 925                         start_dma_in(port);
 926                 }
 927 #endif
 928                 break;
 929         default:
 930                 return_val = -1;
 931         }
 932         /* Make sure we write the config without interruption */
 933         local_irq_save(flags);
 934         /* Set config and enable port */
 935         *port->ctrl_data = port->ctrl_data_shadow;
 936         nop(); nop(); nop(); nop();
 937         *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow;
 938         nop(); nop(); nop(); nop();
 939         if (dev)
 940                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync);
 941         else
 942                 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync);
 943
 944         *R_GEN_CONFIG_II = gen_config_ii_shadow;
 945         /* Reset DMA. At readout from serial port the data could be shifted
 946          * one byte if not resetting DMA.
 947          */
 948         if (port->use_dma) {
 949                 if (port->port_nbr == 0) {
 950                         RESET_DMA(9);
 951                         WAIT_DMA(9);
 952                 } else {
 953                         RESET_DMA(5);
 954                         WAIT_DMA(5);
 955                 }
 956                 start_dma_in(port);
 957         }
 958         local_irq_restore(flags);
 959         return return_val;
 960 }
 961
 962 static long sync_serial_ioctl(struct file *file,
 963                               unsigned int cmd, unsigned long arg)
 964 {
 965         long ret;
 966
 967         mutex_lock(&sync_serial_mutex);
 968         ret = sync_serial_ioctl_unlocked(file, cmd, arg);
 969         mutex_unlock(&sync_serial_mutex);
 970
 971         return ret;
 972 }
 973
 974
 975 static ssize_t sync_serial_write(struct file *file, const char *buf,
 976         size_t count, loff_t *ppos)
 977 {
 978         int dev = MINOR(file_inode(file)->i_rdev);
 979         DECLARE_WAITQUEUE(wait, current);
 980         struct sync_port *port;
 981         unsigned long flags;
 982         unsigned long c, c1;
 983         unsigned long free_outp;
 984         unsigned long outp;
 985         unsigned long out_buffer;
 986
 987         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
 988                 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
 989                 return -ENODEV;
 990         }
 991         port = &ports[dev];
 992
 993         DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n",
 994                 port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE));
 995         /* Space to end of buffer */
 996         /*
 997          * out_buffer <c1>012345<-   c    ->OUT_BUFFER_SIZE
 998          *            outp^    +out_count
 999          *                      ^free_outp
1000          * out_buffer 45<-     c      ->0123OUT_BUFFER_SIZE
1001          *             +out_count   outp^
1002          *              free_outp
1003          *
1004          */
1005
1006         /* Read variables that may be updated by interrupts */
1007         local_irq_save(flags);
1008         if (count > OUT_BUFFER_SIZE - port->out_count)
1009                 count = OUT_BUFFER_SIZE - port->out_count;
1010
1011         outp = (unsigned long)port->outp;
1012         free_outp = outp + port->out_count;
1013         local_irq_restore(flags);
1014         out_buffer = (unsigned long)port->out_buffer;
1015
1016         /* Find out where and how much to write */
1017         if (free_outp >= out_buffer + OUT_BUFFER_SIZE)
1018                 free_outp -= OUT_BUFFER_SIZE;
1019         if (free_outp >= outp)
1020                 c = out_buffer + OUT_BUFFER_SIZE - free_outp;
1021         else
1022                 c = outp - free_outp;
1023         if (c > count)
1024                 c = count;
1025
1026         DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n",
1027                 outp, free_outp, c));
1028         if (copy_from_user((void *)free_outp, buf, c))
1029                 return -EFAULT;
1030
1031         if (c != count) {
1032                 buf += c;
1033                 c1 = count - c;
1034                 DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n",
1035                         free_outp-out_buffer, c, c1));
1036                 if (copy_from_user((void *)out_buffer, buf, c1))
1037                         return -EFAULT;
1038         }
1039         local_irq_save(flags);
1040         port->out_count += count;
1041         local_irq_restore(flags);
1042
1043         /* Make sure transmitter/receiver is running */
1044         if (!port->started) {
1045                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
1046                         running);
1047                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
1048                         enable);
1049                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
1050                         enable);
1051                 port->started = 1;
1052         }
1053
1054         *port->ctrl_data = port->ctrl_data_shadow;
1055
1056         if (file->f_flags & O_NONBLOCK) {
1057                 local_irq_save(flags);
1058                 if (!port->tr_running) {
1059                         if (!port->use_dma) {
1060                                 /* Start sender by writing data */
1061                                 send_word(port);
1062                                 /* and enable transmitter ready IRQ */
1063                                 *R_IRQ_MASK1_SET = 1 <<
1064                                         port->transmitter_ready_bit;
1065                         } else
1066                                 start_dma(port,
1067                                         (unsigned char *volatile)port->outp, c);
1068                 }
1069                 local_irq_restore(flags);
1070                 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n",
1071                         port->port_nbr, count));
1072                 return count;
1073         }
1074
1075         /* Sleep until all sent */
1076         add_wait_queue(&port->out_wait_q, &wait);
1077         set_current_state(TASK_INTERRUPTIBLE);
1078         local_irq_save(flags);
1079         if (!port->tr_running) {
1080                 if (!port->use_dma) {
1081                         /* Start sender by writing data */
1082                         send_word(port);
1083                         /* and enable transmitter ready IRQ */
1084                         *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit;
1085                 } else
1086                         start_dma(port, port->outp, c);
1087         }
1088         local_irq_restore(flags);
1089         schedule();
1090         remove_wait_queue(&port->out_wait_q, &wait);
1091         if (signal_pending(current))
1092                 return -EINTR;
1093
1094         DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count));
1095         return count;
1096 }
1097
1098 static ssize_t sync_serial_read(struct file *file, char *buf,
1099                                 size_t count, loff_t *ppos)
1100 {
1101         int dev = MINOR(file_inode(file)->i_rdev);
1102         int avail;
1103         struct sync_port *port;
1104         unsigned char *start;
1105         unsigned char *end;
1106         unsigned long flags;
1107
1108         if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) {
1109                 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev));
1110                 return -ENODEV;
1111         }
1112         port = &ports[dev];
1113
1114         DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n",
1115                 dev, count, port->readp - port->flip,
1116                 port->writep - port->flip, port->in_buffer_size));
1117
1118         if (!port->started) {
1119                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt,
1120                         running);
1121                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable,
1122                         enable);
1123                 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable,
1124                         enable);
1125                 port->started = 1;
1126         }
1127         *port->ctrl_data = port->ctrl_data_shadow;
1128
1129         /* Calculate number of available bytes */
1130         /* Save pointers to avoid that they are modified by interrupt */
1131         local_irq_save(flags);
1132         start = (unsigned char *)port->readp; /* cast away volatile */
1133         end = (unsigned char *)port->writep;  /* cast away volatile */
1134         local_irq_restore(flags);
1135         while (start == end && !port->full) {
1136                 /* No data */
1137                 if (file->f_flags & O_NONBLOCK)
1138                         return -EAGAIN;
1139
1140                 wait_event_interruptible(port->in_wait_q,
1141                                          !(start == end && !port->full));
1142                 if (signal_pending(current))
1143                         return -EINTR;
1144
1145                 local_irq_save(flags);
1146                 start = (unsigned char *)port->readp; /* cast away volatile */
1147                 end = (unsigned char *)port->writep;  /* cast away volatile */
1148                 local_irq_restore(flags);
1149         }
1150
1151         /* Lazy read, never return wrapped data. */
1152         if (port->full)
1153                 avail = port->in_buffer_size;
1154         else if (end > start)
1155                 avail = end - start;
1156         else
1157                 avail = port->flip + port->in_buffer_size - start;
1158
1159         count = count > avail ? avail : count;
1160         if (copy_to_user(buf, start, count))
1161                 return -EFAULT;
1162         /* Disable interrupts while updating readp */
1163         local_irq_save(flags);
1164         port->readp += count;
1165         if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */
1166                 port->readp = port->flip;
1167         port->full = 0;
1168         local_irq_restore(flags);
1169         DEBUGREAD(printk(KERN_DEBUG "r %d\n", count));
1170         return count;
1171 }
1172
1173 static void send_word(struct sync_port *port)
1174 {
1175         switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize,
1176                         port->ctrl_data_shadow)) {
1177         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1178                  port->out_count--;
1179                  *port->data_out = *port->outp++;
1180                  if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1181                          port->outp = port->out_buffer;
1182                  break;
1183         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1184         {
1185                 int data = (*port->outp++) << 8;
1186                 data |= *port->outp++;
1187                 port->out_count -= 2;
1188                 *port->data_out = data;
1189                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1190                         port->outp = port->out_buffer;
1191                 break;
1192         }
1193         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1194                 port->out_count -= 2;
1195                 *port->data_out = *(unsigned short *)port->outp;
1196                 port->outp += 2;
1197                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1198                         port->outp = port->out_buffer;
1199                 break;
1200         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1201                 port->out_count -= 3;
1202                 *port->data_out = *(unsigned int *)port->outp;
1203                 port->outp += 3;
1204                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1205                         port->outp = port->out_buffer;
1206                 break;
1207         case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
1208                 port->out_count -= 4;
1209                 *port->data_out = *(unsigned int *)port->outp;
1210                 port->outp += 4;
1211                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1212                         port->outp = port->out_buffer;
1213                 break;
1214         }
1215 }
1216
1217
1218 static void start_dma(struct sync_port *port, const char *data, int count)
1219 {
1220         port->tr_running = 1;
1221         port->out_descr.hw_len = 0;
1222         port->out_descr.next = 0;
1223         port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */
1224         port->out_descr.sw_len = count;
1225         port->out_descr.buf = virt_to_phys(data);
1226         port->out_descr.status = 0;
1227
1228         *port->output_dma_first = virt_to_phys(&port->out_descr);
1229         *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1230         DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n",
1231                 (unsigned long)data, count));
1232 }
1233
1234 static void start_dma_in(struct sync_port *port)
1235 {
1236         int i;
1237         unsigned long buf;
1238         port->writep = port->flip;
1239
1240         if (port->writep > port->flip + port->in_buffer_size) {
1241                 panic("Offset too large in sync serial driver\n");
1242                 return;
1243         }
1244         buf = virt_to_phys(port->in_buffer);
1245         for (i = 0; i < NUM_IN_DESCR; i++) {
1246                 port->in_descr[i].sw_len = port->inbufchunk;
1247                 port->in_descr[i].ctrl = d_int;
1248                 port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]);
1249                 port->in_descr[i].buf = buf;
1250                 port->in_descr[i].hw_len = 0;
1251                 port->in_descr[i].status = 0;
1252                 port->in_descr[i].fifo_len = 0;
1253                 buf += port->inbufchunk;
1254                 prepare_rx_descriptor(&port->in_descr[i]);
1255         }
1256         /* Link the last descriptor to the first */
1257         port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]);
1258         port->in_descr[i-1].ctrl |= d_eol;
1259         port->next_rx_desc = &port->in_descr[0];
1260         port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1];
1261         *port->input_dma_first = virt_to_phys(port->next_rx_desc);
1262         *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start);
1263 }
1264
1265 #ifdef SYNC_SER_DMA
1266 static irqreturn_t tr_interrupt(int irq, void *dev_id)
1267 {
1268         unsigned long ireg = *R_IRQ_MASK2_RD;
1269         struct etrax_dma_descr *descr;
1270         unsigned int sentl;
1271         int handled = 0;
1272         int i;
1273
1274         for (i = 0; i < NUMBER_OF_PORTS; i++) {
1275                 struct sync_port *port = &ports[i];
1276                 if (!port->enabled  || !port->use_dma)
1277                         continue;
1278
1279                 /* IRQ active for the port? */
1280                 if (!(ireg & (1 << port->output_dma_bit)))
1281                         continue;
1282
1283                 handled = 1;
1284
1285                 /* Clear IRQ */
1286                 *port->output_dma_clr_irq =
1287                         IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) |
1288                         IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do);
1289
1290                 descr = &port->out_descr;
1291                 if (!(descr->status & d_stop))
1292                         sentl = descr->sw_len;
1293                 else
1294                         /* Otherwise find amount of data sent here */
1295                         sentl = descr->hw_len;
1296
1297                 port->out_count -= sentl;
1298                 port->outp += sentl;
1299                 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE)
1300                         port->outp = port->out_buffer;
1301                 if (port->out_count) {
1302                         int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp;
1303                         if (c > port->out_count)
1304                                 c = port->out_count;
1305                         DEBUGTXINT(printk(KERN_DEBUG
1306                                 "tx_int DMAWRITE %i %i\n", sentl, c));
1307                         start_dma(port, port->outp, c);
1308                 } else  {
1309                         DEBUGTXINT(printk(KERN_DEBUG
1310                                 "tx_int DMA stop %i\n", sentl));
1311                         port->tr_running = 0;
1312                 }
1313                 /* wake up the waiting process */
1314                 wake_up_interruptible(&port->out_wait_q);
1315         }
1316         return IRQ_RETVAL(handled);
1317 } /* tr_interrupt */
1318
1319 static irqreturn_t rx_interrupt(int irq, void *dev_id)
1320 {
1321         unsigned long ireg = *R_IRQ_MASK2_RD;
1322         int i;
1323         int handled = 0;
1324
1325         for (i = 0; i < NUMBER_OF_PORTS; i++) {
1326                 struct sync_port *port = &ports[i];
1327
1328                 if (!port->enabled || !port->use_dma)
1329                         continue;
1330
1331                 if (!(ireg & (1 << port->input_dma_descr_bit)))
1332                         continue;
1333
1334                 /* Descriptor interrupt */
1335                 handled = 1;
1336                 while (*port->input_dma_descr !=
1337                                 virt_to_phys(port->next_rx_desc)) {
1338                         if (port->writep + port->inbufchunk > port->flip +
1339                                         port->in_buffer_size) {
1340                                 int first_size = port->flip +
1341                                         port->in_buffer_size - port->writep;
1342                                 memcpy(port->writep,
1343                                         phys_to_virt(port->next_rx_desc->buf),
1344                                         first_size);
1345                                 memcpy(port->flip,
1346                                         phys_to_virt(port->next_rx_desc->buf +
1347                                         first_size),
1348                                         port->inbufchunk - first_size);
1349                                 port->writep = port->flip +
1350                                         port->inbufchunk - first_size;
1351                         } else {
1352                                 memcpy(port->writep,
1353                                         phys_to_virt(port->next_rx_desc->buf),
1354                                         port->inbufchunk);
1355                                 port->writep += port->inbufchunk;
1356                                 if (port->writep >= port->flip
1357                                                 + port->in_buffer_size)
1358                                         port->writep = port->flip;
1359                         }
1360                         if (port->writep == port->readp)
1361                                 port->full = 1;
1362                         prepare_rx_descriptor(port->next_rx_desc);
1363                         port->next_rx_desc->ctrl |= d_eol;
1364                         port->prev_rx_desc->ctrl &= ~d_eol;
1365                         port->prev_rx_desc = phys_to_virt((unsigned)
1366                                 port->next_rx_desc);
1367                         port->next_rx_desc = phys_to_virt((unsigned)
1368                                 port->next_rx_desc->next);
1369                         /* Wake up the waiting process */
1370                         wake_up_interruptible(&port->in_wait_q);
1371                         *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD,
1372                                 cmd, restart);
1373                         /* DMA has reached end of descriptor */
1374                         *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR,
1375                                 clr_descr, do);
1376                 }
1377         }
1378         return IRQ_RETVAL(handled);
1379 } /* rx_interrupt */
1380 #endif /* SYNC_SER_DMA */
1381
1382 #ifdef SYNC_SER_MANUAL
1383 static irqreturn_t manual_interrupt(int irq, void *dev_id)
1384 {
1385         int i;
1386         int handled = 0;
1387
1388         for (i = 0; i < NUMBER_OF_PORTS; i++) {
1389                 struct sync_port *port = &ports[i];
1390
1391                 if (!port->enabled || port->use_dma)
1392                         continue;
1393
1394                 /* Data received? */
1395                 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) {
1396                         handled = 1;
1397                         /* Read data */
1398                         switch (port->ctrl_data_shadow &
1399                                 IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) {
1400                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit):
1401                                 *port->writep++ =
1402                                         *(volatile char *)port->data_in;
1403                                 break;
1404                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit):
1405                         {
1406                                 int data = *(unsigned short *)port->data_in;
1407                                 *port->writep = (data & 0x0ff0) >> 4;
1408                                 *(port->writep + 1) = data & 0x0f;
1409                                 port->writep += 2;
1410                                 break;
1411                         }
1412                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit):
1413                                 *(unsigned short *)port->writep =
1414                                         *(volatile unsigned short *)port->data_in;
1415                                 port->writep += 2;
1416                                 break;
1417                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit):
1418                                 *(unsigned int *)port->writep = *port->data_in;
1419                                 port->writep += 3;
1420                                 break;
1421                         case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit):
1422                                 *(unsigned int *)port->writep = *port->data_in;
1423                                 port->writep += 4;
1424                                 break;
1425                         }
1426
1427                         /* Wrap? */
1428                         if (port->writep >= port->flip + port->in_buffer_size)
1429                                 port->writep = port->flip;
1430                         if (port->writep == port->readp) {
1431                                 /* Receive buffer overrun, discard oldest */
1432                                 port->readp++;
1433                                 /* Wrap? */
1434                                 if (port->readp >= port->flip +
1435                                                 port->in_buffer_size)
1436                                         port->readp = port->flip;
1437                         }
1438                         if (sync_data_avail(port) >= port->inbufchunk) {
1439                                 /* Wake up application */
1440                                 wake_up_interruptible(&port->in_wait_q);
1441                         }
1442                 }
1443
1444                 /* Transmitter ready? */
1445                 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) {
1446                         if (port->out_count > 0) {
1447                                 /* More data to send */
1448                                 send_word(port);
1449                         } else {
1450                                 /* Transmission finished */
1451                                 /* Turn off IRQ */
1452                                 *R_IRQ_MASK1_CLR = 1 <<
1453                                         port->transmitter_ready_bit;
1454                                 /* Wake up application */
1455                                 wake_up_interruptible(&port->out_wait_q);
1456                         }
1457                 }
1458         }
1459         return IRQ_RETVAL(handled);
1460 }
1461 #endif
1462
1463 module_init(etrax_sync_serial_init);