arch/c6x/kernel/setup.c

   1 /*
   2  *  Port on Texas Instruments TMS320C6x architecture
   3  *
   4  *  Copyright (C) 2004, 2006, 2009, 2010, 2011 Texas Instruments Incorporated
   5  *  Author: Aurelien Jacquiot (aurelien.jacquiot@jaluna.com)
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 as
   9  *  published by the Free Software Foundation.
  10  */
  11 #include <linux/dma-mapping.h>
  12 #include <linux/memblock.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/clkdev.h>
  15 #include <linux/initrd.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/of_fdt.h>
  19 #include <linux/string.h>
  20 #include <linux/errno.h>
  21 #include <linux/cache.h>
  22 #include <linux/delay.h>
  23 #include <linux/sched.h>
  24 #include <linux/clk.h>
  25 #include <linux/cpu.h>
  26 #include <linux/fs.h>
  27 #include <linux/of.h>
  28 #include <linux/console.h>
  29 #include <linux/screen_info.h>
  30
  31 #include <asm/sections.h>
  32 #include <asm/div64.h>
  33 #include <asm/setup.h>
  34 #include <asm/dscr.h>
  35 #include <asm/clock.h>
  36 #include <asm/soc.h>
  37 #include <asm/special_insns.h>
  38
  39 static const char *c6x_soc_name;
  40
  41 struct screen_info screen_info;
  42
  43 int c6x_num_cores;
  44 EXPORT_SYMBOL_GPL(c6x_num_cores);
  45
  46 unsigned int c6x_silicon_rev;
  47 EXPORT_SYMBOL_GPL(c6x_silicon_rev);
  48
  49 /*
  50  * Device status register. This holds information
  51  * about device configuration needed by some drivers.
  52  */
  53 unsigned int c6x_devstat;
  54 EXPORT_SYMBOL_GPL(c6x_devstat);
  55
  56 /*
  57  * Some SoCs have fuse registers holding a unique MAC
  58  * address. This is parsed out of the device tree with
  59  * the resulting MAC being held here.
  60  */
  61 unsigned char c6x_fuse_mac[6];
  62
  63 unsigned long memory_start;
  64 unsigned long memory_end;
  65 EXPORT_SYMBOL(memory_end);
  66
  67 unsigned long ram_start;
  68 unsigned long ram_end;
  69
  70 /* Uncached memory for DMA consistent use (memdma=) */
  71 static unsigned long dma_start __initdata;
  72 static unsigned long dma_size __initdata;
  73
  74 struct cpuinfo_c6x {
  75         const char *cpu_name;
  76         const char *cpu_voltage;
  77         const char *mmu;
  78         const char *fpu;
  79         char *cpu_rev;
  80         unsigned int core_id;
  81         char __cpu_rev[5];
  82 };
  83
  84 static DEFINE_PER_CPU(struct cpuinfo_c6x, cpu_data);
  85
  86 unsigned int ticks_per_ns_scaled;
  87 EXPORT_SYMBOL(ticks_per_ns_scaled);
  88
  89 unsigned int c6x_core_freq;
  90
  91 static void __init get_cpuinfo(void)
  92 {
  93         unsigned cpu_id, rev_id, csr;
  94         struct clk *coreclk = clk_get_sys(NULL, "core");
  95         unsigned long core_khz;
  96         u64 tmp;
  97         struct cpuinfo_c6x *p;
  98         struct device_node *node;
  99
 100         p = &per_cpu(cpu_data, smp_processor_id());
 101
 102         if (!IS_ERR(coreclk))
 103                 c6x_core_freq = clk_get_rate(coreclk);
 104         else {
 105                 printk(KERN_WARNING
 106                        "Cannot find core clock frequency. Using 700MHz\n");
 107                 c6x_core_freq = 700000000;
 108         }
 109
 110         core_khz = c6x_core_freq / 1000;
 111
 112         tmp = (uint64_t)core_khz << C6X_NDELAY_SCALE;
 113         do_div(tmp, 1000000);
 114         ticks_per_ns_scaled = tmp;
 115
 116         csr = get_creg(CSR);
 117         cpu_id = csr >> 24;
 118         rev_id = (csr >> 16) & 0xff;
 119
 120         p->mmu = "none";
 121         p->fpu = "none";
 122         p->cpu_voltage = "unknown";
 123
 124         switch (cpu_id) {
 125         case 0:
 126                 p->cpu_name = "C67x";
 127                 p->fpu = "yes";
 128                 break;
 129         case 2:
 130                 p->cpu_name = "C62x";
 131                 break;
 132         case 8:
 133                 p->cpu_name = "C64x";
 134                 break;
 135         case 12:
 136                 p->cpu_name = "C64x";
 137                 break;
 138         case 16:
 139                 p->cpu_name = "C64x+";
 140                 p->cpu_voltage = "1.2";
 141                 break;
 142         case 21:
 143                 p->cpu_name = "C66X";
 144                 p->cpu_voltage = "1.2";
 145                 break;
 146         default:
 147                 p->cpu_name = "unknown";
 148                 break;
 149         }
 150
 151         if (cpu_id < 16) {
 152                 switch (rev_id) {
 153                 case 0x1:
 154                         if (cpu_id > 8) {
 155                                 p->cpu_rev = "DM640/DM641/DM642/DM643";
 156                                 p->cpu_voltage = "1.2 - 1.4";
 157                         } else {
 158                                 p->cpu_rev = "C6201";
 159                                 p->cpu_voltage = "2.5";
 160                         }
 161                         break;
 162                 case 0x2:
 163                         p->cpu_rev = "C6201B/C6202/C6211";
 164                         p->cpu_voltage = "1.8";
 165                         break;
 166                 case 0x3:
 167                         p->cpu_rev = "C6202B/C6203/C6204/C6205";
 168                         p->cpu_voltage = "1.5";
 169                         break;
 170                 case 0x201:
 171                         p->cpu_rev = "C6701 revision 0 (early CPU)";
 172                         p->cpu_voltage = "1.8";
 173                         break;
 174                 case 0x202:
 175                         p->cpu_rev = "C6701/C6711/C6712";
 176                         p->cpu_voltage = "1.8";
 177                         break;
 178                 case 0x801:
 179                         p->cpu_rev = "C64x";
 180                         p->cpu_voltage = "1.5";
 181                         break;
 182                 default:
 183                         p->cpu_rev = "unknown";
 184                 }
 185         } else {
 186                 p->cpu_rev = p->__cpu_rev;
 187                 snprintf(p->__cpu_rev, sizeof(p->__cpu_rev), "0x%x", cpu_id);
 188         }
 189
 190         p->core_id = get_coreid();
 191
 192         for_each_of_cpu_node(node)
 193                 ++c6x_num_cores;
 194
 195         node = of_find_node_by_name(NULL, "soc");
 196         if (node) {
 197                 if (of_property_read_string(node, "model", &c6x_soc_name))
 198                         c6x_soc_name = "unknown";
 199                 of_node_put(node);
 200         } else
 201                 c6x_soc_name = "unknown";
 202
 203         printk(KERN_INFO "CPU%d: %s rev %s, %s volts, %uMHz\n",
 204                p->core_id, p->cpu_name, p->cpu_rev,
 205                p->cpu_voltage, c6x_core_freq / 1000000);
 206 }
 207
 208 /*
 209  * Early parsing of the command line
 210  */
 211 static u32 mem_size __initdata;
 212
 213 /* "mem=" parsing. */
 214 static int __init early_mem(char *p)
 215 {
 216         if (!p)
 217                 return -EINVAL;
 218
 219         mem_size = memparse(p, &p);
 220         /* don't remove all of memory when handling "mem={invalid}" */
 221         if (mem_size == 0)
 222                 return -EINVAL;
 223
 224         return 0;
 225 }
 226 early_param("mem", early_mem);
 227
 228 /* "memdma=<size>[@<address>]" parsing. */
 229 static int __init early_memdma(char *p)
 230 {
 231         if (!p)
 232                 return -EINVAL;
 233
 234         dma_size = memparse(p, &p);
 235         if (*p == '@')
 236                 dma_start = memparse(p, &p);
 237
 238         return 0;
 239 }
 240 early_param("memdma", early_memdma);
 241
 242 int __init c6x_add_memory(phys_addr_t start, unsigned long size)
 243 {
 244         static int ram_found __initdata;
 245
 246         /* We only handle one bank (the one with PAGE_OFFSET) for now */
 247         if (ram_found)
 248                 return -EINVAL;
 249
 250         if (start > PAGE_OFFSET || PAGE_OFFSET >= (start + size))
 251                 return 0;
 252
 253         ram_start = start;
 254         ram_end = start + size;
 255
 256         ram_found = 1;
 257         return 0;
 258 }
 259
 260 /*
 261  * Do early machine setup and device tree parsing. This is called very
 262  * early on the boot process.
 263  */
 264 notrace void __init machine_init(unsigned long dt_ptr)
 265 {
 266         void *dtb = __va(dt_ptr);
 267         void *fdt = __dtb_start;
 268
 269         /* interrupts must be masked */
 270         set_creg(IER, 2);
 271
 272         /*
 273          * Set the Interrupt Service Table (IST) to the beginning of the
 274          * vector table.
 275          */
 276         set_ist(_vectors_start);
 277
 278         /*
 279          * dtb is passed in from bootloader.
 280          * fdt is linked in blob.
 281          */
 282         if (dtb && dtb != fdt)
 283                 fdt = dtb;
 284
 285         /* Do some early initialization based on the flat device tree */
 286         early_init_dt_scan(fdt);
 287
 288         parse_early_param();
 289 }
 290
 291 void __init setup_arch(char **cmdline_p)
 292 {
 293         struct memblock_region *reg;
 294
 295         printk(KERN_INFO "Initializing kernel\n");
 296
 297         /* Initialize command line */
 298         *cmdline_p = boot_command_line;
 299
 300         memory_end = ram_end;
 301         memory_end &= ~(PAGE_SIZE - 1);
 302
 303         if (mem_size && (PAGE_OFFSET + PAGE_ALIGN(mem_size)) < memory_end)
 304                 memory_end = PAGE_OFFSET + PAGE_ALIGN(mem_size);
 305
 306         /* add block that this kernel can use */
 307         memblock_add(PAGE_OFFSET, memory_end - PAGE_OFFSET);
 308
 309         /* reserve kernel text/data/bss */
 310         memblock_reserve(PAGE_OFFSET,
 311                          PAGE_ALIGN((unsigned long)&_end - PAGE_OFFSET));
 312
 313         if (dma_size) {
 314                 /* align to cacheability granularity */
 315                 dma_size = CACHE_REGION_END(dma_size);
 316
 317                 if (!dma_start)
 318                         dma_start = memory_end - dma_size;
 319
 320                 /* align to cacheability granularity */
 321                 dma_start = CACHE_REGION_START(dma_start);
 322
 323                 /* reserve DMA memory taken from kernel memory */
 324                 if (memblock_is_region_memory(dma_start, dma_size))
 325                         memblock_reserve(dma_start, dma_size);
 326         }
 327
 328         memory_start = PAGE_ALIGN((unsigned int) &_end);
 329
 330         printk(KERN_INFO "Memory Start=%08lx, Memory End=%08lx\n",
 331                memory_start, memory_end);
 332
 333 #ifdef CONFIG_BLK_DEV_INITRD
 334         /*
 335          * Reserve initrd memory if in kernel memory.
 336          */
 337         if (initrd_start < initrd_end)
 338                 if (memblock_is_region_memory(initrd_start,
 339                                               initrd_end - initrd_start))
 340                         memblock_reserve(initrd_start,
 341                                          initrd_end - initrd_start);
 342 #endif
 343
 344         init_mm.start_code = (unsigned long) &_stext;
 345         init_mm.end_code   = (unsigned long) &_etext;
 346         init_mm.end_data   = memory_start;
 347         init_mm.brk        = memory_start;
 348
 349         unflatten_and_copy_device_tree();
 350
 351         c6x_cache_init();
 352
 353         /* Set the whole external memory as non-cacheable */
 354         disable_caching(ram_start, ram_end - 1);
 355
 356         /* Set caching of external RAM used by Linux */
 357         for_each_memblock(memory, reg)
 358                 enable_caching(CACHE_REGION_START(reg->base),
 359                                CACHE_REGION_START(reg->base + reg->size - 1));
 360
 361 #ifdef CONFIG_BLK_DEV_INITRD
 362         /*
 363          * Enable caching for initrd which falls outside kernel memory.
 364          */
 365         if (initrd_start < initrd_end) {
 366                 if (!memblock_is_region_memory(initrd_start,
 367                                                initrd_end - initrd_start))
 368                         enable_caching(CACHE_REGION_START(initrd_start),
 369                                        CACHE_REGION_START(initrd_end - 1));
 370         }
 371 #endif
 372
 373         /*
 374          * Disable caching for dma coherent memory taken from kernel memory.
 375          */
 376         if (dma_size && memblock_is_region_memory(dma_start, dma_size))
 377                 disable_caching(dma_start,
 378                                 CACHE_REGION_START(dma_start + dma_size - 1));
 379
 380         /* Initialize the coherent memory allocator */
 381         coherent_mem_init(dma_start, dma_size);
 382
 383         max_low_pfn = PFN_DOWN(memory_end);
 384         min_low_pfn = PFN_UP(memory_start);
 385         max_pfn = max_low_pfn;
 386         max_mapnr = max_low_pfn - min_low_pfn;
 387
 388         /* Get kmalloc into gear */
 389         paging_init();
 390
 391         /*
 392          * Probe for Device State Configuration Registers.
 393          * We have to do this early in case timer needs to be enabled
 394          * through DSCR.
 395          */
 396         dscr_probe();
 397
 398         /* We do this early for timer and core clock frequency */
 399         c64x_setup_clocks();
 400
 401         /* Get CPU info */
 402         get_cpuinfo();
 403
 404 #if defined(CONFIG_VT) && defined(CONFIG_DUMMY_CONSOLE)
 405         conswitchp = &dummy_con;
 406 #endif
 407 }
 408
 409 #define cpu_to_ptr(n) ((void *)((long)(n)+1))
 410 #define ptr_to_cpu(p) ((long)(p) - 1)
 411
 412 static int show_cpuinfo(struct seq_file *m, void *v)
 413 {
 414         int n = ptr_to_cpu(v);
 415         struct cpuinfo_c6x *p = &per_cpu(cpu_data, n);
 416
 417         if (n == 0) {
 418                 seq_printf(m,
 419                            "soc\t\t: %s\n"
 420                            "soc revision\t: 0x%x\n"
 421                            "soc cores\t: %d\n",
 422                            c6x_soc_name, c6x_silicon_rev, c6x_num_cores);
 423         }
 424
 425         seq_printf(m,
 426                    "\n"
 427                    "processor\t: %d\n"
 428                    "cpu\t\t: %s\n"
 429                    "core revision\t: %s\n"
 430                    "core voltage\t: %s\n"
 431                    "core id\t\t: %d\n"
 432                    "mmu\t\t: %s\n"
 433                    "fpu\t\t: %s\n"
 434                    "cpu MHz\t\t: %u\n"
 435                    "bogomips\t: %lu.%02lu\n\n",
 436                    n,
 437                    p->cpu_name, p->cpu_rev, p->cpu_voltage,
 438                    p->core_id, p->mmu, p->fpu,
 439                    (c6x_core_freq + 500000) / 1000000,
 440                    (loops_per_jiffy/(500000/HZ)),
 441                    (loops_per_jiffy/(5000/HZ))%100);
 442
 443         return 0;
 444 }
 445
 446 static void *c_start(struct seq_file *m, loff_t *pos)
 447 {
 448         return *pos < nr_cpu_ids ? cpu_to_ptr(*pos) : NULL;
 449 }
 450 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 451 {
 452         ++*pos;
 453         return NULL;
 454 }
 455 static void c_stop(struct seq_file *m, void *v)
 456 {
 457 }
 458
 459 const struct seq_operations cpuinfo_op = {
 460         c_start,
 461         c_stop,
 462         c_next,
 463         show_cpuinfo
 464 };
 465
 466 static struct cpu cpu_devices[NR_CPUS];
 467
 468 static int __init topology_init(void)
 469 {
 470         int i;
 471
 472         for_each_present_cpu(i)
 473                 register_cpu(&cpu_devices[i], i);
 474
 475         return 0;
 476 }
 477
 478 subsys_initcall(topology_init);