arch/blackfin/mach-common/ints-priority.c

   1 /*
   2  * Set up the interrupt priorities
   3  *
   4  * Copyright  2004-2009 Analog Devices Inc.
   5  *                 2003 Bas Vermeulen <bas@buyways.nl>
   6  *                 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
   7  *            2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
   8  *                 1999 D. Jeff Dionne <jeff@uclinux.org>
   9  *                 1996 Roman Zippel
  10  *
  11  * Licensed under the GPL-2
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel_stat.h>
  16 #include <linux/seq_file.h>
  17 #include <linux/irq.h>
  18 #include <linux/sched.h>
  19 #include <linux/syscore_ops.h>
  20 #include <asm/delay.h>
  21 #ifdef CONFIG_IPIPE
  22 #include <linux/ipipe.h>
  23 #endif
  24 #include <asm/traps.h>
  25 #include <asm/blackfin.h>
  26 #include <asm/gpio.h>
  27 #include <asm/irq_handler.h>
  28 #include <asm/dpmc.h>
  29 #include <asm/traps.h>
  30
  31 /*
  32  * NOTES:
  33  * - we have separated the physical Hardware interrupt from the
  34  * levels that the LINUX kernel sees (see the description in irq.h)
  35  * -
  36  */
  37
  38 #ifndef CONFIG_SMP
  39 /* Initialize this to an actual value to force it into the .data
  40  * section so that we know it is properly initialized at entry into
  41  * the kernel but before bss is initialized to zero (which is where
  42  * it would live otherwise).  The 0x1f magic represents the IRQs we
  43  * cannot actually mask out in hardware.
  44  */
  45 unsigned long bfin_irq_flags = 0x1f;
  46 EXPORT_SYMBOL(bfin_irq_flags);
  47 #endif
  48
  49 #ifdef CONFIG_PM
  50 unsigned long bfin_sic_iwr[3];  /* Up to 3 SIC_IWRx registers */
  51 unsigned vr_wakeup;
  52 #endif
  53
  54 #ifndef SEC_GCTL
  55 static struct ivgx {
  56         /* irq number for request_irq, available in mach-bf5xx/irq.h */
  57         unsigned int irqno;
  58         /* corresponding bit in the SIC_ISR register */
  59         unsigned int isrflag;
  60 } ivg_table[NR_PERI_INTS];
  61
  62 static struct ivg_slice {
  63         /* position of first irq in ivg_table for given ivg */
  64         struct ivgx *ifirst;
  65         struct ivgx *istop;
  66 } ivg7_13[IVG13 - IVG7 + 1];
  67
  68
  69 /*
  70  * Search SIC_IAR and fill tables with the irqvalues
  71  * and their positions in the SIC_ISR register.
  72  */
  73 static void __init search_IAR(void)
  74 {
  75         unsigned ivg, irq_pos = 0;
  76         for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) {
  77                 int irqN;
  78
  79                 ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos];
  80
  81                 for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) {
  82                         int irqn;
  83                         u32 iar =
  84                                 bfin_read32((unsigned long *)SIC_IAR0 +
  85 #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \
  86         defined(CONFIG_BF538) || defined(CONFIG_BF539)
  87                                 ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4))
  88 #else
  89                                 (irqN >> 3)
  90 #endif
  91                                 );
  92                         for (irqn = irqN; irqn < irqN + 4; ++irqn) {
  93                                 int iar_shift = (irqn & 7) * 4;
  94                                 if (ivg == (0xf & (iar >> iar_shift))) {
  95                                         ivg_table[irq_pos].irqno = IVG7 + irqn;
  96                                         ivg_table[irq_pos].isrflag = 1 << (irqn % 32);
  97                                         ivg7_13[ivg].istop++;
  98                                         irq_pos++;
  99                                 }
 100                         }
 101                 }
 102         }
 103 }
 104 #endif
 105
 106 /*
 107  * This is for core internal IRQs
 108  */
 109 void bfin_ack_noop(struct irq_data *d)
 110 {
 111         /* Dummy function.  */
 112 }
 113
 114 static void bfin_core_mask_irq(struct irq_data *d)
 115 {
 116         bfin_irq_flags &= ~(1 << d->irq);
 117         if (!hard_irqs_disabled())
 118                 hard_local_irq_enable();
 119 }
 120
 121 static void bfin_core_unmask_irq(struct irq_data *d)
 122 {
 123         bfin_irq_flags |= 1 << d->irq;
 124         /*
 125          * If interrupts are enabled, IMASK must contain the same value
 126          * as bfin_irq_flags.  Make sure that invariant holds.  If interrupts
 127          * are currently disabled we need not do anything; one of the
 128          * callers will take care of setting IMASK to the proper value
 129          * when reenabling interrupts.
 130          * local_irq_enable just does "STI bfin_irq_flags", so it's exactly
 131          * what we need.
 132          */
 133         if (!hard_irqs_disabled())
 134                 hard_local_irq_enable();
 135         return;
 136 }
 137
 138 #ifndef SEC_GCTL
 139 void bfin_internal_mask_irq(unsigned int irq)
 140 {
 141         unsigned long flags = hard_local_irq_save();
 142 #ifdef SIC_IMASK0
 143         unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
 144         unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
 145         bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
 146                         ~(1 << mask_bit));
 147 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
 148         bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
 149                         ~(1 << mask_bit));
 150 # endif
 151 #else
 152         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
 153                         ~(1 << BFIN_SYSIRQ(irq)));
 154 #endif /* end of SIC_IMASK0 */
 155         hard_local_irq_restore(flags);
 156 }
 157
 158 static void bfin_internal_mask_irq_chip(struct irq_data *d)
 159 {
 160         bfin_internal_mask_irq(d->irq);
 161 }
 162
 163 #ifdef CONFIG_SMP
 164 void bfin_internal_unmask_irq_affinity(unsigned int irq,
 165                 const struct cpumask *affinity)
 166 #else
 167 void bfin_internal_unmask_irq(unsigned int irq)
 168 #endif
 169 {
 170         unsigned long flags = hard_local_irq_save();
 171
 172 #ifdef SIC_IMASK0
 173         unsigned mask_bank = BFIN_SYSIRQ(irq) / 32;
 174         unsigned mask_bit = BFIN_SYSIRQ(irq) % 32;
 175 # ifdef CONFIG_SMP
 176         if (cpumask_test_cpu(0, affinity))
 177 # endif
 178                 bfin_write_SIC_IMASK(mask_bank,
 179                                 bfin_read_SIC_IMASK(mask_bank) |
 180                                 (1 << mask_bit));
 181 # ifdef CONFIG_SMP
 182         if (cpumask_test_cpu(1, affinity))
 183                 bfin_write_SICB_IMASK(mask_bank,
 184                                 bfin_read_SICB_IMASK(mask_bank) |
 185                                 (1 << mask_bit));
 186 # endif
 187 #else
 188         bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
 189                         (1 << BFIN_SYSIRQ(irq)));
 190 #endif
 191         hard_local_irq_restore(flags);
 192 }
 193
 194 #ifdef CONFIG_SMP
 195 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 196 {
 197         bfin_internal_unmask_irq_affinity(d->irq, d->affinity);
 198 }
 199
 200 static int bfin_internal_set_affinity(struct irq_data *d,
 201                                       const struct cpumask *mask, bool force)
 202 {
 203         bfin_internal_mask_irq(d->irq);
 204         bfin_internal_unmask_irq_affinity(d->irq, mask);
 205
 206         return 0;
 207 }
 208 #else
 209 static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 210 {
 211         bfin_internal_unmask_irq(d->irq);
 212 }
 213 #endif
 214
 215 #if defined(CONFIG_PM)
 216 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 217 {
 218         u32 bank, bit, wakeup = 0;
 219         unsigned long flags;
 220         bank = BFIN_SYSIRQ(irq) / 32;
 221         bit = BFIN_SYSIRQ(irq) % 32;
 222
 223         switch (irq) {
 224 #ifdef IRQ_RTC
 225         case IRQ_RTC:
 226         wakeup |= WAKE;
 227         break;
 228 #endif
 229 #ifdef IRQ_CAN0_RX
 230         case IRQ_CAN0_RX:
 231         wakeup |= CANWE;
 232         break;
 233 #endif
 234 #ifdef IRQ_CAN1_RX
 235         case IRQ_CAN1_RX:
 236         wakeup |= CANWE;
 237         break;
 238 #endif
 239 #ifdef IRQ_USB_INT0
 240         case IRQ_USB_INT0:
 241         wakeup |= USBWE;
 242         break;
 243 #endif
 244 #ifdef CONFIG_BF54x
 245         case IRQ_CNT:
 246         wakeup |= ROTWE;
 247         break;
 248 #endif
 249         default:
 250         break;
 251         }
 252
 253         flags = hard_local_irq_save();
 254
 255         if (state) {
 256                 bfin_sic_iwr[bank] |= (1 << bit);
 257                 vr_wakeup  |= wakeup;
 258
 259         } else {
 260                 bfin_sic_iwr[bank] &= ~(1 << bit);
 261                 vr_wakeup  &= ~wakeup;
 262         }
 263
 264         hard_local_irq_restore(flags);
 265
 266         return 0;
 267 }
 268
 269 static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
 270 {
 271         return bfin_internal_set_wake(d->irq, state);
 272 }
 273 #else
 274 inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 275 {
 276         return 0;
 277 }
 278 # define bfin_internal_set_wake_chip NULL
 279 #endif
 280
 281 #else /* SEC_GCTL */
 282 static void bfin_sec_preflow_handler(struct irq_data *d)
 283 {
 284         unsigned long flags = hard_local_irq_save();
 285         unsigned int sid = BFIN_SYSIRQ(d->irq);
 286
 287         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 288
 289         hard_local_irq_restore(flags);
 290 }
 291
 292 static void bfin_sec_mask_ack_irq(struct irq_data *d)
 293 {
 294         unsigned long flags = hard_local_irq_save();
 295         unsigned int sid = BFIN_SYSIRQ(d->irq);
 296
 297         bfin_write_SEC_SCI(0, SEC_CSID, sid);
 298
 299         hard_local_irq_restore(flags);
 300 }
 301
 302 static void bfin_sec_unmask_irq(struct irq_data *d)
 303 {
 304         unsigned long flags = hard_local_irq_save();
 305         unsigned int sid = BFIN_SYSIRQ(d->irq);
 306
 307         bfin_write32(SEC_END, sid);
 308
 309         hard_local_irq_restore(flags);
 310 }
 311
 312 static void bfin_sec_enable_ssi(unsigned int sid)
 313 {
 314         unsigned long flags = hard_local_irq_save();
 315         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 316
 317         reg_sctl |= SEC_SCTL_SRC_EN;
 318         bfin_write_SEC_SCTL(sid, reg_sctl);
 319
 320         hard_local_irq_restore(flags);
 321 }
 322
 323 static void bfin_sec_disable_ssi(unsigned int sid)
 324 {
 325         unsigned long flags = hard_local_irq_save();
 326         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 327
 328         reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN);
 329         bfin_write_SEC_SCTL(sid, reg_sctl);
 330
 331         hard_local_irq_restore(flags);
 332 }
 333
 334 static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid)
 335 {
 336         unsigned long flags = hard_local_irq_save();
 337         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 338
 339         reg_sctl &= ((uint32_t)~SEC_SCTL_CTG);
 340         bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG));
 341
 342         hard_local_irq_restore(flags);
 343 }
 344
 345 static void bfin_sec_enable_sci(unsigned int sid)
 346 {
 347         unsigned long flags = hard_local_irq_save();
 348         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 349
 350         if (sid == BFIN_SYSIRQ(IRQ_WATCH0))
 351                 reg_sctl |= SEC_SCTL_FAULT_EN;
 352         else
 353                 reg_sctl |= SEC_SCTL_INT_EN;
 354         bfin_write_SEC_SCTL(sid, reg_sctl);
 355
 356         hard_local_irq_restore(flags);
 357 }
 358
 359 static void bfin_sec_disable_sci(unsigned int sid)
 360 {
 361         unsigned long flags = hard_local_irq_save();
 362         uint32_t reg_sctl = bfin_read_SEC_SCTL(sid);
 363
 364         reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN);
 365         bfin_write_SEC_SCTL(sid, reg_sctl);
 366
 367         hard_local_irq_restore(flags);
 368 }
 369
 370 static void bfin_sec_enable(struct irq_data *d)
 371 {
 372         unsigned long flags = hard_local_irq_save();
 373         unsigned int sid = BFIN_SYSIRQ(d->irq);
 374
 375         bfin_sec_enable_sci(sid);
 376         bfin_sec_enable_ssi(sid);
 377
 378         hard_local_irq_restore(flags);
 379 }
 380
 381 static void bfin_sec_disable(struct irq_data *d)
 382 {
 383         unsigned long flags = hard_local_irq_save();
 384         unsigned int sid = BFIN_SYSIRQ(d->irq);
 385
 386         bfin_sec_disable_sci(sid);
 387         bfin_sec_disable_ssi(sid);
 388
 389         hard_local_irq_restore(flags);
 390 }
 391
 392 static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
 393 {
 394         unsigned long flags = hard_local_irq_save();
 395         uint32_t reg_sctl;
 396         int i;
 397
 398         bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
 399
 400         for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
 401                 reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
 402                 reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
 403                 bfin_write_SEC_SCTL(i, reg_sctl);
 404         }
 405
 406         hard_local_irq_restore(flags);
 407 }
 408
 409 void bfin_sec_raise_irq(unsigned int irq)
 410 {
 411         unsigned long flags = hard_local_irq_save();
 412         unsigned int sid = BFIN_SYSIRQ(irq);
 413
 414         bfin_write32(SEC_RAISE, sid);
 415
 416         hard_local_irq_restore(flags);
 417 }
 418
 419 static void init_software_driven_irq(void)
 420 {
 421         bfin_sec_set_ssi_coreid(34, 0);
 422         bfin_sec_set_ssi_coreid(35, 1);
 423
 424         bfin_sec_enable_sci(35);
 425         bfin_sec_enable_ssi(35);
 426         bfin_sec_set_ssi_coreid(36, 0);
 427         bfin_sec_set_ssi_coreid(37, 1);
 428         bfin_sec_enable_sci(37);
 429         bfin_sec_enable_ssi(37);
 430 }
 431
 432 void bfin_sec_resume(void)
 433 {
 434         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
 435         udelay(100);
 436         bfin_write_SEC_GCTL(SEC_GCTL_EN);
 437         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
 438 }
 439
 440 void handle_sec_sfi_fault(uint32_t gstat)
 441 {
 442
 443 }
 444
 445 void handle_sec_sci_fault(uint32_t gstat)
 446 {
 447         uint32_t core_id;
 448         uint32_t cstat;
 449
 450         core_id = gstat & SEC_GSTAT_SCI;
 451         cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT);
 452         if (cstat & SEC_CSTAT_ERR) {
 453                 switch (cstat & SEC_CSTAT_ERRC) {
 454                 case SEC_CSTAT_ACKERR:
 455                         printk(KERN_DEBUG "sec ack err\n");
 456                         break;
 457                 default:
 458                         printk(KERN_DEBUG "sec sci unknow err\n");
 459                 }
 460         }
 461
 462 }
 463
 464 void handle_sec_ssi_fault(uint32_t gstat)
 465 {
 466         uint32_t sid;
 467         uint32_t sstat;
 468
 469         sid = gstat & SEC_GSTAT_SID;
 470         sstat = bfin_read_SEC_SSTAT(sid);
 471
 472 }
 473
 474 void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
 475 {
 476         uint32_t sec_gstat;
 477
 478         raw_spin_lock(&desc->lock);
 479
 480         sec_gstat = bfin_read32(SEC_GSTAT);
 481         if (sec_gstat & SEC_GSTAT_ERR) {
 482
 483                 switch (sec_gstat & SEC_GSTAT_ERRC) {
 484                 case 0:
 485                         handle_sec_sfi_fault(sec_gstat);
 486                         break;
 487                 case SEC_GSTAT_SCIERR:
 488                         handle_sec_sci_fault(sec_gstat);
 489                         break;
 490                 case SEC_GSTAT_SSIERR:
 491                         handle_sec_ssi_fault(sec_gstat);
 492                         break;
 493                 }
 494
 495
 496         }
 497
 498         raw_spin_unlock(&desc->lock);
 499
 500         handle_fasteoi_irq(irq, desc);
 501 }
 502
 503 void handle_core_fault(unsigned int irq, struct irq_desc *desc)
 504 {
 505         struct pt_regs *fp = get_irq_regs();
 506
 507         raw_spin_lock(&desc->lock);
 508
 509         switch (irq) {
 510         case IRQ_C0_DBL_FAULT:
 511                 double_fault_c(fp);
 512                 break;
 513         case IRQ_C0_HW_ERR:
 514                 dump_bfin_process(fp);
 515                 dump_bfin_mem(fp);
 516                 show_regs(fp);
 517                 printk(KERN_NOTICE "Kernel Stack\n");
 518                 show_stack(current, NULL);
 519                 print_modules();
 520                 panic("Core 0 hardware error");
 521                 break;
 522         case IRQ_C0_NMI_L1_PARITY_ERR:
 523                 panic("Core 0 NMI L1 parity error");
 524                 break;
 525         default:
 526                 panic("Core 1 fault %d occurs unexpectedly", irq);
 527         }
 528
 529         raw_spin_unlock(&desc->lock);
 530 }
 531 #endif /* SEC_GCTL */
 532
 533 static struct irq_chip bfin_core_irqchip = {
 534         .name = "CORE",
 535         .irq_mask = bfin_core_mask_irq,
 536         .irq_unmask = bfin_core_unmask_irq,
 537 };
 538
 539 #ifndef SEC_GCTL
 540 static struct irq_chip bfin_internal_irqchip = {
 541         .name = "INTN",
 542         .irq_mask = bfin_internal_mask_irq_chip,
 543         .irq_unmask = bfin_internal_unmask_irq_chip,
 544         .irq_disable = bfin_internal_mask_irq_chip,
 545         .irq_enable = bfin_internal_unmask_irq_chip,
 546 #ifdef CONFIG_SMP
 547         .irq_set_affinity = bfin_internal_set_affinity,
 548 #endif
 549         .irq_set_wake = bfin_internal_set_wake_chip,
 550 };
 551 #else
 552 static struct irq_chip bfin_sec_irqchip = {
 553         .name = "SEC",
 554         .irq_mask_ack = bfin_sec_mask_ack_irq,
 555         .irq_mask = bfin_sec_mask_ack_irq,
 556         .irq_unmask = bfin_sec_unmask_irq,
 557         .irq_eoi = bfin_sec_unmask_irq,
 558         .irq_disable = bfin_sec_disable,
 559         .irq_enable = bfin_sec_enable,
 560 };
 561 #endif
 562
 563 void bfin_handle_irq(unsigned irq)
 564 {
 565 #ifdef CONFIG_IPIPE
 566         struct pt_regs regs;    /* Contents not used. */
 567         ipipe_trace_irq_entry(irq);
 568         __ipipe_handle_irq(irq, &regs);
 569         ipipe_trace_irq_exit(irq);
 570 #else /* !CONFIG_IPIPE */
 571         generic_handle_irq(irq);
 572 #endif  /* !CONFIG_IPIPE */
 573 }
 574
 575 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
 576 static int mac_stat_int_mask;
 577
 578 static void bfin_mac_status_ack_irq(unsigned int irq)
 579 {
 580         switch (irq) {
 581         case IRQ_MAC_MMCINT:
 582                 bfin_write_EMAC_MMC_TIRQS(
 583                         bfin_read_EMAC_MMC_TIRQE() &
 584                         bfin_read_EMAC_MMC_TIRQS());
 585                 bfin_write_EMAC_MMC_RIRQS(
 586                         bfin_read_EMAC_MMC_RIRQE() &
 587                         bfin_read_EMAC_MMC_RIRQS());
 588                 break;
 589         case IRQ_MAC_RXFSINT:
 590                 bfin_write_EMAC_RX_STKY(
 591                         bfin_read_EMAC_RX_IRQE() &
 592                         bfin_read_EMAC_RX_STKY());
 593                 break;
 594         case IRQ_MAC_TXFSINT:
 595                 bfin_write_EMAC_TX_STKY(
 596                         bfin_read_EMAC_TX_IRQE() &
 597                         bfin_read_EMAC_TX_STKY());
 598                 break;
 599         case IRQ_MAC_WAKEDET:
 600                  bfin_write_EMAC_WKUP_CTL(
 601                         bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS);
 602                 break;
 603         default:
 604                 /* These bits are W1C */
 605                 bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT));
 606                 break;
 607         }
 608 }
 609
 610 static void bfin_mac_status_mask_irq(struct irq_data *d)
 611 {
 612         unsigned int irq = d->irq;
 613
 614         mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
 615 #ifdef BF537_FAMILY
 616         switch (irq) {
 617         case IRQ_MAC_PHYINT:
 618                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
 619                 break;
 620         default:
 621                 break;
 622         }
 623 #else
 624         if (!mac_stat_int_mask)
 625                 bfin_internal_mask_irq(IRQ_MAC_ERROR);
 626 #endif
 627         bfin_mac_status_ack_irq(irq);
 628 }
 629
 630 static void bfin_mac_status_unmask_irq(struct irq_data *d)
 631 {
 632         unsigned int irq = d->irq;
 633
 634 #ifdef BF537_FAMILY
 635         switch (irq) {
 636         case IRQ_MAC_PHYINT:
 637                 bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
 638                 break;
 639         default:
 640                 break;
 641         }
 642 #else
 643         if (!mac_stat_int_mask)
 644                 bfin_internal_unmask_irq(IRQ_MAC_ERROR);
 645 #endif
 646         mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT);
 647 }
 648
 649 #ifdef CONFIG_PM
 650 int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
 651 {
 652 #ifdef BF537_FAMILY
 653         return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
 654 #else
 655         return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
 656 #endif
 657 }
 658 #else
 659 # define bfin_mac_status_set_wake NULL
 660 #endif
 661
 662 static struct irq_chip bfin_mac_status_irqchip = {
 663         .name = "MACST",
 664         .irq_mask = bfin_mac_status_mask_irq,
 665         .irq_unmask = bfin_mac_status_unmask_irq,
 666         .irq_set_wake = bfin_mac_status_set_wake,
 667 };
 668
 669 void bfin_demux_mac_status_irq(unsigned int int_err_irq,
 670                                struct irq_desc *inta_desc)
 671 {
 672         int i, irq = 0;
 673         u32 status = bfin_read_EMAC_SYSTAT();
 674
 675         for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++)
 676                 if (status & (1L << i)) {
 677                         irq = IRQ_MAC_PHYINT + i;
 678                         break;
 679                 }
 680
 681         if (irq) {
 682                 if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) {
 683                         bfin_handle_irq(irq);
 684                 } else {
 685                         bfin_mac_status_ack_irq(irq);
 686                         pr_debug("IRQ %d:"
 687                                         " MASKED MAC ERROR INTERRUPT ASSERTED\n",
 688                                         irq);
 689                 }
 690         } else
 691                 printk(KERN_ERR
 692                                 "%s : %s : LINE %d :\nIRQ ?: MAC ERROR"
 693                                 " INTERRUPT ASSERTED BUT NO SOURCE FOUND"
 694                                 "(EMAC_SYSTAT=0x%X)\n",
 695                                 __func__, __FILE__, __LINE__, status);
 696 }
 697 #endif
 698
 699 static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle)
 700 {
 701 #ifdef CONFIG_IPIPE
 702         handle = handle_level_irq;
 703 #endif
 704         __irq_set_handler_locked(irq, handle);
 705 }
 706
 707 #ifdef CONFIG_GPIO_ADI
 708
 709 static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS);
 710
 711 static void bfin_gpio_ack_irq(struct irq_data *d)
 712 {
 713         /* AFAIK ack_irq in case mask_ack is provided
 714          * get's only called for edge sense irqs
 715          */
 716         set_gpio_data(irq_to_gpio(d->irq), 0);
 717 }
 718
 719 static void bfin_gpio_mask_ack_irq(struct irq_data *d)
 720 {
 721         unsigned int irq = d->irq;
 722         u32 gpionr = irq_to_gpio(irq);
 723
 724         if (!irqd_is_level_type(d))
 725                 set_gpio_data(gpionr, 0);
 726
 727         set_gpio_maska(gpionr, 0);
 728 }
 729
 730 static void bfin_gpio_mask_irq(struct irq_data *d)
 731 {
 732         set_gpio_maska(irq_to_gpio(d->irq), 0);
 733 }
 734
 735 static void bfin_gpio_unmask_irq(struct irq_data *d)
 736 {
 737         set_gpio_maska(irq_to_gpio(d->irq), 1);
 738 }
 739
 740 static unsigned int bfin_gpio_irq_startup(struct irq_data *d)
 741 {
 742         u32 gpionr = irq_to_gpio(d->irq);
 743
 744         if (__test_and_set_bit(gpionr, gpio_enabled))
 745                 bfin_gpio_irq_prepare(gpionr);
 746
 747         bfin_gpio_unmask_irq(d);
 748
 749         return 0;
 750 }
 751
 752 static void bfin_gpio_irq_shutdown(struct irq_data *d)
 753 {
 754         u32 gpionr = irq_to_gpio(d->irq);
 755
 756         bfin_gpio_mask_irq(d);
 757         __clear_bit(gpionr, gpio_enabled);
 758         bfin_gpio_irq_free(gpionr);
 759 }
 760
 761 static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 762 {
 763         unsigned int irq = d->irq;
 764         int ret;
 765         char buf[16];
 766         u32 gpionr = irq_to_gpio(irq);
 767
 768         if (type == IRQ_TYPE_PROBE) {
 769                 /* only probe unenabled GPIO interrupt lines */
 770                 if (test_bit(gpionr, gpio_enabled))
 771                         return 0;
 772                 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
 773         }
 774
 775         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
 776                     IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
 777
 778                 snprintf(buf, 16, "gpio-irq%d", irq);
 779                 ret = bfin_gpio_irq_request(gpionr, buf);
 780                 if (ret)
 781                         return ret;
 782
 783                 if (__test_and_set_bit(gpionr, gpio_enabled))
 784                         bfin_gpio_irq_prepare(gpionr);
 785
 786         } else {
 787                 __clear_bit(gpionr, gpio_enabled);
 788                 return 0;
 789         }
 790
 791         set_gpio_inen(gpionr, 0);
 792         set_gpio_dir(gpionr, 0);
 793
 794         if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 795             == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 796                 set_gpio_both(gpionr, 1);
 797         else
 798                 set_gpio_both(gpionr, 0);
 799
 800         if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
 801                 set_gpio_polar(gpionr, 1);      /* low or falling edge denoted by one */
 802         else
 803                 set_gpio_polar(gpionr, 0);      /* high or rising edge denoted by zero */
 804
 805         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
 806                 set_gpio_edge(gpionr, 1);
 807                 set_gpio_inen(gpionr, 1);
 808                 set_gpio_data(gpionr, 0);
 809
 810         } else {
 811                 set_gpio_edge(gpionr, 0);
 812                 set_gpio_inen(gpionr, 1);
 813         }
 814
 815         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
 816                 bfin_set_irq_handler(irq, handle_edge_irq);
 817         else
 818                 bfin_set_irq_handler(irq, handle_level_irq);
 819
 820         return 0;
 821 }
 822
 823 static void bfin_demux_gpio_block(unsigned int irq)
 824 {
 825         unsigned int gpio, mask;
 826
 827         gpio = irq_to_gpio(irq);
 828         mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
 829
 830         while (mask) {
 831                 if (mask & 1)
 832                         bfin_handle_irq(irq);
 833                 irq++;
 834                 mask >>= 1;
 835         }
 836 }
 837
 838 void bfin_demux_gpio_irq(unsigned int inta_irq,
 839                         struct irq_desc *desc)
 840 {
 841         unsigned int irq;
 842
 843         switch (inta_irq) {
 844 #if defined(BF537_FAMILY)
 845         case IRQ_PF_INTA_PG_INTA:
 846                 bfin_demux_gpio_block(IRQ_PF0);
 847                 irq = IRQ_PG0;
 848                 break;
 849         case IRQ_PH_INTA_MAC_RX:
 850                 irq = IRQ_PH0;
 851                 break;
 852 #elif defined(BF533_FAMILY)
 853         case IRQ_PROG_INTA:
 854                 irq = IRQ_PF0;
 855                 break;
 856 #elif defined(BF538_FAMILY)
 857         case IRQ_PORTF_INTA:
 858                 irq = IRQ_PF0;
 859                 break;
 860 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
 861         case IRQ_PORTF_INTA:
 862                 irq = IRQ_PF0;
 863                 break;
 864         case IRQ_PORTG_INTA:
 865                 irq = IRQ_PG0;
 866                 break;
 867         case IRQ_PORTH_INTA:
 868                 irq = IRQ_PH0;
 869                 break;
 870 #elif defined(CONFIG_BF561)
 871         case IRQ_PROG0_INTA:
 872                 irq = IRQ_PF0;
 873                 break;
 874         case IRQ_PROG1_INTA:
 875                 irq = IRQ_PF16;
 876                 break;
 877         case IRQ_PROG2_INTA:
 878                 irq = IRQ_PF32;
 879                 break;
 880 #endif
 881         default:
 882                 BUG();
 883                 return;
 884         }
 885
 886         bfin_demux_gpio_block(irq);
 887 }
 888
 889 #ifdef CONFIG_PM
 890
 891 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 892 {
 893         return bfin_gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
 894 }
 895
 896 #else
 897
 898 # define bfin_gpio_set_wake NULL
 899
 900 #endif
 901
 902 static struct irq_chip bfin_gpio_irqchip = {
 903         .name = "GPIO",
 904         .irq_ack = bfin_gpio_ack_irq,
 905         .irq_mask = bfin_gpio_mask_irq,
 906         .irq_mask_ack = bfin_gpio_mask_ack_irq,
 907         .irq_unmask = bfin_gpio_unmask_irq,
 908         .irq_disable = bfin_gpio_mask_irq,
 909         .irq_enable = bfin_gpio_unmask_irq,
 910         .irq_set_type = bfin_gpio_irq_type,
 911         .irq_startup = bfin_gpio_irq_startup,
 912         .irq_shutdown = bfin_gpio_irq_shutdown,
 913         .irq_set_wake = bfin_gpio_set_wake,
 914 };
 915
 916 #endif
 917
 918 #ifdef CONFIG_PM
 919
 920 #ifdef SEC_GCTL
 921 static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
 922
 923 static int sec_suspend(void)
 924 {
 925         u32 bank;
 926
 927         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
 928                 save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0));
 929         return 0;
 930 }
 931
 932 static void sec_resume(void)
 933 {
 934         u32 bank;
 935
 936         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
 937         udelay(100);
 938         bfin_write_SEC_GCTL(SEC_GCTL_EN);
 939         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
 940
 941         for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
 942                 bfin_write_SEC_SCTL(bank + BFIN_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
 943 }
 944
 945 static struct syscore_ops sec_pm_syscore_ops = {
 946         .suspend = sec_suspend,
 947         .resume = sec_resume,
 948 };
 949 #endif
 950
 951 #endif
 952
 953 void init_exception_vectors(void)
 954 {
 955         /* cannot program in software:
 956          * evt0 - emulation (jtag)
 957          * evt1 - reset
 958          */
 959         bfin_write_EVT2(evt_nmi);
 960         bfin_write_EVT3(trap);
 961         bfin_write_EVT5(evt_ivhw);
 962         bfin_write_EVT6(evt_timer);
 963         bfin_write_EVT7(evt_evt7);
 964         bfin_write_EVT8(evt_evt8);
 965         bfin_write_EVT9(evt_evt9);
 966         bfin_write_EVT10(evt_evt10);
 967         bfin_write_EVT11(evt_evt11);
 968         bfin_write_EVT12(evt_evt12);
 969         bfin_write_EVT13(evt_evt13);
 970         bfin_write_EVT14(evt_evt14);
 971         bfin_write_EVT15(evt_system_call);
 972         CSYNC();
 973 }
 974
 975 #ifndef SEC_GCTL
 976 /*
 977  * This function should be called during kernel startup to initialize
 978  * the BFin IRQ handling routines.
 979  */
 980
 981 int __init init_arch_irq(void)
 982 {
 983         int irq;
 984         unsigned long ilat = 0;
 985
 986         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 987 #ifdef SIC_IMASK0
 988         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
 989         bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
 990 # ifdef SIC_IMASK2
 991         bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
 992 # endif
 993 # if defined(CONFIG_SMP) || defined(CONFIG_ICC)
 994         bfin_write_SICB_IMASK0(SIC_UNMASK_ALL);
 995         bfin_write_SICB_IMASK1(SIC_UNMASK_ALL);
 996 # endif
 997 #else
 998         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 999 #endif
1000
1001         local_irq_disable();
1002
1003         for (irq = 0; irq <= SYS_IRQS; irq++) {
1004                 if (irq <= IRQ_CORETMR)
1005                         irq_set_chip(irq, &bfin_core_irqchip);
1006                 else
1007                         irq_set_chip(irq, &bfin_internal_irqchip);
1008
1009                 switch (irq) {
1010 #if !BFIN_GPIO_PINT
1011 #if defined(BF537_FAMILY)
1012                 case IRQ_PH_INTA_MAC_RX:
1013                 case IRQ_PF_INTA_PG_INTA:
1014 #elif defined(BF533_FAMILY)
1015                 case IRQ_PROG_INTA:
1016 #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
1017                 case IRQ_PORTF_INTA:
1018                 case IRQ_PORTG_INTA:
1019                 case IRQ_PORTH_INTA:
1020 #elif defined(CONFIG_BF561)
1021                 case IRQ_PROG0_INTA:
1022                 case IRQ_PROG1_INTA:
1023                 case IRQ_PROG2_INTA:
1024 #elif defined(BF538_FAMILY)
1025                 case IRQ_PORTF_INTA:
1026 #endif
1027                         irq_set_chained_handler(irq, bfin_demux_gpio_irq);
1028                         break;
1029 #endif
1030 #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
1031                 case IRQ_MAC_ERROR:
1032                         irq_set_chained_handler(irq,
1033                                                 bfin_demux_mac_status_irq);
1034                         break;
1035 #endif
1036 #if defined(CONFIG_SMP) || defined(CONFIG_ICC)
1037                 case IRQ_SUPPLE_0:
1038                 case IRQ_SUPPLE_1:
1039                         irq_set_handler(irq, handle_percpu_irq);
1040                         break;
1041 #endif
1042
1043 #ifdef CONFIG_TICKSOURCE_CORETMR
1044                 case IRQ_CORETMR:
1045 # ifdef CONFIG_SMP
1046                         irq_set_handler(irq, handle_percpu_irq);
1047 # else
1048                         irq_set_handler(irq, handle_simple_irq);
1049 # endif
1050                         break;
1051 #endif
1052
1053 #ifdef CONFIG_TICKSOURCE_GPTMR0
1054                 case IRQ_TIMER0:
1055                         irq_set_handler(irq, handle_simple_irq);
1056                         break;
1057 #endif
1058
1059                 default:
1060 #ifdef CONFIG_IPIPE
1061                         irq_set_handler(irq, handle_level_irq);
1062 #else
1063                         irq_set_handler(irq, handle_simple_irq);
1064 #endif
1065                         break;
1066                 }
1067         }
1068
1069         init_mach_irq();
1070
1071 #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
1072         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
1073                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
1074                                          handle_level_irq);
1075 #endif
1076         /* if configured as edge, then will be changed to do_edge_IRQ */
1077 #ifdef CONFIG_GPIO_ADI
1078         for (irq = GPIO_IRQ_BASE;
1079                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
1080                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
1081                                          handle_level_irq);
1082 #endif
1083         bfin_write_IMASK(0);
1084         CSYNC();
1085         ilat = bfin_read_ILAT();
1086         CSYNC();
1087         bfin_write_ILAT(ilat);
1088         CSYNC();
1089
1090         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1091         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
1092          * local_irq_enable()
1093          */
1094         program_IAR();
1095         /* Therefore it's better to setup IARs before interrupts enabled */
1096         search_IAR();
1097
1098         /* Enable interrupts IVG7-15 */
1099         bfin_irq_flags |= IMASK_IVG15 |
1100                 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1101                 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1102
1103
1104         /* This implicitly covers ANOMALY_05000171
1105          * Boot-ROM code modifies SICA_IWRx wakeup registers
1106          */
1107 #ifdef SIC_IWR0
1108         bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
1109 # ifdef SIC_IWR1
1110         /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which
1111          * will screw up the bootrom as it relies on MDMA0/1 waking it
1112          * up from IDLE instructions.  See this report for more info:
1113          * http://blackfin.uclinux.org/gf/tracker/4323
1114          */
1115         if (ANOMALY_05000435)
1116                 bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
1117         else
1118                 bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
1119 # endif
1120 # ifdef SIC_IWR2
1121         bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
1122 # endif
1123 #else
1124         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
1125 #endif
1126         return 0;
1127 }
1128
1129 #ifdef CONFIG_DO_IRQ_L1
1130 __attribute__((l1_text))
1131 #endif
1132 static int vec_to_irq(int vec)
1133 {
1134         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
1135         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
1136         unsigned long sic_status[3];
1137         if (likely(vec == EVT_IVTMR_P))
1138                 return IRQ_CORETMR;
1139 #ifdef SIC_ISR
1140         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
1141 #else
1142         if (smp_processor_id()) {
1143 # ifdef SICB_ISR0
1144                 /* This will be optimized out in UP mode. */
1145                 sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
1146                 sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
1147 # endif
1148         } else {
1149                 sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
1150                 sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
1151         }
1152 #endif
1153 #ifdef SIC_ISR2
1154         sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
1155 #endif
1156
1157         for (;; ivg++) {
1158                 if (ivg >= ivg_stop)
1159                         return -1;
1160 #ifdef SIC_ISR
1161                 if (sic_status[0] & ivg->isrflag)
1162 #else
1163                 if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
1164 #endif
1165                         return ivg->irqno;
1166         }
1167 }
1168
1169 #else /* SEC_GCTL */
1170
1171 /*
1172  * This function should be called during kernel startup to initialize
1173  * the BFin IRQ handling routines.
1174  */
1175
1176 int __init init_arch_irq(void)
1177 {
1178         int irq;
1179         unsigned long ilat = 0;
1180
1181         bfin_write_SEC_GCTL(SEC_GCTL_RESET);
1182
1183         local_irq_disable();
1184
1185         for (irq = 0; irq <= SYS_IRQS; irq++) {
1186                 if (irq <= IRQ_CORETMR) {
1187                         irq_set_chip_and_handler(irq, &bfin_core_irqchip,
1188                                 handle_simple_irq);
1189 #if defined(CONFIG_TICKSOURCE_CORETMR) && defined(CONFIG_SMP)
1190                         if (irq == IRQ_CORETMR)
1191                                 irq_set_handler(irq, handle_percpu_irq);
1192 #endif
1193                 } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
1194                         irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
1195                                 handle_percpu_irq);
1196                 } else {
1197                         irq_set_chip(irq, &bfin_sec_irqchip);
1198                         if (irq == IRQ_SEC_ERR)
1199                                 irq_set_handler(irq, handle_sec_fault);
1200                         else if (irq >= IRQ_C0_DBL_FAULT && irq < CORE_IRQS)
1201                                 irq_set_handler(irq, handle_core_fault);
1202                         else
1203                                 irq_set_handler(irq, handle_fasteoi_irq);
1204                         __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
1205                 }
1206         }
1207
1208         bfin_write_IMASK(0);
1209         CSYNC();
1210         ilat = bfin_read_ILAT();
1211         CSYNC();
1212         bfin_write_ILAT(ilat);
1213         CSYNC();
1214
1215         printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
1216
1217         bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1218
1219         bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
1220
1221         /* Enable interrupts IVG7-15 */
1222         bfin_irq_flags |= IMASK_IVG15 |
1223             IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1224             IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1225
1226
1227         bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
1228         bfin_sec_enable_sci(BFIN_SYSIRQ(IRQ_WATCH0));
1229         bfin_sec_enable_ssi(BFIN_SYSIRQ(IRQ_WATCH0));
1230         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
1231         udelay(100);
1232         bfin_write_SEC_GCTL(SEC_GCTL_EN);
1233         bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1234         bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
1235
1236         init_software_driven_irq();
1237
1238 #ifdef CONFIG_PM
1239         register_syscore_ops(&sec_pm_syscore_ops);
1240 #endif
1241
1242         return 0;
1243 }
1244
1245 #ifdef CONFIG_DO_IRQ_L1
1246 __attribute__((l1_text))
1247 #endif
1248 static int vec_to_irq(int vec)
1249 {
1250         if (likely(vec == EVT_IVTMR_P))
1251                 return IRQ_CORETMR;
1252
1253         return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
1254 }
1255 #endif  /* SEC_GCTL */
1256
1257 #ifdef CONFIG_DO_IRQ_L1
1258 __attribute__((l1_text))
1259 #endif
1260 void do_irq(int vec, struct pt_regs *fp)
1261 {
1262         int irq = vec_to_irq(vec);
1263         if (irq == -1)
1264                 return;
1265         asm_do_IRQ(irq, fp);
1266 }
1267
1268 #ifdef CONFIG_IPIPE
1269
1270 int __ipipe_get_irq_priority(unsigned irq)
1271 {
1272         int ient, prio;
1273
1274         if (irq <= IRQ_CORETMR)
1275                 return irq;
1276
1277 #ifdef SEC_GCTL
1278         if (irq >= BFIN_IRQ(0))
1279                 return IVG11;
1280 #else
1281         for (ient = 0; ient < NR_PERI_INTS; ient++) {
1282                 struct ivgx *ivg = ivg_table + ient;
1283                 if (ivg->irqno == irq) {
1284                         for (prio = 0; prio <= IVG13-IVG7; prio++) {
1285                                 if (ivg7_13[prio].ifirst <= ivg &&
1286                                     ivg7_13[prio].istop > ivg)
1287                                         return IVG7 + prio;
1288                         }
1289                 }
1290         }
1291 #endif
1292
1293         return IVG15;
1294 }
1295
1296 /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */
1297 #ifdef CONFIG_DO_IRQ_L1
1298 __attribute__((l1_text))
1299 #endif
1300 asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
1301 {
1302         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
1303         struct ipipe_domain *this_domain = __ipipe_current_domain;
1304         int irq, s = 0;
1305
1306         irq = vec_to_irq(vec);
1307         if (irq == -1)
1308                 return 0;
1309
1310         if (irq == IRQ_SYSTMR) {
1311 #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
1312                 bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */
1313 #endif
1314                 /* This is basically what we need from the register frame. */
1315                 __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend;
1316                 __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc;
1317                 if (this_domain != ipipe_root_domain)
1318                         __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10;
1319                 else
1320                         __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10;
1321         }
1322
1323         /*
1324          * We don't want Linux interrupt handlers to run at the
1325          * current core priority level (i.e. < EVT15), since this
1326          * might delay other interrupts handled by a high priority
1327          * domain. Here is what we do instead:
1328          *
1329          * - we raise the SYNCDEFER bit to prevent
1330          * __ipipe_handle_irq() to sync the pipeline for the root
1331          * stage for the incoming interrupt. Upon return, that IRQ is
1332          * pending in the interrupt log.
1333          *
1334          * - we raise the TIF_IRQ_SYNC bit for the current thread, so
1335          * that _schedule_and_signal_from_int will eventually sync the
1336          * pipeline from EVT15.
1337          */
1338         if (this_domain == ipipe_root_domain) {
1339                 s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1340                 barrier();
1341         }
1342
1343         ipipe_trace_irq_entry(irq);
1344         __ipipe_handle_irq(irq, regs);
1345         ipipe_trace_irq_exit(irq);
1346
1347         if (user_mode(regs) &&
1348             !ipipe_test_foreign_stack() &&
1349             (current->ipipe_flags & PF_EVTRET) != 0) {
1350                 /*
1351                  * Testing for user_regs() does NOT fully eliminate
1352                  * foreign stack contexts, because of the forged
1353                  * interrupt returns we do through
1354                  * __ipipe_call_irqtail. In that case, we might have
1355                  * preempted a foreign stack context in a high
1356                  * priority domain, with a single interrupt level now
1357                  * pending after the irqtail unwinding is done. In
1358                  * which case user_mode() is now true, and the event
1359                  * gets dispatched spuriously.
1360                  */
1361                 current->ipipe_flags &= ~PF_EVTRET;
1362                 __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs);
1363         }
1364
1365         if (this_domain == ipipe_root_domain) {
1366                 set_thread_flag(TIF_IRQ_SYNC);
1367                 if (!s) {
1368                         __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status);
1369                         return !test_bit(IPIPE_STALL_FLAG, &p->status);
1370                 }
1371         }
1372
1373         return 0;
1374 }
1375
1376 #endif /* CONFIG_IPIPE */