Merge branch 'x86/cpufeature' into irq/numa
[sfrench/cifs-2.6.git] / arch / blackfin / mach-bf561 / smp.c
1 /*
2  * File:         arch/blackfin/mach-bf561/smp.c
3  * Author:       Philippe Gerum <rpm@xenomai.org>
4  *
5  *               Copyright 2007 Analog Devices Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License, or
10  * (at your option) any later version.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  * You should have received a copy of the GNU General Public License
18  * along with this program; if not, see the file COPYING, or write
19  * to the Free Software Foundation, Inc.,
20  * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
21  */
22
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/sched.h>
26 #include <linux/delay.h>
27 #include <asm/smp.h>
28 #include <asm/dma.h>
29
30 static DEFINE_SPINLOCK(boot_lock);
31
32 static cpumask_t cpu_callin_map;
33
34 /*
35  * platform_init_cpus() - Tell the world about how many cores we
36  * have. This is called while setting up the architecture support
37  * (setup_arch()), so don't be too demanding here with respect to
38  * available kernel services.
39  */
40
41 void __init platform_init_cpus(void)
42 {
43         cpu_set(0, cpu_possible_map); /* CoreA */
44         cpu_set(1, cpu_possible_map); /* CoreB */
45 }
46
47 void __init platform_prepare_cpus(unsigned int max_cpus)
48 {
49         int len;
50
51         len = &coreb_trampoline_end - &coreb_trampoline_start + 1;
52         BUG_ON(len > L1_CODE_LENGTH);
53
54         dma_memcpy((void *)COREB_L1_CODE_START, &coreb_trampoline_start, len);
55
56         /* Both cores ought to be present on a bf561! */
57         cpu_set(0, cpu_present_map); /* CoreA */
58         cpu_set(1, cpu_present_map); /* CoreB */
59
60         printk(KERN_INFO "CoreB bootstrap code to SRAM %p via DMA.\n", (void *)COREB_L1_CODE_START);
61 }
62
63 int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
64 {
65         return -EINVAL;
66 }
67
68 void __cpuinit platform_secondary_init(unsigned int cpu)
69 {
70         local_irq_disable();
71
72         /* Clone setup for peripheral interrupt sources from CoreA. */
73         bfin_write_SICB_IMASK0(bfin_read_SICA_IMASK0());
74         bfin_write_SICB_IMASK1(bfin_read_SICA_IMASK1());
75         SSYNC();
76
77         /* Clone setup for IARs from CoreA. */
78         bfin_write_SICB_IAR0(bfin_read_SICA_IAR0());
79         bfin_write_SICB_IAR1(bfin_read_SICA_IAR1());
80         bfin_write_SICB_IAR2(bfin_read_SICA_IAR2());
81         bfin_write_SICB_IAR3(bfin_read_SICA_IAR3());
82         bfin_write_SICB_IAR4(bfin_read_SICA_IAR4());
83         bfin_write_SICB_IAR5(bfin_read_SICA_IAR5());
84         bfin_write_SICB_IAR6(bfin_read_SICA_IAR6());
85         bfin_write_SICB_IAR7(bfin_read_SICA_IAR7());
86         SSYNC();
87
88         local_irq_enable();
89
90         /* Calibrate loops per jiffy value. */
91         calibrate_delay();
92
93         /* Store CPU-private information to the cpu_data array. */
94         bfin_setup_cpudata(cpu);
95
96         /* We are done with local CPU inits, unblock the boot CPU. */
97         cpu_set(cpu, cpu_callin_map);
98         spin_lock(&boot_lock);
99         spin_unlock(&boot_lock);
100 }
101
102 int __cpuinit platform_boot_secondary(unsigned int cpu, struct task_struct *idle)
103 {
104         unsigned long timeout;
105
106         /* CoreB already running?! */
107         BUG_ON((bfin_read_SICA_SYSCR() & COREB_SRAM_INIT) == 0);
108
109         printk(KERN_INFO "Booting Core B.\n");
110
111         spin_lock(&boot_lock);
112
113         /* Kick CoreB, which should start execution from CORE_SRAM_BASE. */
114         SSYNC();
115         bfin_write_SICA_SYSCR(bfin_read_SICA_SYSCR() & ~COREB_SRAM_INIT);
116         SSYNC();
117
118         timeout = jiffies + 1 * HZ;
119         while (time_before(jiffies, timeout)) {
120                 if (cpu_isset(cpu, cpu_callin_map))
121                         break;
122                 udelay(100);
123                 barrier();
124         }
125
126         spin_unlock(&boot_lock);
127
128         return cpu_isset(cpu, cpu_callin_map) ? 0 : -ENOSYS;
129 }
130
131 void __init platform_request_ipi(irq_handler_t handler)
132 {
133         int ret;
134
135         ret = request_irq(IRQ_SUPPLE_0, handler, IRQF_DISABLED,
136                           "SMP interrupt", handler);
137         if (ret)
138                 panic("Cannot request supplemental interrupt 0 for IPI service\n");
139 }
140
141 void platform_send_ipi(cpumask_t callmap)
142 {
143         unsigned int cpu;
144
145         for_each_cpu_mask(cpu, callmap) {
146                 BUG_ON(cpu >= 2);
147                 SSYNC();
148                 bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
149                 SSYNC();
150         }
151 }
152
153 void platform_send_ipi_cpu(unsigned int cpu)
154 {
155         BUG_ON(cpu >= 2);
156         SSYNC();
157         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (6 + cpu)));
158         SSYNC();
159 }
160
161 void platform_clear_ipi(unsigned int cpu)
162 {
163         BUG_ON(cpu >= 2);
164         SSYNC();
165         bfin_write_SICB_SYSCR(bfin_read_SICB_SYSCR() | (1 << (10 + cpu)));
166         SSYNC();
167 }