arch/avr32/mach-at32ap/at32ap7000.c

   1 /*
   2  * Copyright (C) 2005-2006 Atmel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8 #include <linux/clk.h>
   9 #include <linux/fb.h>
  10 #include <linux/init.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/spi/spi.h>
  13
  14 #include <asm/io.h>
  15
  16 #include <asm/arch/at32ap7000.h>
  17 #include <asm/arch/board.h>
  18 #include <asm/arch/portmux.h>
  19 #include <asm/arch/sm.h>
  20
  21 #include <video/atmel_lcdc.h>
  22
  23 #include "clock.h"
  24 #include "hmatrix.h"
  25 #include "pio.h"
  26 #include "sm.h"
  27
  28 #define PBMEM(base)                                     \
  29         {                                               \
  30                 .start          = base,                 \
  31                 .end            = base + 0x3ff,         \
  32                 .flags          = IORESOURCE_MEM,       \
  33         }
  34 #define IRQ(num)                                        \
  35         {                                               \
  36                 .start          = num,                  \
  37                 .end            = num,                  \
  38                 .flags          = IORESOURCE_IRQ,       \
  39         }
  40 #define NAMED_IRQ(num, _name)                           \
  41         {                                               \
  42                 .start          = num,                  \
  43                 .end            = num,                  \
  44                 .name           = _name,                \
  45                 .flags          = IORESOURCE_IRQ,       \
  46         }
  47
  48 #define DEFINE_DEV(_name, _id)                                  \
  49 static struct platform_device _name##_id##_device = {           \
  50         .name           = #_name,                               \
  51         .id             = _id,                                  \
  52         .resource       = _name##_id##_resource,                \
  53         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  54 }
  55 #define DEFINE_DEV_DATA(_name, _id)                             \
  56 static struct platform_device _name##_id##_device = {           \
  57         .name           = #_name,                               \
  58         .id             = _id,                                  \
  59         .dev            = {                                     \
  60                 .platform_data  = &_name##_id##_data,           \
  61         },                                                      \
  62         .resource       = _name##_id##_resource,                \
  63         .num_resources  = ARRAY_SIZE(_name##_id##_resource),    \
  64 }
  65
  66 #define select_peripheral(pin, periph, flags)                   \
  67         at32_select_periph(GPIO_PIN_##pin, GPIO_##periph, flags)
  68
  69 #define DEV_CLK(_name, devname, bus, _index)                    \
  70 static struct clk devname##_##_name = {                         \
  71         .name           = #_name,                               \
  72         .dev            = &devname##_device.dev,                \
  73         .parent         = &bus##_clk,                           \
  74         .mode           = bus##_clk_mode,                       \
  75         .get_rate       = bus##_clk_get_rate,                   \
  76         .index          = _index,                               \
  77 }
  78
  79 unsigned long at32ap7000_osc_rates[3] = {
  80         [0] = 32768,
  81         /* FIXME: these are ATSTK1002-specific */
  82         [1] = 20000000,
  83         [2] = 12000000,
  84 };
  85
  86 static unsigned long osc_get_rate(struct clk *clk)
  87 {
  88         return at32ap7000_osc_rates[clk->index];
  89 }
  90
  91 static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
  92 {
  93         unsigned long div, mul, rate;
  94
  95         if (!(control & SM_BIT(PLLEN)))
  96                 return 0;
  97
  98         div = SM_BFEXT(PLLDIV, control) + 1;
  99         mul = SM_BFEXT(PLLMUL, control) + 1;
 100
 101         rate = clk->parent->get_rate(clk->parent);
 102         rate = (rate + div / 2) / div;
 103         rate *= mul;
 104
 105         return rate;
 106 }
 107
 108 static unsigned long pll0_get_rate(struct clk *clk)
 109 {
 110         u32 control;
 111
 112         control = sm_readl(&system_manager, PM_PLL0);
 113
 114         return pll_get_rate(clk, control);
 115 }
 116
 117 static unsigned long pll1_get_rate(struct clk *clk)
 118 {
 119         u32 control;
 120
 121         control = sm_readl(&system_manager, PM_PLL1);
 122
 123         return pll_get_rate(clk, control);
 124 }
 125
 126 /*
 127  * The AT32AP7000 has five primary clock sources: One 32kHz
 128  * oscillator, two crystal oscillators and two PLLs.
 129  */
 130 static struct clk osc32k = {
 131         .name           = "osc32k",
 132         .get_rate       = osc_get_rate,
 133         .users          = 1,
 134         .index          = 0,
 135 };
 136 static struct clk osc0 = {
 137         .name           = "osc0",
 138         .get_rate       = osc_get_rate,
 139         .users          = 1,
 140         .index          = 1,
 141 };
 142 static struct clk osc1 = {
 143         .name           = "osc1",
 144         .get_rate       = osc_get_rate,
 145         .index          = 2,
 146 };
 147 static struct clk pll0 = {
 148         .name           = "pll0",
 149         .get_rate       = pll0_get_rate,
 150         .parent         = &osc0,
 151 };
 152 static struct clk pll1 = {
 153         .name           = "pll1",
 154         .get_rate       = pll1_get_rate,
 155         .parent         = &osc0,
 156 };
 157
 158 /*
 159  * The main clock can be either osc0 or pll0.  The boot loader may
 160  * have chosen one for us, so we don't really know which one until we
 161  * have a look at the SM.
 162  */
 163 static struct clk *main_clock;
 164
 165 /*
 166  * Synchronous clocks are generated from the main clock. The clocks
 167  * must satisfy the constraint
 168  *   fCPU >= fHSB >= fPB
 169  * i.e. each clock must not be faster than its parent.
 170  */
 171 static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
 172 {
 173         return main_clock->get_rate(main_clock) >> shift;
 174 };
 175
 176 static void cpu_clk_mode(struct clk *clk, int enabled)
 177 {
 178         struct at32_sm *sm = &system_manager;
 179         unsigned long flags;
 180         u32 mask;
 181
 182         spin_lock_irqsave(&sm->lock, flags);
 183         mask = sm_readl(sm, PM_CPU_MASK);
 184         if (enabled)
 185                 mask |= 1 << clk->index;
 186         else
 187                 mask &= ~(1 << clk->index);
 188         sm_writel(sm, PM_CPU_MASK, mask);
 189         spin_unlock_irqrestore(&sm->lock, flags);
 190 }
 191
 192 static unsigned long cpu_clk_get_rate(struct clk *clk)
 193 {
 194         unsigned long cksel, shift = 0;
 195
 196         cksel = sm_readl(&system_manager, PM_CKSEL);
 197         if (cksel & SM_BIT(CPUDIV))
 198                 shift = SM_BFEXT(CPUSEL, cksel) + 1;
 199
 200         return bus_clk_get_rate(clk, shift);
 201 }
 202
 203 static void hsb_clk_mode(struct clk *clk, int enabled)
 204 {
 205         struct at32_sm *sm = &system_manager;
 206         unsigned long flags;
 207         u32 mask;
 208
 209         spin_lock_irqsave(&sm->lock, flags);
 210         mask = sm_readl(sm, PM_HSB_MASK);
 211         if (enabled)
 212                 mask |= 1 << clk->index;
 213         else
 214                 mask &= ~(1 << clk->index);
 215         sm_writel(sm, PM_HSB_MASK, mask);
 216         spin_unlock_irqrestore(&sm->lock, flags);
 217 }
 218
 219 static unsigned long hsb_clk_get_rate(struct clk *clk)
 220 {
 221         unsigned long cksel, shift = 0;
 222
 223         cksel = sm_readl(&system_manager, PM_CKSEL);
 224         if (cksel & SM_BIT(HSBDIV))
 225                 shift = SM_BFEXT(HSBSEL, cksel) + 1;
 226
 227         return bus_clk_get_rate(clk, shift);
 228 }
 229
 230 static void pba_clk_mode(struct clk *clk, int enabled)
 231 {
 232         struct at32_sm *sm = &system_manager;
 233         unsigned long flags;
 234         u32 mask;
 235
 236         spin_lock_irqsave(&sm->lock, flags);
 237         mask = sm_readl(sm, PM_PBA_MASK);
 238         if (enabled)
 239                 mask |= 1 << clk->index;
 240         else
 241                 mask &= ~(1 << clk->index);
 242         sm_writel(sm, PM_PBA_MASK, mask);
 243         spin_unlock_irqrestore(&sm->lock, flags);
 244 }
 245
 246 static unsigned long pba_clk_get_rate(struct clk *clk)
 247 {
 248         unsigned long cksel, shift = 0;
 249
 250         cksel = sm_readl(&system_manager, PM_CKSEL);
 251         if (cksel & SM_BIT(PBADIV))
 252                 shift = SM_BFEXT(PBASEL, cksel) + 1;
 253
 254         return bus_clk_get_rate(clk, shift);
 255 }
 256
 257 static void pbb_clk_mode(struct clk *clk, int enabled)
 258 {
 259         struct at32_sm *sm = &system_manager;
 260         unsigned long flags;
 261         u32 mask;
 262
 263         spin_lock_irqsave(&sm->lock, flags);
 264         mask = sm_readl(sm, PM_PBB_MASK);
 265         if (enabled)
 266                 mask |= 1 << clk->index;
 267         else
 268                 mask &= ~(1 << clk->index);
 269         sm_writel(sm, PM_PBB_MASK, mask);
 270         spin_unlock_irqrestore(&sm->lock, flags);
 271 }
 272
 273 static unsigned long pbb_clk_get_rate(struct clk *clk)
 274 {
 275         unsigned long cksel, shift = 0;
 276
 277         cksel = sm_readl(&system_manager, PM_CKSEL);
 278         if (cksel & SM_BIT(PBBDIV))
 279                 shift = SM_BFEXT(PBBSEL, cksel) + 1;
 280
 281         return bus_clk_get_rate(clk, shift);
 282 }
 283
 284 static struct clk cpu_clk = {
 285         .name           = "cpu",
 286         .get_rate       = cpu_clk_get_rate,
 287         .users          = 1,
 288 };
 289 static struct clk hsb_clk = {
 290         .name           = "hsb",
 291         .parent         = &cpu_clk,
 292         .get_rate       = hsb_clk_get_rate,
 293 };
 294 static struct clk pba_clk = {
 295         .name           = "pba",
 296         .parent         = &hsb_clk,
 297         .mode           = hsb_clk_mode,
 298         .get_rate       = pba_clk_get_rate,
 299         .index          = 1,
 300 };
 301 static struct clk pbb_clk = {
 302         .name           = "pbb",
 303         .parent         = &hsb_clk,
 304         .mode           = hsb_clk_mode,
 305         .get_rate       = pbb_clk_get_rate,
 306         .users          = 1,
 307         .index          = 2,
 308 };
 309
 310 /* --------------------------------------------------------------------
 311  *  Generic Clock operations
 312  * -------------------------------------------------------------------- */
 313
 314 static void genclk_mode(struct clk *clk, int enabled)
 315 {
 316         u32 control;
 317
 318         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 319         if (enabled)
 320                 control |= SM_BIT(CEN);
 321         else
 322                 control &= ~SM_BIT(CEN);
 323         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
 324 }
 325
 326 static unsigned long genclk_get_rate(struct clk *clk)
 327 {
 328         u32 control;
 329         unsigned long div = 1;
 330
 331         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 332         if (control & SM_BIT(DIVEN))
 333                 div = 2 * (SM_BFEXT(DIV, control) + 1);
 334
 335         return clk->parent->get_rate(clk->parent) / div;
 336 }
 337
 338 static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
 339 {
 340         u32 control;
 341         unsigned long parent_rate, actual_rate, div;
 342
 343         parent_rate = clk->parent->get_rate(clk->parent);
 344         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 345
 346         if (rate > 3 * parent_rate / 4) {
 347                 actual_rate = parent_rate;
 348                 control &= ~SM_BIT(DIVEN);
 349         } else {
 350                 div = (parent_rate + rate) / (2 * rate) - 1;
 351                 control = SM_BFINS(DIV, div, control) | SM_BIT(DIVEN);
 352                 actual_rate = parent_rate / (2 * (div + 1));
 353         }
 354
 355         printk("clk %s: new rate %lu (actual rate %lu)\n",
 356                clk->name, rate, actual_rate);
 357
 358         if (apply)
 359                 sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index,
 360                           control);
 361
 362         return actual_rate;
 363 }
 364
 365 int genclk_set_parent(struct clk *clk, struct clk *parent)
 366 {
 367         u32 control;
 368
 369         printk("clk %s: new parent %s (was %s)\n",
 370                clk->name, parent->name, clk->parent->name);
 371
 372         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 373
 374         if (parent == &osc1 || parent == &pll1)
 375                 control |= SM_BIT(OSCSEL);
 376         else if (parent == &osc0 || parent == &pll0)
 377                 control &= ~SM_BIT(OSCSEL);
 378         else
 379                 return -EINVAL;
 380
 381         if (parent == &pll0 || parent == &pll1)
 382                 control |= SM_BIT(PLLSEL);
 383         else
 384                 control &= ~SM_BIT(PLLSEL);
 385
 386         sm_writel(&system_manager, PM_GCCTRL + 4 * clk->index, control);
 387         clk->parent = parent;
 388
 389         return 0;
 390 }
 391
 392 static void __init genclk_init_parent(struct clk *clk)
 393 {
 394         u32 control;
 395         struct clk *parent;
 396
 397         BUG_ON(clk->index > 7);
 398
 399         control = sm_readl(&system_manager, PM_GCCTRL + 4 * clk->index);
 400         if (control & SM_BIT(OSCSEL))
 401                 parent = (control & SM_BIT(PLLSEL)) ? &pll1 : &osc1;
 402         else
 403                 parent = (control & SM_BIT(PLLSEL)) ? &pll0 : &osc0;
 404
 405         clk->parent = parent;
 406 }
 407
 408 /* --------------------------------------------------------------------
 409  *  System peripherals
 410  * -------------------------------------------------------------------- */
 411 static struct resource sm_resource[] = {
 412         PBMEM(0xfff00000),
 413         NAMED_IRQ(19, "eim"),
 414         NAMED_IRQ(20, "pm"),
 415         NAMED_IRQ(21, "rtc"),
 416 };
 417 struct platform_device at32_sm_device = {
 418         .name           = "sm",
 419         .id             = 0,
 420         .resource       = sm_resource,
 421         .num_resources  = ARRAY_SIZE(sm_resource),
 422 };
 423 static struct clk at32_sm_pclk = {
 424         .name           = "pclk",
 425         .dev            = &at32_sm_device.dev,
 426         .parent         = &pbb_clk,
 427         .mode           = pbb_clk_mode,
 428         .get_rate       = pbb_clk_get_rate,
 429         .users          = 1,
 430         .index          = 0,
 431 };
 432
 433 static struct resource intc0_resource[] = {
 434         PBMEM(0xfff00400),
 435 };
 436 struct platform_device at32_intc0_device = {
 437         .name           = "intc",
 438         .id             = 0,
 439         .resource       = intc0_resource,
 440         .num_resources  = ARRAY_SIZE(intc0_resource),
 441 };
 442 DEV_CLK(pclk, at32_intc0, pbb, 1);
 443
 444 static struct clk ebi_clk = {
 445         .name           = "ebi",
 446         .parent         = &hsb_clk,
 447         .mode           = hsb_clk_mode,
 448         .get_rate       = hsb_clk_get_rate,
 449         .users          = 1,
 450 };
 451 static struct clk hramc_clk = {
 452         .name           = "hramc",
 453         .parent         = &hsb_clk,
 454         .mode           = hsb_clk_mode,
 455         .get_rate       = hsb_clk_get_rate,
 456         .users          = 1,
 457         .index          = 3,
 458 };
 459
 460 static struct resource smc0_resource[] = {
 461         PBMEM(0xfff03400),
 462 };
 463 DEFINE_DEV(smc, 0);
 464 DEV_CLK(pclk, smc0, pbb, 13);
 465 DEV_CLK(mck, smc0, hsb, 0);
 466
 467 static struct platform_device pdc_device = {
 468         .name           = "pdc",
 469         .id             = 0,
 470 };
 471 DEV_CLK(hclk, pdc, hsb, 4);
 472 DEV_CLK(pclk, pdc, pba, 16);
 473
 474 static struct clk pico_clk = {
 475         .name           = "pico",
 476         .parent         = &cpu_clk,
 477         .mode           = cpu_clk_mode,
 478         .get_rate       = cpu_clk_get_rate,
 479         .users          = 1,
 480 };
 481
 482 /* --------------------------------------------------------------------
 483  * HMATRIX
 484  * -------------------------------------------------------------------- */
 485
 486 static struct clk hmatrix_clk = {
 487         .name           = "hmatrix_clk",
 488         .parent         = &pbb_clk,
 489         .mode           = pbb_clk_mode,
 490         .get_rate       = pbb_clk_get_rate,
 491         .index          = 2,
 492         .users          = 1,
 493 };
 494 #define HMATRIX_BASE    ((void __iomem *)0xfff00800)
 495
 496 #define hmatrix_readl(reg)                                      \
 497         __raw_readl((HMATRIX_BASE) + HMATRIX_##reg)
 498 #define hmatrix_writel(reg,value)                               \
 499         __raw_writel((value), (HMATRIX_BASE) + HMATRIX_##reg)
 500
 501 /*
 502  * Set bits in the HMATRIX Special Function Register (SFR) used by the
 503  * External Bus Interface (EBI). This can be used to enable special
 504  * features like CompactFlash support, NAND Flash support, etc. on
 505  * certain chipselects.
 506  */
 507 static inline void set_ebi_sfr_bits(u32 mask)
 508 {
 509         u32 sfr;
 510
 511         clk_enable(&hmatrix_clk);
 512         sfr = hmatrix_readl(SFR4);
 513         sfr |= mask;
 514         hmatrix_writel(SFR4, sfr);
 515         clk_disable(&hmatrix_clk);
 516 }
 517
 518 /* --------------------------------------------------------------------
 519  *  System Timer/Counter (TC)
 520  * -------------------------------------------------------------------- */
 521 static struct resource at32_systc0_resource[] = {
 522         PBMEM(0xfff00c00),
 523         IRQ(22),
 524 };
 525 struct platform_device at32_systc0_device = {
 526         .name           = "systc",
 527         .id             = 0,
 528         .resource       = at32_systc0_resource,
 529         .num_resources  = ARRAY_SIZE(at32_systc0_resource),
 530 };
 531 DEV_CLK(pclk, at32_systc0, pbb, 3);
 532
 533 /* --------------------------------------------------------------------
 534  *  PIO
 535  * -------------------------------------------------------------------- */
 536
 537 static struct resource pio0_resource[] = {
 538         PBMEM(0xffe02800),
 539         IRQ(13),
 540 };
 541 DEFINE_DEV(pio, 0);
 542 DEV_CLK(mck, pio0, pba, 10);
 543
 544 static struct resource pio1_resource[] = {
 545         PBMEM(0xffe02c00),
 546         IRQ(14),
 547 };
 548 DEFINE_DEV(pio, 1);
 549 DEV_CLK(mck, pio1, pba, 11);
 550
 551 static struct resource pio2_resource[] = {
 552         PBMEM(0xffe03000),
 553         IRQ(15),
 554 };
 555 DEFINE_DEV(pio, 2);
 556 DEV_CLK(mck, pio2, pba, 12);
 557
 558 static struct resource pio3_resource[] = {
 559         PBMEM(0xffe03400),
 560         IRQ(16),
 561 };
 562 DEFINE_DEV(pio, 3);
 563 DEV_CLK(mck, pio3, pba, 13);
 564
 565 static struct resource pio4_resource[] = {
 566         PBMEM(0xffe03800),
 567         IRQ(17),
 568 };
 569 DEFINE_DEV(pio, 4);
 570 DEV_CLK(mck, pio4, pba, 14);
 571
 572 void __init at32_add_system_devices(void)
 573 {
 574         system_manager.eim_first_irq = EIM_IRQ_BASE;
 575
 576         platform_device_register(&at32_sm_device);
 577         platform_device_register(&at32_intc0_device);
 578         platform_device_register(&smc0_device);
 579         platform_device_register(&pdc_device);
 580
 581         platform_device_register(&at32_systc0_device);
 582
 583         platform_device_register(&pio0_device);
 584         platform_device_register(&pio1_device);
 585         platform_device_register(&pio2_device);
 586         platform_device_register(&pio3_device);
 587         platform_device_register(&pio4_device);
 588 }
 589
 590 /* --------------------------------------------------------------------
 591  *  USART
 592  * -------------------------------------------------------------------- */
 593
 594 static struct atmel_uart_data atmel_usart0_data = {
 595         .use_dma_tx     = 1,
 596         .use_dma_rx     = 1,
 597 };
 598 static struct resource atmel_usart0_resource[] = {
 599         PBMEM(0xffe00c00),
 600         IRQ(6),
 601 };
 602 DEFINE_DEV_DATA(atmel_usart, 0);
 603 DEV_CLK(usart, atmel_usart0, pba, 4);
 604
 605 static struct atmel_uart_data atmel_usart1_data = {
 606         .use_dma_tx     = 1,
 607         .use_dma_rx     = 1,
 608 };
 609 static struct resource atmel_usart1_resource[] = {
 610         PBMEM(0xffe01000),
 611         IRQ(7),
 612 };
 613 DEFINE_DEV_DATA(atmel_usart, 1);
 614 DEV_CLK(usart, atmel_usart1, pba, 4);
 615
 616 static struct atmel_uart_data atmel_usart2_data = {
 617         .use_dma_tx     = 1,
 618         .use_dma_rx     = 1,
 619 };
 620 static struct resource atmel_usart2_resource[] = {
 621         PBMEM(0xffe01400),
 622         IRQ(8),
 623 };
 624 DEFINE_DEV_DATA(atmel_usart, 2);
 625 DEV_CLK(usart, atmel_usart2, pba, 5);
 626
 627 static struct atmel_uart_data atmel_usart3_data = {
 628         .use_dma_tx     = 1,
 629         .use_dma_rx     = 1,
 630 };
 631 static struct resource atmel_usart3_resource[] = {
 632         PBMEM(0xffe01800),
 633         IRQ(9),
 634 };
 635 DEFINE_DEV_DATA(atmel_usart, 3);
 636 DEV_CLK(usart, atmel_usart3, pba, 6);
 637
 638 static inline void configure_usart0_pins(void)
 639 {
 640         select_peripheral(PA(8),  PERIPH_B, 0); /* RXD  */
 641         select_peripheral(PA(9),  PERIPH_B, 0); /* TXD  */
 642 }
 643
 644 static inline void configure_usart1_pins(void)
 645 {
 646         select_peripheral(PA(17), PERIPH_A, 0); /* RXD  */
 647         select_peripheral(PA(18), PERIPH_A, 0); /* TXD  */
 648 }
 649
 650 static inline void configure_usart2_pins(void)
 651 {
 652         select_peripheral(PB(26), PERIPH_B, 0); /* RXD  */
 653         select_peripheral(PB(27), PERIPH_B, 0); /* TXD  */
 654 }
 655
 656 static inline void configure_usart3_pins(void)
 657 {
 658         select_peripheral(PB(18), PERIPH_B, 0); /* RXD  */
 659         select_peripheral(PB(17), PERIPH_B, 0); /* TXD  */
 660 }
 661
 662 static struct platform_device *__initdata at32_usarts[4];
 663
 664 void __init at32_map_usart(unsigned int hw_id, unsigned int line)
 665 {
 666         struct platform_device *pdev;
 667
 668         switch (hw_id) {
 669         case 0:
 670                 pdev = &atmel_usart0_device;
 671                 configure_usart0_pins();
 672                 break;
 673         case 1:
 674                 pdev = &atmel_usart1_device;
 675                 configure_usart1_pins();
 676                 break;
 677         case 2:
 678                 pdev = &atmel_usart2_device;
 679                 configure_usart2_pins();
 680                 break;
 681         case 3:
 682                 pdev = &atmel_usart3_device;
 683                 configure_usart3_pins();
 684                 break;
 685         default:
 686                 return;
 687         }
 688
 689         if (PXSEG(pdev->resource[0].start) == P4SEG) {
 690                 /* Addresses in the P4 segment are permanently mapped 1:1 */
 691                 struct atmel_uart_data *data = pdev->dev.platform_data;
 692                 data->regs = (void __iomem *)pdev->resource[0].start;
 693         }
 694
 695         pdev->id = line;
 696         at32_usarts[line] = pdev;
 697 }
 698
 699 struct platform_device *__init at32_add_device_usart(unsigned int id)
 700 {
 701         platform_device_register(at32_usarts[id]);
 702         return at32_usarts[id];
 703 }
 704
 705 struct platform_device *atmel_default_console_device;
 706
 707 void __init at32_setup_serial_console(unsigned int usart_id)
 708 {
 709         atmel_default_console_device = at32_usarts[usart_id];
 710 }
 711
 712 /* --------------------------------------------------------------------
 713  *  Ethernet
 714  * -------------------------------------------------------------------- */
 715
 716 static struct eth_platform_data macb0_data;
 717 static struct resource macb0_resource[] = {
 718         PBMEM(0xfff01800),
 719         IRQ(25),
 720 };
 721 DEFINE_DEV_DATA(macb, 0);
 722 DEV_CLK(hclk, macb0, hsb, 8);
 723 DEV_CLK(pclk, macb0, pbb, 6);
 724
 725 static struct eth_platform_data macb1_data;
 726 static struct resource macb1_resource[] = {
 727         PBMEM(0xfff01c00),
 728         IRQ(26),
 729 };
 730 DEFINE_DEV_DATA(macb, 1);
 731 DEV_CLK(hclk, macb1, hsb, 9);
 732 DEV_CLK(pclk, macb1, pbb, 7);
 733
 734 struct platform_device *__init
 735 at32_add_device_eth(unsigned int id, struct eth_platform_data *data)
 736 {
 737         struct platform_device *pdev;
 738
 739         switch (id) {
 740         case 0:
 741                 pdev = &macb0_device;
 742
 743                 select_peripheral(PC(3),  PERIPH_A, 0); /* TXD0 */
 744                 select_peripheral(PC(4),  PERIPH_A, 0); /* TXD1 */
 745                 select_peripheral(PC(7),  PERIPH_A, 0); /* TXEN */
 746                 select_peripheral(PC(8),  PERIPH_A, 0); /* TXCK */
 747                 select_peripheral(PC(9),  PERIPH_A, 0); /* RXD0 */
 748                 select_peripheral(PC(10), PERIPH_A, 0); /* RXD1 */
 749                 select_peripheral(PC(13), PERIPH_A, 0); /* RXER */
 750                 select_peripheral(PC(15), PERIPH_A, 0); /* RXDV */
 751                 select_peripheral(PC(16), PERIPH_A, 0); /* MDC  */
 752                 select_peripheral(PC(17), PERIPH_A, 0); /* MDIO */
 753
 754                 if (!data->is_rmii) {
 755                         select_peripheral(PC(0),  PERIPH_A, 0); /* COL  */
 756                         select_peripheral(PC(1),  PERIPH_A, 0); /* CRS  */
 757                         select_peripheral(PC(2),  PERIPH_A, 0); /* TXER */
 758                         select_peripheral(PC(5),  PERIPH_A, 0); /* TXD2 */
 759                         select_peripheral(PC(6),  PERIPH_A, 0); /* TXD3 */
 760                         select_peripheral(PC(11), PERIPH_A, 0); /* RXD2 */
 761                         select_peripheral(PC(12), PERIPH_A, 0); /* RXD3 */
 762                         select_peripheral(PC(14), PERIPH_A, 0); /* RXCK */
 763                         select_peripheral(PC(18), PERIPH_A, 0); /* SPD  */
 764                 }
 765                 break;
 766
 767         case 1:
 768                 pdev = &macb1_device;
 769
 770                 select_peripheral(PD(13), PERIPH_B, 0);         /* TXD0 */
 771                 select_peripheral(PD(14), PERIPH_B, 0);         /* TXD1 */
 772                 select_peripheral(PD(11), PERIPH_B, 0);         /* TXEN */
 773                 select_peripheral(PD(12), PERIPH_B, 0);         /* TXCK */
 774                 select_peripheral(PD(10), PERIPH_B, 0);         /* RXD0 */
 775                 select_peripheral(PD(6),  PERIPH_B, 0);         /* RXD1 */
 776                 select_peripheral(PD(5),  PERIPH_B, 0);         /* RXER */
 777                 select_peripheral(PD(4),  PERIPH_B, 0);         /* RXDV */
 778                 select_peripheral(PD(3),  PERIPH_B, 0);         /* MDC  */
 779                 select_peripheral(PD(2),  PERIPH_B, 0);         /* MDIO */
 780
 781                 if (!data->is_rmii) {
 782                         select_peripheral(PC(19), PERIPH_B, 0); /* COL  */
 783                         select_peripheral(PC(23), PERIPH_B, 0); /* CRS  */
 784                         select_peripheral(PC(26), PERIPH_B, 0); /* TXER */
 785                         select_peripheral(PC(27), PERIPH_B, 0); /* TXD2 */
 786                         select_peripheral(PC(28), PERIPH_B, 0); /* TXD3 */
 787                         select_peripheral(PC(29), PERIPH_B, 0); /* RXD2 */
 788                         select_peripheral(PC(30), PERIPH_B, 0); /* RXD3 */
 789                         select_peripheral(PC(24), PERIPH_B, 0); /* RXCK */
 790                         select_peripheral(PD(15), PERIPH_B, 0); /* SPD  */
 791                 }
 792                 break;
 793
 794         default:
 795                 return NULL;
 796         }
 797
 798         memcpy(pdev->dev.platform_data, data, sizeof(struct eth_platform_data));
 799         platform_device_register(pdev);
 800
 801         return pdev;
 802 }
 803
 804 /* --------------------------------------------------------------------
 805  *  SPI
 806  * -------------------------------------------------------------------- */
 807 static struct resource atmel_spi0_resource[] = {
 808         PBMEM(0xffe00000),
 809         IRQ(3),
 810 };
 811 DEFINE_DEV(atmel_spi, 0);
 812 DEV_CLK(spi_clk, atmel_spi0, pba, 0);
 813
 814 static struct resource atmel_spi1_resource[] = {
 815         PBMEM(0xffe00400),
 816         IRQ(4),
 817 };
 818 DEFINE_DEV(atmel_spi, 1);
 819 DEV_CLK(spi_clk, atmel_spi1, pba, 1);
 820
 821 static void __init
 822 at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b,
 823                       unsigned int n, const u8 *pins)
 824 {
 825         unsigned int pin, mode;
 826
 827         for (; n; n--, b++) {
 828                 b->bus_num = bus_num;
 829                 if (b->chip_select >= 4)
 830                         continue;
 831                 pin = (unsigned)b->controller_data;
 832                 if (!pin) {
 833                         pin = pins[b->chip_select];
 834                         b->controller_data = (void *)pin;
 835                 }
 836                 mode = AT32_GPIOF_OUTPUT;
 837                 if (!(b->mode & SPI_CS_HIGH))
 838                         mode |= AT32_GPIOF_HIGH;
 839                 at32_select_gpio(pin, mode);
 840         }
 841 }
 842
 843 struct platform_device *__init
 844 at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
 845 {
 846         /*
 847          * Manage the chipselects as GPIOs, normally using the same pins
 848          * the SPI controller expects; but boards can use other pins.
 849          */
 850         static u8 __initdata spi0_pins[] =
 851                 { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
 852                   GPIO_PIN_PA(5), GPIO_PIN_PA(20), };
 853         static u8 __initdata spi1_pins[] =
 854                 { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
 855                   GPIO_PIN_PB(4), GPIO_PIN_PA(27), };
 856         struct platform_device *pdev;
 857
 858         switch (id) {
 859         case 0:
 860                 pdev = &atmel_spi0_device;
 861                 select_peripheral(PA(0),  PERIPH_A, 0); /* MISO  */
 862                 select_peripheral(PA(1),  PERIPH_A, 0); /* MOSI  */
 863                 select_peripheral(PA(2),  PERIPH_A, 0); /* SCK   */
 864                 at32_spi_setup_slaves(0, b, n, spi0_pins);
 865                 break;
 866
 867         case 1:
 868                 pdev = &atmel_spi1_device;
 869                 select_peripheral(PB(0),  PERIPH_B, 0); /* MISO  */
 870                 select_peripheral(PB(1),  PERIPH_B, 0); /* MOSI  */
 871                 select_peripheral(PB(5),  PERIPH_B, 0); /* SCK   */
 872                 at32_spi_setup_slaves(1, b, n, spi1_pins);
 873                 break;
 874
 875         default:
 876                 return NULL;
 877         }
 878
 879         spi_register_board_info(b, n);
 880         platform_device_register(pdev);
 881         return pdev;
 882 }
 883
 884 /* --------------------------------------------------------------------
 885  *  LCDC
 886  * -------------------------------------------------------------------- */
 887 static struct atmel_lcdfb_info atmel_lcdfb0_data;
 888 static struct resource atmel_lcdfb0_resource[] = {
 889         {
 890                 .start          = 0xff000000,
 891                 .end            = 0xff000fff,
 892                 .flags          = IORESOURCE_MEM,
 893         },
 894         IRQ(1),
 895         {
 896                 /* Placeholder for pre-allocated fb memory */
 897                 .start          = 0x00000000,
 898                 .end            = 0x00000000,
 899                 .flags          = 0,
 900         },
 901 };
 902 DEFINE_DEV_DATA(atmel_lcdfb, 0);
 903 DEV_CLK(hck1, atmel_lcdfb0, hsb, 7);
 904 static struct clk atmel_lcdfb0_pixclk = {
 905         .name           = "lcdc_clk",
 906         .dev            = &atmel_lcdfb0_device.dev,
 907         .mode           = genclk_mode,
 908         .get_rate       = genclk_get_rate,
 909         .set_rate       = genclk_set_rate,
 910         .set_parent     = genclk_set_parent,
 911         .index          = 7,
 912 };
 913
 914 struct platform_device *__init
 915 at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
 916                      unsigned long fbmem_start, unsigned long fbmem_len)
 917 {
 918         struct platform_device *pdev;
 919         struct atmel_lcdfb_info *info;
 920         struct fb_monspecs *monspecs;
 921         struct fb_videomode *modedb;
 922         unsigned int modedb_size;
 923
 924         /*
 925          * Do a deep copy of the fb data, monspecs and modedb. Make
 926          * sure all allocations are done before setting up the
 927          * portmux.
 928          */
 929         monspecs = kmemdup(data->default_monspecs,
 930                            sizeof(struct fb_monspecs), GFP_KERNEL);
 931         if (!monspecs)
 932                 return NULL;
 933
 934         modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
 935         modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
 936         if (!modedb)
 937                 goto err_dup_modedb;
 938         monspecs->modedb = modedb;
 939
 940         switch (id) {
 941         case 0:
 942                 pdev = &atmel_lcdfb0_device;
 943                 select_peripheral(PC(19), PERIPH_A, 0); /* CC     */
 944                 select_peripheral(PC(20), PERIPH_A, 0); /* HSYNC  */
 945                 select_peripheral(PC(21), PERIPH_A, 0); /* PCLK   */
 946                 select_peripheral(PC(22), PERIPH_A, 0); /* VSYNC  */
 947                 select_peripheral(PC(23), PERIPH_A, 0); /* DVAL   */
 948                 select_peripheral(PC(24), PERIPH_A, 0); /* MODE   */
 949                 select_peripheral(PC(25), PERIPH_A, 0); /* PWR    */
 950                 select_peripheral(PC(26), PERIPH_A, 0); /* DATA0  */
 951                 select_peripheral(PC(27), PERIPH_A, 0); /* DATA1  */
 952                 select_peripheral(PC(28), PERIPH_A, 0); /* DATA2  */
 953                 select_peripheral(PC(29), PERIPH_A, 0); /* DATA3  */
 954                 select_peripheral(PC(30), PERIPH_A, 0); /* DATA4  */
 955                 select_peripheral(PC(31), PERIPH_A, 0); /* DATA5  */
 956                 select_peripheral(PD(0),  PERIPH_A, 0); /* DATA6  */
 957                 select_peripheral(PD(1),  PERIPH_A, 0); /* DATA7  */
 958                 select_peripheral(PD(2),  PERIPH_A, 0); /* DATA8  */
 959                 select_peripheral(PD(3),  PERIPH_A, 0); /* DATA9  */
 960                 select_peripheral(PD(4),  PERIPH_A, 0); /* DATA10 */
 961                 select_peripheral(PD(5),  PERIPH_A, 0); /* DATA11 */
 962                 select_peripheral(PD(6),  PERIPH_A, 0); /* DATA12 */
 963                 select_peripheral(PD(7),  PERIPH_A, 0); /* DATA13 */
 964                 select_peripheral(PD(8),  PERIPH_A, 0); /* DATA14 */
 965                 select_peripheral(PD(9),  PERIPH_A, 0); /* DATA15 */
 966                 select_peripheral(PD(10), PERIPH_A, 0); /* DATA16 */
 967                 select_peripheral(PD(11), PERIPH_A, 0); /* DATA17 */
 968                 select_peripheral(PD(12), PERIPH_A, 0); /* DATA18 */
 969                 select_peripheral(PD(13), PERIPH_A, 0); /* DATA19 */
 970                 select_peripheral(PD(14), PERIPH_A, 0); /* DATA20 */
 971                 select_peripheral(PD(15), PERIPH_A, 0); /* DATA21 */
 972                 select_peripheral(PD(16), PERIPH_A, 0); /* DATA22 */
 973                 select_peripheral(PD(17), PERIPH_A, 0); /* DATA23 */
 974
 975                 clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
 976                 clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
 977                 break;
 978
 979         default:
 980                 goto err_invalid_id;
 981         }
 982
 983         if (fbmem_len) {
 984                 pdev->resource[2].start = fbmem_start;
 985                 pdev->resource[2].end = fbmem_start + fbmem_len - 1;
 986                 pdev->resource[2].flags = IORESOURCE_MEM;
 987         }
 988
 989         info = pdev->dev.platform_data;
 990         memcpy(info, data, sizeof(struct atmel_lcdfb_info));
 991         info->default_monspecs = monspecs;
 992
 993         platform_device_register(pdev);
 994         return pdev;
 995
 996 err_invalid_id:
 997         kfree(modedb);
 998 err_dup_modedb:
 999         kfree(monspecs);
1000         return NULL;
1001 }
1002
1003 /* --------------------------------------------------------------------
1004  *  GCLK
1005  * -------------------------------------------------------------------- */
1006 static struct clk gclk0 = {
1007         .name           = "gclk0",
1008         .mode           = genclk_mode,
1009         .get_rate       = genclk_get_rate,
1010         .set_rate       = genclk_set_rate,
1011         .set_parent     = genclk_set_parent,
1012         .index          = 0,
1013 };
1014 static struct clk gclk1 = {
1015         .name           = "gclk1",
1016         .mode           = genclk_mode,
1017         .get_rate       = genclk_get_rate,
1018         .set_rate       = genclk_set_rate,
1019         .set_parent     = genclk_set_parent,
1020         .index          = 1,
1021 };
1022 static struct clk gclk2 = {
1023         .name           = "gclk2",
1024         .mode           = genclk_mode,
1025         .get_rate       = genclk_get_rate,
1026         .set_rate       = genclk_set_rate,
1027         .set_parent     = genclk_set_parent,
1028         .index          = 2,
1029 };
1030 static struct clk gclk3 = {
1031         .name           = "gclk3",
1032         .mode           = genclk_mode,
1033         .get_rate       = genclk_get_rate,
1034         .set_rate       = genclk_set_rate,
1035         .set_parent     = genclk_set_parent,
1036         .index          = 3,
1037 };
1038 static struct clk gclk4 = {
1039         .name           = "gclk4",
1040         .mode           = genclk_mode,
1041         .get_rate       = genclk_get_rate,
1042         .set_rate       = genclk_set_rate,
1043         .set_parent     = genclk_set_parent,
1044         .index          = 4,
1045 };
1046
1047 struct clk *at32_clock_list[] = {
1048         &osc32k,
1049         &osc0,
1050         &osc1,
1051         &pll0,
1052         &pll1,
1053         &cpu_clk,
1054         &hsb_clk,
1055         &pba_clk,
1056         &pbb_clk,
1057         &at32_sm_pclk,
1058         &at32_intc0_pclk,
1059         &hmatrix_clk,
1060         &ebi_clk,
1061         &hramc_clk,
1062         &smc0_pclk,
1063         &smc0_mck,
1064         &pdc_hclk,
1065         &pdc_pclk,
1066         &pico_clk,
1067         &pio0_mck,
1068         &pio1_mck,
1069         &pio2_mck,
1070         &pio3_mck,
1071         &pio4_mck,
1072         &at32_systc0_pclk,
1073         &atmel_usart0_usart,
1074         &atmel_usart1_usart,
1075         &atmel_usart2_usart,
1076         &atmel_usart3_usart,
1077         &macb0_hclk,
1078         &macb0_pclk,
1079         &macb1_hclk,
1080         &macb1_pclk,
1081         &atmel_spi0_spi_clk,
1082         &atmel_spi1_spi_clk,
1083         &atmel_lcdfb0_hck1,
1084         &atmel_lcdfb0_pixclk,
1085         &gclk0,
1086         &gclk1,
1087         &gclk2,
1088         &gclk3,
1089         &gclk4,
1090 };
1091 unsigned int at32_nr_clocks = ARRAY_SIZE(at32_clock_list);
1092
1093 void __init at32_portmux_init(void)
1094 {
1095         at32_init_pio(&pio0_device);
1096         at32_init_pio(&pio1_device);
1097         at32_init_pio(&pio2_device);
1098         at32_init_pio(&pio3_device);
1099         at32_init_pio(&pio4_device);
1100 }
1101
1102 void __init at32_clock_init(void)
1103 {
1104         struct at32_sm *sm = &system_manager;
1105         u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
1106         int i;
1107
1108         if (sm_readl(sm, PM_MCCTRL) & SM_BIT(PLLSEL))
1109                 main_clock = &pll0;
1110         else
1111                 main_clock = &osc0;
1112
1113         if (sm_readl(sm, PM_PLL0) & SM_BIT(PLLOSC))
1114                 pll0.parent = &osc1;
1115         if (sm_readl(sm, PM_PLL1) & SM_BIT(PLLOSC))
1116                 pll1.parent = &osc1;
1117
1118         genclk_init_parent(&gclk0);
1119         genclk_init_parent(&gclk1);
1120         genclk_init_parent(&gclk2);
1121         genclk_init_parent(&gclk3);
1122         genclk_init_parent(&gclk4);
1123         genclk_init_parent(&atmel_lcdfb0_pixclk);
1124
1125         /*
1126          * Turn on all clocks that have at least one user already, and
1127          * turn off everything else. We only do this for module
1128          * clocks, and even though it isn't particularly pretty to
1129          * check the address of the mode function, it should do the
1130          * trick...
1131          */
1132         for (i = 0; i < ARRAY_SIZE(at32_clock_list); i++) {
1133                 struct clk *clk = at32_clock_list[i];
1134
1135                 if (clk->users == 0)
1136                         continue;
1137
1138                 if (clk->mode == &cpu_clk_mode)
1139                         cpu_mask |= 1 << clk->index;
1140                 else if (clk->mode == &hsb_clk_mode)
1141                         hsb_mask |= 1 << clk->index;
1142                 else if (clk->mode == &pba_clk_mode)
1143                         pba_mask |= 1 << clk->index;
1144                 else if (clk->mode == &pbb_clk_mode)
1145                         pbb_mask |= 1 << clk->index;
1146         }
1147
1148         sm_writel(sm, PM_CPU_MASK, cpu_mask);
1149         sm_writel(sm, PM_HSB_MASK, hsb_mask);
1150         sm_writel(sm, PM_PBA_MASK, pba_mask);
1151         sm_writel(sm, PM_PBB_MASK, pbb_mask);
1152 }