2 * Based on arch/arm/mm/proc.S
4 * Copyright (C) 2001 Deep Blue Solutions Ltd.
5 * Copyright (C) 2012 ARM Ltd.
6 * Author: Catalin Marinas <catalin.marinas@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
23 #include <asm/assembler.h>
24 #include <asm/asm-offsets.h>
25 #include <asm/hwcap.h>
26 #include <asm/pgtable.h>
27 #include <asm/pgtable-hwdef.h>
28 #include <asm/cpufeature.h>
29 #include <asm/alternative.h>
31 #ifdef CONFIG_ARM64_64K_PAGES
32 #define TCR_TG_FLAGS TCR_TG0_64K | TCR_TG1_64K
33 #elif defined(CONFIG_ARM64_16K_PAGES)
34 #define TCR_TG_FLAGS TCR_TG0_16K | TCR_TG1_16K
35 #else /* CONFIG_ARM64_4K_PAGES */
36 #define TCR_TG_FLAGS TCR_TG0_4K | TCR_TG1_4K
39 #ifdef CONFIG_RANDOMIZE_BASE
40 #define TCR_KASLR_FLAGS TCR_NFD1
42 #define TCR_KASLR_FLAGS 0
45 #define TCR_SMP_FLAGS TCR_SHARED
47 /* PTWs cacheable, inner/outer WBWA */
48 #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
50 #ifdef CONFIG_KASAN_SW_TAGS
51 #define TCR_KASAN_FLAGS TCR_TBI1
53 #define TCR_KASAN_FLAGS 0
56 #define MAIR(attr, mt) ((attr) << ((mt) * 8))
60 * cpu_do_suspend - save CPU registers context
62 * x0: virtual address of context pointer
67 mrs x4, contextidr_el1
75 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
85 stp x10, x11, [x0, #64]
86 stp x12, x13, [x0, #80]
88 ENDPROC(cpu_do_suspend)
91 * cpu_do_resume - restore CPU register context
93 * x0: Address of context pointer
95 .pushsection ".idmap.text", "awx"
100 ldp x9, x10, [x0, #48]
101 ldp x11, x12, [x0, #64]
102 ldp x13, x14, [x0, #80]
105 msr contextidr_el1, x4
108 /* Don't change t0sz here, mask those bits when restoring */
110 bfi x8, x7, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
116 * __cpu_setup() cleared MDSCR_EL1.MDE and friends, before unmasking
117 * debug exceptions. By restoring MDSCR_EL1 here, we may take a debug
118 * exception. Mask them until local_daif_restore() in cpu_suspend()
125 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN
132 * Restore oslsr_el1 by writing oslar_el1
135 ubfx x11, x11, #1, #1
137 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
139 alternative_if ARM64_HAS_RAS_EXTN
140 msr_s SYS_DISR_EL1, xzr
141 alternative_else_nop_endif
145 ENDPROC(cpu_do_resume)
150 * cpu_do_switch_mm(pgd_phys, tsk)
152 * Set the translation table base pointer to be pgd_phys.
154 * - pgd_phys - physical address of new TTB
156 ENTRY(cpu_do_switch_mm)
158 mmid x1, x1 // get mm->context.id
161 alternative_if ARM64_HAS_CNP
162 cbz x1, 1f // skip CNP for reserved ASID
163 orr x3, x3, #TTBR_CNP_BIT
165 alternative_else_nop_endif
166 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
167 bfi x3, x1, #48, #16 // set the ASID field in TTBR0
169 bfi x2, x1, #48, #16 // set the ASID
170 msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
172 msr ttbr0_el1, x3 // now update TTBR0
174 b post_ttbr_update_workaround // Back to C code...
175 ENDPROC(cpu_do_switch_mm)
177 .pushsection ".idmap.text", "awx"
179 .macro __idmap_cpu_set_reserved_ttbr1, tmp1, tmp2
180 adrp \tmp1, empty_zero_page
181 phys_to_ttbr \tmp2, \tmp1
191 * void idmap_cpu_replace_ttbr1(phys_addr_t ttbr1)
193 * This is the low-level counterpart to cpu_replace_ttbr1, and should not be
194 * called by anything else. It can only be executed from a TTBR0 mapping.
196 ENTRY(idmap_cpu_replace_ttbr1)
197 save_and_disable_daif flags=x2
199 __idmap_cpu_set_reserved_ttbr1 x1, x3
208 ENDPROC(idmap_cpu_replace_ttbr1)
211 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
212 .pushsection ".idmap.text", "awx"
214 .macro __idmap_kpti_get_pgtable_ent, type
215 dc cvac, cur_\()\type\()p // Ensure any existing dirty
216 dmb sy // lines are written back before
217 ldr \type, [cur_\()\type\()p] // loading the entry
218 tbz \type, #0, skip_\()\type // Skip invalid and
219 tbnz \type, #11, skip_\()\type // non-global entries
222 .macro __idmap_kpti_put_pgtable_ent_ng, type
223 orr \type, \type, #PTE_NG // Same bit for blocks and pages
224 str \type, [cur_\()\type\()p] // Update the entry and ensure
225 dmb sy // that it is visible to all
226 dc civac, cur_\()\type\()p // CPUs.
230 * void __kpti_install_ng_mappings(int cpu, int num_cpus, phys_addr_t swapper)
232 * Called exactly once from stop_machine context by each CPU found during boot.
236 ENTRY(idmap_kpti_install_ng_mappings)
255 mrs swapper_ttb, ttbr1_el1
256 restore_ttbr1 swapper_ttb
257 adr flag_ptr, __idmap_kpti_flag
259 cbnz cpu, __idmap_kpti_secondary
261 /* We're the boot CPU. Wait for the others to catch up */
264 ldaxr w18, [flag_ptr]
265 eor w18, w18, num_cpus
268 /* We need to walk swapper, so turn off the MMU. */
269 pre_disable_mmu_workaround
271 bic x18, x18, #SCTLR_ELx_M
275 /* Everybody is enjoying the idmap, so we can rewrite swapper. */
277 mov cur_pgdp, swapper_pa
278 add end_pgdp, cur_pgdp, #(PTRS_PER_PGD * 8)
279 do_pgd: __idmap_kpti_get_pgtable_ent pgd
280 tbnz pgd, #1, walk_puds
282 __idmap_kpti_put_pgtable_ent_ng pgd
284 add cur_pgdp, cur_pgdp, #8
285 cmp cur_pgdp, end_pgdp
288 /* Publish the updated tables and nuke all the TLBs */
294 /* We're done: fire up the MMU again */
296 orr x18, x18, #SCTLR_ELx_M
300 /* Set the flag to zero to indicate that we're all done */
306 .if CONFIG_PGTABLE_LEVELS > 3
307 pte_to_phys cur_pudp, pgd
308 add end_pudp, cur_pudp, #(PTRS_PER_PUD * 8)
309 do_pud: __idmap_kpti_get_pgtable_ent pud
310 tbnz pud, #1, walk_pmds
312 __idmap_kpti_put_pgtable_ent_ng pud
314 add cur_pudp, cur_pudp, 8
315 cmp cur_pudp, end_pudp
318 .else /* CONFIG_PGTABLE_LEVELS <= 3 */
327 .if CONFIG_PGTABLE_LEVELS > 2
328 pte_to_phys cur_pmdp, pud
329 add end_pmdp, cur_pmdp, #(PTRS_PER_PMD * 8)
330 do_pmd: __idmap_kpti_get_pgtable_ent pmd
331 tbnz pmd, #1, walk_ptes
333 __idmap_kpti_put_pgtable_ent_ng pmd
335 add cur_pmdp, cur_pmdp, #8
336 cmp cur_pmdp, end_pmdp
339 .else /* CONFIG_PGTABLE_LEVELS <= 2 */
348 pte_to_phys cur_ptep, pmd
349 add end_ptep, cur_ptep, #(PTRS_PER_PTE * 8)
350 do_pte: __idmap_kpti_get_pgtable_ent pte
351 __idmap_kpti_put_pgtable_ent_ng pte
353 add cur_ptep, cur_ptep, #8
354 cmp cur_ptep, end_ptep
358 /* Secondary CPUs end up here */
359 __idmap_kpti_secondary:
360 /* Uninstall swapper before surgery begins */
361 __idmap_cpu_set_reserved_ttbr1 x18, x17
363 /* Increment the flag to let the boot CPU we're ready */
364 1: ldxr w18, [flag_ptr]
366 stxr w17, w18, [flag_ptr]
369 /* Wait for the boot CPU to finish messing around with swapper */
375 /* All done, act like nothing happened */
376 offset_ttbr1 swapper_ttb
377 msr ttbr1_el1, swapper_ttb
398 ENDPROC(idmap_kpti_install_ng_mappings)
405 * Initialise the processor for turning the MMU on. Return in x0 the
406 * value of the SCTLR_EL1 register.
408 .pushsection ".idmap.text", "awx"
410 tlbi vmalle1 // Invalidate local TLB
414 msr cpacr_el1, x0 // Enable FP/ASIMD
415 mov x0, #1 << 12 // Reset mdscr_el1 and disable
416 msr mdscr_el1, x0 // access to the DCC from EL0
417 isb // Unmask debug exceptions now,
418 enable_dbg // since this is per-cpu
419 reset_pmuserenr_el0 x0 // Disable PMU access from EL0
421 * Memory region attributes for LPAE:
425 * DEVICE_nGnRnE 000 00000000
426 * DEVICE_nGnRE 001 00000100
427 * DEVICE_GRE 010 00001100
428 * NORMAL_NC 011 01000100
429 * NORMAL 100 11111111
430 * NORMAL_WT 101 10111011
432 ldr x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
433 MAIR(0x04, MT_DEVICE_nGnRE) | \
434 MAIR(0x0c, MT_DEVICE_GRE) | \
435 MAIR(0x44, MT_NORMAL_NC) | \
436 MAIR(0xff, MT_NORMAL) | \
437 MAIR(0xbb, MT_NORMAL_WT)
442 mov_q x0, SCTLR_EL1_SET
444 * Set/prepare TCR and TTBR. We use 512GB (39-bit) address range for
445 * both user and kernel.
447 ldr x10, =TCR_TxSZ(VA_BITS) | TCR_CACHE_FLAGS | TCR_SMP_FLAGS | \
448 TCR_TG_FLAGS | TCR_KASLR_FLAGS | TCR_ASID16 | \
449 TCR_TBI0 | TCR_A1 | TCR_KASAN_FLAGS
450 tcr_clear_errata_bits x10, x9, x5
452 #ifdef CONFIG_ARM64_USER_VA_BITS_52
453 ldr_l x9, vabits_user
462 * Set the IPS bits in TCR_EL1.
464 tcr_compute_pa_size x10, #TCR_IPS_SHIFT, x5, x6
465 #ifdef CONFIG_ARM64_HW_AFDBM
467 * Enable hardware update of the Access Flags bit.
468 * Hardware dirty bit management is enabled later,
471 mrs x9, ID_AA64MMFR1_EL1
474 orr x10, x10, #TCR_HA // hardware Access flag update
476 #endif /* CONFIG_ARM64_HW_AFDBM */
478 ret // return to head.S