arch/arm64/kvm/hyp/vgic-v3-sr.c

   1 /*
   2  * Copyright (C) 2012-2015 - ARM Ltd
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/compiler.h>
  19 #include <linux/irqchip/arm-gic-v3.h>
  20 #include <linux/kvm_host.h>
  21
  22 #include <asm/kvm_hyp.h>
  23
  24 #define vtr_to_max_lr_idx(v)            ((v) & 0xf)
  25 #define vtr_to_nr_pri_bits(v)           (((u32)(v) >> 29) + 1)
  26
  27 #define read_gicreg(r)                                                  \
  28         ({                                                              \
  29                 u64 reg;                                                \
  30                 asm volatile("mrs_s %0, " __stringify(r) : "=r" (reg)); \
  31                 reg;                                                    \
  32         })
  33
  34 #define write_gicreg(v,r)                                               \
  35         do {                                                            \
  36                 u64 __val = (v);                                        \
  37                 asm volatile("msr_s " __stringify(r) ", %0" : : "r" (__val));\
  38         } while (0)
  39
  40 static u64 __hyp_text __gic_v3_get_lr(unsigned int lr)
  41 {
  42         switch (lr & 0xf) {
  43         case 0:
  44                 return read_gicreg(ICH_LR0_EL2);
  45         case 1:
  46                 return read_gicreg(ICH_LR1_EL2);
  47         case 2:
  48                 return read_gicreg(ICH_LR2_EL2);
  49         case 3:
  50                 return read_gicreg(ICH_LR3_EL2);
  51         case 4:
  52                 return read_gicreg(ICH_LR4_EL2);
  53         case 5:
  54                 return read_gicreg(ICH_LR5_EL2);
  55         case 6:
  56                 return read_gicreg(ICH_LR6_EL2);
  57         case 7:
  58                 return read_gicreg(ICH_LR7_EL2);
  59         case 8:
  60                 return read_gicreg(ICH_LR8_EL2);
  61         case 9:
  62                 return read_gicreg(ICH_LR9_EL2);
  63         case 10:
  64                 return read_gicreg(ICH_LR10_EL2);
  65         case 11:
  66                 return read_gicreg(ICH_LR11_EL2);
  67         case 12:
  68                 return read_gicreg(ICH_LR12_EL2);
  69         case 13:
  70                 return read_gicreg(ICH_LR13_EL2);
  71         case 14:
  72                 return read_gicreg(ICH_LR14_EL2);
  73         case 15:
  74                 return read_gicreg(ICH_LR15_EL2);
  75         }
  76
  77         unreachable();
  78 }
  79
  80 static void __hyp_text __gic_v3_set_lr(u64 val, int lr)
  81 {
  82         switch (lr & 0xf) {
  83         case 0:
  84                 write_gicreg(val, ICH_LR0_EL2);
  85                 break;
  86         case 1:
  87                 write_gicreg(val, ICH_LR1_EL2);
  88                 break;
  89         case 2:
  90                 write_gicreg(val, ICH_LR2_EL2);
  91                 break;
  92         case 3:
  93                 write_gicreg(val, ICH_LR3_EL2);
  94                 break;
  95         case 4:
  96                 write_gicreg(val, ICH_LR4_EL2);
  97                 break;
  98         case 5:
  99                 write_gicreg(val, ICH_LR5_EL2);
 100                 break;
 101         case 6:
 102                 write_gicreg(val, ICH_LR6_EL2);
 103                 break;
 104         case 7:
 105                 write_gicreg(val, ICH_LR7_EL2);
 106                 break;
 107         case 8:
 108                 write_gicreg(val, ICH_LR8_EL2);
 109                 break;
 110         case 9:
 111                 write_gicreg(val, ICH_LR9_EL2);
 112                 break;
 113         case 10:
 114                 write_gicreg(val, ICH_LR10_EL2);
 115                 break;
 116         case 11:
 117                 write_gicreg(val, ICH_LR11_EL2);
 118                 break;
 119         case 12:
 120                 write_gicreg(val, ICH_LR12_EL2);
 121                 break;
 122         case 13:
 123                 write_gicreg(val, ICH_LR13_EL2);
 124                 break;
 125         case 14:
 126                 write_gicreg(val, ICH_LR14_EL2);
 127                 break;
 128         case 15:
 129                 write_gicreg(val, ICH_LR15_EL2);
 130                 break;
 131         }
 132 }
 133
 134 static void __hyp_text save_maint_int_state(struct kvm_vcpu *vcpu, int nr_lr)
 135 {
 136         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 137         int i;
 138         bool expect_mi;
 139
 140         expect_mi = !!(cpu_if->vgic_hcr & ICH_HCR_UIE);
 141
 142         for (i = 0; i < nr_lr; i++) {
 143                 if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
 144                                 continue;
 145
 146                 expect_mi |= (!(cpu_if->vgic_lr[i] & ICH_LR_HW) &&
 147                               (cpu_if->vgic_lr[i] & ICH_LR_EOI));
 148         }
 149
 150         if (expect_mi) {
 151                 cpu_if->vgic_misr  = read_gicreg(ICH_MISR_EL2);
 152
 153                 if (cpu_if->vgic_misr & ICH_MISR_EOI)
 154                         cpu_if->vgic_eisr = read_gicreg(ICH_EISR_EL2);
 155                 else
 156                         cpu_if->vgic_eisr = 0;
 157         } else {
 158                 cpu_if->vgic_misr = 0;
 159                 cpu_if->vgic_eisr = 0;
 160         }
 161 }
 162
 163 void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
 164 {
 165         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 166         u64 val;
 167
 168         /*
 169          * Make sure stores to the GIC via the memory mapped interface
 170          * are now visible to the system register interface.
 171          */
 172         if (!cpu_if->vgic_sre)
 173                 dsb(st);
 174
 175         cpu_if->vgic_vmcr  = read_gicreg(ICH_VMCR_EL2);
 176
 177         if (vcpu->arch.vgic_cpu.live_lrs) {
 178                 int i;
 179                 u32 max_lr_idx, nr_pri_bits;
 180
 181                 cpu_if->vgic_elrsr = read_gicreg(ICH_ELSR_EL2);
 182
 183                 write_gicreg(0, ICH_HCR_EL2);
 184                 val = read_gicreg(ICH_VTR_EL2);
 185                 max_lr_idx = vtr_to_max_lr_idx(val);
 186                 nr_pri_bits = vtr_to_nr_pri_bits(val);
 187
 188                 save_maint_int_state(vcpu, max_lr_idx + 1);
 189
 190                 for (i = 0; i <= max_lr_idx; i++) {
 191                         if (!(vcpu->arch.vgic_cpu.live_lrs & (1UL << i)))
 192                                 continue;
 193
 194                         if (cpu_if->vgic_elrsr & (1 << i))
 195                                 cpu_if->vgic_lr[i] &= ~ICH_LR_STATE;
 196                         else
 197                                 cpu_if->vgic_lr[i] = __gic_v3_get_lr(i);
 198
 199                         __gic_v3_set_lr(0, i);
 200                 }
 201
 202                 switch (nr_pri_bits) {
 203                 case 7:
 204                         cpu_if->vgic_ap0r[3] = read_gicreg(ICH_AP0R3_EL2);
 205                         cpu_if->vgic_ap0r[2] = read_gicreg(ICH_AP0R2_EL2);
 206                 case 6:
 207                         cpu_if->vgic_ap0r[1] = read_gicreg(ICH_AP0R1_EL2);
 208                 default:
 209                         cpu_if->vgic_ap0r[0] = read_gicreg(ICH_AP0R0_EL2);
 210                 }
 211
 212                 switch (nr_pri_bits) {
 213                 case 7:
 214                         cpu_if->vgic_ap1r[3] = read_gicreg(ICH_AP1R3_EL2);
 215                         cpu_if->vgic_ap1r[2] = read_gicreg(ICH_AP1R2_EL2);
 216                 case 6:
 217                         cpu_if->vgic_ap1r[1] = read_gicreg(ICH_AP1R1_EL2);
 218                 default:
 219                         cpu_if->vgic_ap1r[0] = read_gicreg(ICH_AP1R0_EL2);
 220                 }
 221
 222                 vcpu->arch.vgic_cpu.live_lrs = 0;
 223         } else {
 224                 cpu_if->vgic_misr  = 0;
 225                 cpu_if->vgic_eisr  = 0;
 226                 cpu_if->vgic_elrsr = 0xffff;
 227                 cpu_if->vgic_ap0r[0] = 0;
 228                 cpu_if->vgic_ap0r[1] = 0;
 229                 cpu_if->vgic_ap0r[2] = 0;
 230                 cpu_if->vgic_ap0r[3] = 0;
 231                 cpu_if->vgic_ap1r[0] = 0;
 232                 cpu_if->vgic_ap1r[1] = 0;
 233                 cpu_if->vgic_ap1r[2] = 0;
 234                 cpu_if->vgic_ap1r[3] = 0;
 235         }
 236
 237         val = read_gicreg(ICC_SRE_EL2);
 238         write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2);
 239
 240         if (!cpu_if->vgic_sre) {
 241                 /* Make sure ENABLE is set at EL2 before setting SRE at EL1 */
 242                 isb();
 243                 write_gicreg(1, ICC_SRE_EL1);
 244         }
 245 }
 246
 247 void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
 248 {
 249         struct vgic_v3_cpu_if *cpu_if = &vcpu->arch.vgic_cpu.vgic_v3;
 250         u64 val;
 251         u32 max_lr_idx, nr_pri_bits;
 252         u16 live_lrs = 0;
 253         int i;
 254
 255         /*
 256          * VFIQEn is RES1 if ICC_SRE_EL1.SRE is 1. This causes a
 257          * Group0 interrupt (as generated in GICv2 mode) to be
 258          * delivered as a FIQ to the guest, with potentially fatal
 259          * consequences. So we must make sure that ICC_SRE_EL1 has
 260          * been actually programmed with the value we want before
 261          * starting to mess with the rest of the GIC.
 262          */
 263         if (!cpu_if->vgic_sre) {
 264                 write_gicreg(0, ICC_SRE_EL1);
 265                 isb();
 266         }
 267
 268         val = read_gicreg(ICH_VTR_EL2);
 269         max_lr_idx = vtr_to_max_lr_idx(val);
 270         nr_pri_bits = vtr_to_nr_pri_bits(val);
 271
 272         for (i = 0; i <= max_lr_idx; i++) {
 273                 if (cpu_if->vgic_lr[i] & ICH_LR_STATE)
 274                         live_lrs |= (1 << i);
 275         }
 276
 277         write_gicreg(cpu_if->vgic_vmcr, ICH_VMCR_EL2);
 278
 279         if (live_lrs) {
 280                 write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
 281
 282                 switch (nr_pri_bits) {
 283                 case 7:
 284                         write_gicreg(cpu_if->vgic_ap0r[3], ICH_AP0R3_EL2);
 285                         write_gicreg(cpu_if->vgic_ap0r[2], ICH_AP0R2_EL2);
 286                 case 6:
 287                         write_gicreg(cpu_if->vgic_ap0r[1], ICH_AP0R1_EL2);
 288                 default:
 289                         write_gicreg(cpu_if->vgic_ap0r[0], ICH_AP0R0_EL2);
 290                 }
 291
 292                 switch (nr_pri_bits) {
 293                 case 7:
 294                         write_gicreg(cpu_if->vgic_ap1r[3], ICH_AP1R3_EL2);
 295                         write_gicreg(cpu_if->vgic_ap1r[2], ICH_AP1R2_EL2);
 296                 case 6:
 297                         write_gicreg(cpu_if->vgic_ap1r[1], ICH_AP1R1_EL2);
 298                 default:
 299                         write_gicreg(cpu_if->vgic_ap1r[0], ICH_AP1R0_EL2);
 300                 }
 301
 302                 for (i = 0; i <= max_lr_idx; i++) {
 303                         if (!(live_lrs & (1 << i)))
 304                                 continue;
 305
 306                         __gic_v3_set_lr(cpu_if->vgic_lr[i], i);
 307                 }
 308         }
 309
 310         /*
 311          * Ensures that the above will have reached the
 312          * (re)distributors. This ensure the guest will read the
 313          * correct values from the memory-mapped interface.
 314          */
 315         if (!cpu_if->vgic_sre) {
 316                 isb();
 317                 dsb(sy);
 318         }
 319         vcpu->arch.vgic_cpu.live_lrs = live_lrs;
 320
 321         /*
 322          * Prevent the guest from touching the GIC system registers if
 323          * SRE isn't enabled for GICv3 emulation.
 324          */
 325         write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE,
 326                      ICC_SRE_EL2);
 327 }
 328
 329 void __hyp_text __vgic_v3_init_lrs(void)
 330 {
 331         int max_lr_idx = vtr_to_max_lr_idx(read_gicreg(ICH_VTR_EL2));
 332         int i;
 333
 334         for (i = 0; i <= max_lr_idx; i++)
 335                 __gic_v3_set_lr(0, i);
 336 }
 337
 338 static u64 __hyp_text __vgic_v3_read_ich_vtr_el2(void)
 339 {
 340         return read_gicreg(ICH_VTR_EL2);
 341 }
 342
 343 __alias(__vgic_v3_read_ich_vtr_el2) u64 __vgic_v3_get_ich_vtr_el2(void);