arch/arm64/kernel/perf_event.c

   1 /*
   2  * PMU support
   3  *
   4  * Copyright (C) 2012 ARM Limited
   5  * Author: Will Deacon <will.deacon@arm.com>
   6  *
   7  * This code is based heavily on the ARMv7 perf event code.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <asm/irq_regs.h>
  23 #include <asm/virt.h>
  24
  25 #include <linux/of.h>
  26 #include <linux/perf/arm_pmu.h>
  27 #include <linux/platform_device.h>
  28
  29 /*
  30  * ARMv8 PMUv3 Performance Events handling code.
  31  * Common event types.
  32  */
  33
  34 /* Required events. */
  35 #define ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR                        0x00
  36 #define ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL                    0x03
  37 #define ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS                    0x04
  38 #define ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED                  0x10
  39 #define ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES                        0x11
  40 #define ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED                      0x12
  41
  42 /* At least one of the following is required. */
  43 #define ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED                      0x08
  44 #define ARMV8_PMUV3_PERFCTR_OP_SPEC                             0x1B
  45
  46 /* Common architectural events. */
  47 #define ARMV8_PMUV3_PERFCTR_MEM_READ                            0x06
  48 #define ARMV8_PMUV3_PERFCTR_MEM_WRITE                           0x07
  49 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           0x09
  50 #define ARMV8_PMUV3_PERFCTR_EXC_EXECUTED                        0x0A
  51 #define ARMV8_PMUV3_PERFCTR_CID_WRITE                           0x0B
  52 #define ARMV8_PMUV3_PERFCTR_PC_WRITE                            0x0C
  53 #define ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH                       0x0D
  54 #define ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN                      0x0E
  55 #define ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS                0x0F
  56 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE                          0x1C
  57 #define ARMV8_PMUV3_PERFCTR_CHAIN                               0x1E
  58 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED                          0x21
  59
  60 /* Common microarchitectural events. */
  61 #define ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL                    0x01
  62 #define ARMV8_PMUV3_PERFCTR_ITLB_REFILL                         0x02
  63 #define ARMV8_PMUV3_PERFCTR_DTLB_REFILL                         0x05
  64 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          0x13
  65 #define ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS                    0x14
  66 #define ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB                        0x15
  67 #define ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS                     0x16
  68 #define ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL                     0x17
  69 #define ARMV8_PMUV3_PERFCTR_L2_CACHE_WB                         0x18
  70 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          0x19
  71 #define ARMV8_PMUV3_PERFCTR_MEM_ERROR                           0x1A
  72 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          0x1D
  73 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE                  0x1F
  74 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE                  0x20
  75 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED                 0x22
  76 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND                      0x23
  77 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND                       0x24
  78 #define ARMV8_PMUV3_PERFCTR_L1D_TLB                             0x25
  79 #define ARMV8_PMUV3_PERFCTR_L1I_TLB                             0x26
  80 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE                           0x27
  81 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL                    0x28
  82 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE                  0x29
  83 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL                    0x2A
  84 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE                           0x2B
  85 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB                        0x2C
  86 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL                      0x2D
  87 #define ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL                      0x2E
  88 #define ARMV8_PMUV3_PERFCTR_L2D_TLB                             0x2F
  89 #define ARMV8_PMUV3_PERFCTR_L21_TLB                             0x30
  90
  91 /* ARMv8 implementation defined event types. */
  92 #define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_LD                0x40
  93 #define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_ST                0x41
  94 #define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_LD                0x42
  95 #define ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_ST                0x43
  96 #define ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_LD                     0x4C
  97 #define ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_ST                     0x4D
  98 #define ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_LD                     0x4E
  99 #define ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_ST                     0x4F
 100
 101 /* ARMv8 Cortex-A53 specific event types. */
 102 #define ARMV8_A53_PERFCTR_PREFETCH_LINEFILL                     0xC2
 103
 104 /* ARMv8 Cavium ThunderX specific event types. */
 105 #define ARMV8_THUNDER_PERFCTR_L1_DCACHE_MISS_ST                 0xE9
 106 #define ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_ACCESS             0xEA
 107 #define ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_MISS               0xEB
 108 #define ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_ACCESS             0xEC
 109 #define ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_MISS               0xED
 110
 111 /* PMUv3 HW events mapping. */
 112 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 113         PERF_MAP_ALL_UNSUPPORTED,
 114         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
 115         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
 116         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 117         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 118         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 119 };
 120
 121 /* ARM Cortex-A53 HW events mapping. */
 122 static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
 123         PERF_MAP_ALL_UNSUPPORTED,
 124         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
 125         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
 126         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 127         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 128         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE,
 129         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 130         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 131 };
 132
 133 /* ARM Cortex-A57 and Cortex-A72 events mapping. */
 134 static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
 135         PERF_MAP_ALL_UNSUPPORTED,
 136         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
 137         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
 138         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 139         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 140         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 141         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 142 };
 143
 144 static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
 145         PERF_MAP_ALL_UNSUPPORTED,
 146         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES,
 147         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED,
 148         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 149         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 150         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE,
 151         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 152         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 153         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 154 };
 155
 156 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 157                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 158                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 159         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 160
 161         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 162         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 163         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 164         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 165
 166         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 167         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 168         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 169         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 170 };
 171
 172 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 173                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 174                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 175         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 176
 177         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 178         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 179         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS,
 180         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL,
 181         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREFETCH_LINEFILL,
 182
 183         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
 184         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
 185
 186         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
 187
 188         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 189         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 190         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 191         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 192 };
 193
 194 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 195                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 196                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 197         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 198
 199         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_LD,
 200         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_LD,
 201         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_ST,
 202         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_ST,
 203
 204         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
 205         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
 206
 207         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_LD,
 208         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_ST,
 209
 210         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
 211
 212         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 213         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 214         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 215         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 216 };
 217
 218 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 219                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 220                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 221         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 222
 223         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_LD,
 224         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_REFILL_LD,
 225         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1_DCACHE_ACCESS_ST,
 226         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1_DCACHE_MISS_ST,
 227         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_ACCESS,
 228         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1_DCACHE_PREF_MISS,
 229
 230         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS,
 231         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL,
 232         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_ACCESS,
 233         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1_ICACHE_PREF_MISS,
 234
 235         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_LD,
 236         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_LD,
 237         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_DTLB_ACCESS_ST,
 238         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_DTLB_REFILL_ST,
 239
 240         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_ITLB_REFILL,
 241
 242         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 243         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 244         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED,
 245         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED,
 246 };
 247
 248 #define ARMV8_EVENT_ATTR_RESOLVE(m) #m
 249 #define ARMV8_EVENT_ATTR(name, config) \
 250         PMU_EVENT_ATTR_STRING(name, armv8_event_attr_##name, \
 251                               "event=" ARMV8_EVENT_ATTR_RESOLVE(config))
 252
 253 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_PMNC_SW_INCR);
 254 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1_ICACHE_REFILL);
 255 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_ITLB_REFILL);
 256 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1_DCACHE_REFILL);
 257 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1_DCACHE_ACCESS);
 258 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_DTLB_REFILL);
 259 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_MEM_READ);
 260 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_MEM_WRITE);
 261 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INSTR_EXECUTED);
 262 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
 263 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_EXECUTED);
 264 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE);
 265 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE);
 266 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_PC_IMM_BRANCH);
 267 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_PC_PROC_RETURN);
 268 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_MEM_UNALIGNED_ACCESS);
 269 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_MIS_PRED);
 270 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES);
 271 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_PC_BRANCH_PRED);
 272 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
 273 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1_ICACHE_ACCESS);
 274 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1_DCACHE_WB);
 275 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2_CACHE_ACCESS);
 276 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2_CACHE_REFILL);
 277 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2_CACHE_WB);
 278 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
 279 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEM_ERROR);
 280 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_OP_SPEC);
 281 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE);
 282 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
 283 ARMV8_EVENT_ATTR(chain, ARMV8_PMUV3_PERFCTR_CHAIN);
 284 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
 285 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
 286 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
 287 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
 288 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
 289 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
 290 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
 291 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
 292 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
 293 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
 294 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
 295 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
 296 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
 297 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
 298 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
 299 ARMV8_EVENT_ATTR(l21_tlb_refill, ARMV8_PMUV3_PERFCTR_L21_TLB_REFILL);
 300 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
 301 ARMV8_EVENT_ATTR(l21_tlb, ARMV8_PMUV3_PERFCTR_L21_TLB);
 302
 303 static struct attribute *armv8_pmuv3_event_attrs[] = {
 304         &armv8_event_attr_sw_incr.attr.attr,
 305         &armv8_event_attr_l1i_cache_refill.attr.attr,
 306         &armv8_event_attr_l1i_tlb_refill.attr.attr,
 307         &armv8_event_attr_l1d_cache_refill.attr.attr,
 308         &armv8_event_attr_l1d_cache.attr.attr,
 309         &armv8_event_attr_l1d_tlb_refill.attr.attr,
 310         &armv8_event_attr_ld_retired.attr.attr,
 311         &armv8_event_attr_st_retired.attr.attr,
 312         &armv8_event_attr_inst_retired.attr.attr,
 313         &armv8_event_attr_exc_taken.attr.attr,
 314         &armv8_event_attr_exc_return.attr.attr,
 315         &armv8_event_attr_cid_write_retired.attr.attr,
 316         &armv8_event_attr_pc_write_retired.attr.attr,
 317         &armv8_event_attr_br_immed_retired.attr.attr,
 318         &armv8_event_attr_br_return_retired.attr.attr,
 319         &armv8_event_attr_unaligned_ldst_retired.attr.attr,
 320         &armv8_event_attr_br_mis_pred.attr.attr,
 321         &armv8_event_attr_cpu_cycles.attr.attr,
 322         &armv8_event_attr_br_pred.attr.attr,
 323         &armv8_event_attr_mem_access.attr.attr,
 324         &armv8_event_attr_l1i_cache.attr.attr,
 325         &armv8_event_attr_l1d_cache_wb.attr.attr,
 326         &armv8_event_attr_l2d_cache.attr.attr,
 327         &armv8_event_attr_l2d_cache_refill.attr.attr,
 328         &armv8_event_attr_l2d_cache_wb.attr.attr,
 329         &armv8_event_attr_bus_access.attr.attr,
 330         &armv8_event_attr_memory_error.attr.attr,
 331         &armv8_event_attr_inst_spec.attr.attr,
 332         &armv8_event_attr_ttbr_write_retired.attr.attr,
 333         &armv8_event_attr_bus_cycles.attr.attr,
 334         &armv8_event_attr_chain.attr.attr,
 335         &armv8_event_attr_l1d_cache_allocate.attr.attr,
 336         &armv8_event_attr_l2d_cache_allocate.attr.attr,
 337         &armv8_event_attr_br_retired.attr.attr,
 338         &armv8_event_attr_br_mis_pred_retired.attr.attr,
 339         &armv8_event_attr_stall_frontend.attr.attr,
 340         &armv8_event_attr_stall_backend.attr.attr,
 341         &armv8_event_attr_l1d_tlb.attr.attr,
 342         &armv8_event_attr_l1i_tlb.attr.attr,
 343         &armv8_event_attr_l2i_cache.attr.attr,
 344         &armv8_event_attr_l2i_cache_refill.attr.attr,
 345         &armv8_event_attr_l3d_cache_allocate.attr.attr,
 346         &armv8_event_attr_l3d_cache_refill.attr.attr,
 347         &armv8_event_attr_l3d_cache.attr.attr,
 348         &armv8_event_attr_l3d_cache_wb.attr.attr,
 349         &armv8_event_attr_l2d_tlb_refill.attr.attr,
 350         &armv8_event_attr_l21_tlb_refill.attr.attr,
 351         &armv8_event_attr_l2d_tlb.attr.attr,
 352         &armv8_event_attr_l21_tlb.attr.attr,
 353         NULL,
 354 };
 355
 356 static struct attribute_group armv8_pmuv3_events_attr_group = {
 357         .name = "events",
 358         .attrs = armv8_pmuv3_event_attrs,
 359 };
 360
 361 PMU_FORMAT_ATTR(event, "config:0-9");
 362
 363 static struct attribute *armv8_pmuv3_format_attrs[] = {
 364         &format_attr_event.attr,
 365         NULL,
 366 };
 367
 368 static struct attribute_group armv8_pmuv3_format_attr_group = {
 369         .name = "format",
 370         .attrs = armv8_pmuv3_format_attrs,
 371 };
 372
 373 static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
 374         &armv8_pmuv3_events_attr_group,
 375         &armv8_pmuv3_format_attr_group,
 376         NULL,
 377 };
 378
 379 /*
 380  * Perf Events' indices
 381  */
 382 #define ARMV8_IDX_CYCLE_COUNTER 0
 383 #define ARMV8_IDX_COUNTER0      1
 384 #define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
 385         (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 386
 387 #define ARMV8_MAX_COUNTERS      32
 388 #define ARMV8_COUNTER_MASK      (ARMV8_MAX_COUNTERS - 1)
 389
 390 /*
 391  * ARMv8 low level PMU access
 392  */
 393
 394 /*
 395  * Perf Event to low level counters mapping
 396  */
 397 #define ARMV8_IDX_TO_COUNTER(x) \
 398         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
 399
 400 /*
 401  * Per-CPU PMCR: config reg
 402  */
 403 #define ARMV8_PMCR_E            (1 << 0) /* Enable all counters */
 404 #define ARMV8_PMCR_P            (1 << 1) /* Reset all counters */
 405 #define ARMV8_PMCR_C            (1 << 2) /* Cycle counter reset */
 406 #define ARMV8_PMCR_D            (1 << 3) /* CCNT counts every 64th cpu cycle */
 407 #define ARMV8_PMCR_X            (1 << 4) /* Export to ETM */
 408 #define ARMV8_PMCR_DP           (1 << 5) /* Disable CCNT if non-invasive debug*/
 409 #define ARMV8_PMCR_LC           (1 << 6) /* Overflow on 64 bit cycle counter */
 410 #define ARMV8_PMCR_N_SHIFT      11       /* Number of counters supported */
 411 #define ARMV8_PMCR_N_MASK       0x1f
 412 #define ARMV8_PMCR_MASK         0x7f     /* Mask for writable bits */
 413
 414 /*
 415  * PMOVSR: counters overflow flag status reg
 416  */
 417 #define ARMV8_OVSR_MASK         0xffffffff      /* Mask for writable bits */
 418 #define ARMV8_OVERFLOWED_MASK   ARMV8_OVSR_MASK
 419
 420 /*
 421  * PMXEVTYPER: Event selection reg
 422  */
 423 #define ARMV8_EVTYPE_MASK       0xc800ffff      /* Mask for writable bits */
 424 #define ARMV8_EVTYPE_EVENT      0xffff          /* Mask for EVENT bits */
 425
 426 /*
 427  * Event filters for PMUv3
 428  */
 429 #define ARMV8_EXCLUDE_EL1       (1 << 31)
 430 #define ARMV8_EXCLUDE_EL0       (1 << 30)
 431 #define ARMV8_INCLUDE_EL2       (1 << 27)
 432
 433 static inline u32 armv8pmu_pmcr_read(void)
 434 {
 435         u32 val;
 436         asm volatile("mrs %0, pmcr_el0" : "=r" (val));
 437         return val;
 438 }
 439
 440 static inline void armv8pmu_pmcr_write(u32 val)
 441 {
 442         val &= ARMV8_PMCR_MASK;
 443         isb();
 444         asm volatile("msr pmcr_el0, %0" :: "r" (val));
 445 }
 446
 447 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 448 {
 449         return pmovsr & ARMV8_OVERFLOWED_MASK;
 450 }
 451
 452 static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
 453 {
 454         return idx >= ARMV8_IDX_CYCLE_COUNTER &&
 455                 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
 456 }
 457
 458 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 459 {
 460         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 461 }
 462
 463 static inline int armv8pmu_select_counter(int idx)
 464 {
 465         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 466         asm volatile("msr pmselr_el0, %0" :: "r" (counter));
 467         isb();
 468
 469         return idx;
 470 }
 471
 472 static inline u32 armv8pmu_read_counter(struct perf_event *event)
 473 {
 474         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 475         struct hw_perf_event *hwc = &event->hw;
 476         int idx = hwc->idx;
 477         u32 value = 0;
 478
 479         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 480                 pr_err("CPU%u reading wrong counter %d\n",
 481                         smp_processor_id(), idx);
 482         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 483                 asm volatile("mrs %0, pmccntr_el0" : "=r" (value));
 484         else if (armv8pmu_select_counter(idx) == idx)
 485                 asm volatile("mrs %0, pmxevcntr_el0" : "=r" (value));
 486
 487         return value;
 488 }
 489
 490 static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
 491 {
 492         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 493         struct hw_perf_event *hwc = &event->hw;
 494         int idx = hwc->idx;
 495
 496         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 497                 pr_err("CPU%u writing wrong counter %d\n",
 498                         smp_processor_id(), idx);
 499         else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
 500                 /*
 501                  * Set the upper 32bits as this is a 64bit counter but we only
 502                  * count using the lower 32bits and we want an interrupt when
 503                  * it overflows.
 504                  */
 505                 u64 value64 = 0xffffffff00000000ULL | value;
 506
 507                 asm volatile("msr pmccntr_el0, %0" :: "r" (value64));
 508         } else if (armv8pmu_select_counter(idx) == idx)
 509                 asm volatile("msr pmxevcntr_el0, %0" :: "r" (value));
 510 }
 511
 512 static inline void armv8pmu_write_evtype(int idx, u32 val)
 513 {
 514         if (armv8pmu_select_counter(idx) == idx) {
 515                 val &= ARMV8_EVTYPE_MASK;
 516                 asm volatile("msr pmxevtyper_el0, %0" :: "r" (val));
 517         }
 518 }
 519
 520 static inline int armv8pmu_enable_counter(int idx)
 521 {
 522         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 523         asm volatile("msr pmcntenset_el0, %0" :: "r" (BIT(counter)));
 524         return idx;
 525 }
 526
 527 static inline int armv8pmu_disable_counter(int idx)
 528 {
 529         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 530         asm volatile("msr pmcntenclr_el0, %0" :: "r" (BIT(counter)));
 531         return idx;
 532 }
 533
 534 static inline int armv8pmu_enable_intens(int idx)
 535 {
 536         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 537         asm volatile("msr pmintenset_el1, %0" :: "r" (BIT(counter)));
 538         return idx;
 539 }
 540
 541 static inline int armv8pmu_disable_intens(int idx)
 542 {
 543         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 544         asm volatile("msr pmintenclr_el1, %0" :: "r" (BIT(counter)));
 545         isb();
 546         /* Clear the overflow flag in case an interrupt is pending. */
 547         asm volatile("msr pmovsclr_el0, %0" :: "r" (BIT(counter)));
 548         isb();
 549
 550         return idx;
 551 }
 552
 553 static inline u32 armv8pmu_getreset_flags(void)
 554 {
 555         u32 value;
 556
 557         /* Read */
 558         asm volatile("mrs %0, pmovsclr_el0" : "=r" (value));
 559
 560         /* Write to clear flags */
 561         value &= ARMV8_OVSR_MASK;
 562         asm volatile("msr pmovsclr_el0, %0" :: "r" (value));
 563
 564         return value;
 565 }
 566
 567 static void armv8pmu_enable_event(struct perf_event *event)
 568 {
 569         unsigned long flags;
 570         struct hw_perf_event *hwc = &event->hw;
 571         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 572         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 573         int idx = hwc->idx;
 574
 575         /*
 576          * Enable counter and interrupt, and set the counter to count
 577          * the event that we're interested in.
 578          */
 579         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 580
 581         /*
 582          * Disable counter
 583          */
 584         armv8pmu_disable_counter(idx);
 585
 586         /*
 587          * Set event (if destined for PMNx counters).
 588          */
 589         armv8pmu_write_evtype(idx, hwc->config_base);
 590
 591         /*
 592          * Enable interrupt for this counter
 593          */
 594         armv8pmu_enable_intens(idx);
 595
 596         /*
 597          * Enable counter
 598          */
 599         armv8pmu_enable_counter(idx);
 600
 601         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 602 }
 603
 604 static void armv8pmu_disable_event(struct perf_event *event)
 605 {
 606         unsigned long flags;
 607         struct hw_perf_event *hwc = &event->hw;
 608         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 609         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 610         int idx = hwc->idx;
 611
 612         /*
 613          * Disable counter and interrupt
 614          */
 615         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 616
 617         /*
 618          * Disable counter
 619          */
 620         armv8pmu_disable_counter(idx);
 621
 622         /*
 623          * Disable interrupt for this counter
 624          */
 625         armv8pmu_disable_intens(idx);
 626
 627         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 628 }
 629
 630 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
 631 {
 632         u32 pmovsr;
 633         struct perf_sample_data data;
 634         struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
 635         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 636         struct pt_regs *regs;
 637         int idx;
 638
 639         /*
 640          * Get and reset the IRQ flags
 641          */
 642         pmovsr = armv8pmu_getreset_flags();
 643
 644         /*
 645          * Did an overflow occur?
 646          */
 647         if (!armv8pmu_has_overflowed(pmovsr))
 648                 return IRQ_NONE;
 649
 650         /*
 651          * Handle the counter(s) overflow(s)
 652          */
 653         regs = get_irq_regs();
 654
 655         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 656                 struct perf_event *event = cpuc->events[idx];
 657                 struct hw_perf_event *hwc;
 658
 659                 /* Ignore if we don't have an event. */
 660                 if (!event)
 661                         continue;
 662
 663                 /*
 664                  * We have a single interrupt for all counters. Check that
 665                  * each counter has overflowed before we process it.
 666                  */
 667                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 668                         continue;
 669
 670                 hwc = &event->hw;
 671                 armpmu_event_update(event);
 672                 perf_sample_data_init(&data, 0, hwc->last_period);
 673                 if (!armpmu_event_set_period(event))
 674                         continue;
 675
 676                 if (perf_event_overflow(event, &data, regs))
 677                         cpu_pmu->disable(event);
 678         }
 679
 680         /*
 681          * Handle the pending perf events.
 682          *
 683          * Note: this call *must* be run with interrupts disabled. For
 684          * platforms that can have the PMU interrupts raised as an NMI, this
 685          * will not work.
 686          */
 687         irq_work_run();
 688
 689         return IRQ_HANDLED;
 690 }
 691
 692 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 693 {
 694         unsigned long flags;
 695         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 696
 697         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 698         /* Enable all counters */
 699         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMCR_E);
 700         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 701 }
 702
 703 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 704 {
 705         unsigned long flags;
 706         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 707
 708         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 709         /* Disable all counters */
 710         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMCR_E);
 711         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 712 }
 713
 714 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 715                                   struct perf_event *event)
 716 {
 717         int idx;
 718         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 719         struct hw_perf_event *hwc = &event->hw;
 720         unsigned long evtype = hwc->config_base & ARMV8_EVTYPE_EVENT;
 721
 722         /* Always place a cycle counter into the cycle counter. */
 723         if (evtype == ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES) {
 724                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 725                         return -EAGAIN;
 726
 727                 return ARMV8_IDX_CYCLE_COUNTER;
 728         }
 729
 730         /*
 731          * For anything other than a cycle counter, try and use
 732          * the events counters
 733          */
 734         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
 735                 if (!test_and_set_bit(idx, cpuc->used_mask))
 736                         return idx;
 737         }
 738
 739         /* The counters are all in use. */
 740         return -EAGAIN;
 741 }
 742
 743 /*
 744  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
 745  */
 746 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 747                                      struct perf_event_attr *attr)
 748 {
 749         unsigned long config_base = 0;
 750
 751         if (attr->exclude_idle)
 752                 return -EPERM;
 753         if (is_kernel_in_hyp_mode() &&
 754             attr->exclude_kernel != attr->exclude_hv)
 755                 return -EINVAL;
 756         if (attr->exclude_user)
 757                 config_base |= ARMV8_EXCLUDE_EL0;
 758         if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
 759                 config_base |= ARMV8_EXCLUDE_EL1;
 760         if (!attr->exclude_hv)
 761                 config_base |= ARMV8_INCLUDE_EL2;
 762
 763         /*
 764          * Install the filter into config_base as this is used to
 765          * construct the event type.
 766          */
 767         event->config_base = config_base;
 768
 769         return 0;
 770 }
 771
 772 static void armv8pmu_reset(void *info)
 773 {
 774         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 775         u32 idx, nb_cnt = cpu_pmu->num_events;
 776
 777         /* The counter and interrupt enable registers are unknown at reset. */
 778         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
 779                 armv8pmu_disable_counter(idx);
 780                 armv8pmu_disable_intens(idx);
 781         }
 782
 783         /*
 784          * Initialize & Reset PMNC. Request overflow interrupt for
 785          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 786          */
 787         armv8pmu_pmcr_write(ARMV8_PMCR_P | ARMV8_PMCR_C | ARMV8_PMCR_LC);
 788 }
 789
 790 static int armv8_pmuv3_map_event(struct perf_event *event)
 791 {
 792         return armpmu_map_event(event, &armv8_pmuv3_perf_map,
 793                                 &armv8_pmuv3_perf_cache_map,
 794                                 ARMV8_EVTYPE_EVENT);
 795 }
 796
 797 static int armv8_a53_map_event(struct perf_event *event)
 798 {
 799         return armpmu_map_event(event, &armv8_a53_perf_map,
 800                                 &armv8_a53_perf_cache_map,
 801                                 ARMV8_EVTYPE_EVENT);
 802 }
 803
 804 static int armv8_a57_map_event(struct perf_event *event)
 805 {
 806         return armpmu_map_event(event, &armv8_a57_perf_map,
 807                                 &armv8_a57_perf_cache_map,
 808                                 ARMV8_EVTYPE_EVENT);
 809 }
 810
 811 static int armv8_thunder_map_event(struct perf_event *event)
 812 {
 813         return armpmu_map_event(event, &armv8_thunder_perf_map,
 814                                 &armv8_thunder_perf_cache_map,
 815                                 ARMV8_EVTYPE_EVENT);
 816 }
 817
 818 static void armv8pmu_read_num_pmnc_events(void *info)
 819 {
 820         int *nb_cnt = info;
 821
 822         /* Read the nb of CNTx counters supported from PMNC */
 823         *nb_cnt = (armv8pmu_pmcr_read() >> ARMV8_PMCR_N_SHIFT) & ARMV8_PMCR_N_MASK;
 824
 825         /* Add the CPU cycles counter */
 826         *nb_cnt += 1;
 827 }
 828
 829 static int armv8pmu_probe_num_events(struct arm_pmu *arm_pmu)
 830 {
 831         return smp_call_function_any(&arm_pmu->supported_cpus,
 832                                     armv8pmu_read_num_pmnc_events,
 833                                     &arm_pmu->num_events, 1);
 834 }
 835
 836 static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
 837 {
 838         cpu_pmu->handle_irq             = armv8pmu_handle_irq,
 839         cpu_pmu->enable                 = armv8pmu_enable_event,
 840         cpu_pmu->disable                = armv8pmu_disable_event,
 841         cpu_pmu->read_counter           = armv8pmu_read_counter,
 842         cpu_pmu->write_counter          = armv8pmu_write_counter,
 843         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx,
 844         cpu_pmu->start                  = armv8pmu_start,
 845         cpu_pmu->stop                   = armv8pmu_stop,
 846         cpu_pmu->reset                  = armv8pmu_reset,
 847         cpu_pmu->max_period             = (1LLU << 32) - 1,
 848         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
 849 }
 850
 851 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
 852 {
 853         armv8_pmu_init(cpu_pmu);
 854         cpu_pmu->name                   = "armv8_pmuv3";
 855         cpu_pmu->map_event              = armv8_pmuv3_map_event;
 856         return armv8pmu_probe_num_events(cpu_pmu);
 857 }
 858
 859 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
 860 {
 861         armv8_pmu_init(cpu_pmu);
 862         cpu_pmu->name                   = "armv8_cortex_a53";
 863         cpu_pmu->map_event              = armv8_a53_map_event;
 864         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 865         return armv8pmu_probe_num_events(cpu_pmu);
 866 }
 867
 868 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
 869 {
 870         armv8_pmu_init(cpu_pmu);
 871         cpu_pmu->name                   = "armv8_cortex_a57";
 872         cpu_pmu->map_event              = armv8_a57_map_event;
 873         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 874         return armv8pmu_probe_num_events(cpu_pmu);
 875 }
 876
 877 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
 878 {
 879         armv8_pmu_init(cpu_pmu);
 880         cpu_pmu->name                   = "armv8_cortex_a72";
 881         cpu_pmu->map_event              = armv8_a57_map_event;
 882         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 883         return armv8pmu_probe_num_events(cpu_pmu);
 884 }
 885
 886 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
 887 {
 888         armv8_pmu_init(cpu_pmu);
 889         cpu_pmu->name                   = "armv8_cavium_thunder";
 890         cpu_pmu->map_event              = armv8_thunder_map_event;
 891         cpu_pmu->pmu.attr_groups        = armv8_pmuv3_attr_groups;
 892         return armv8pmu_probe_num_events(cpu_pmu);
 893 }
 894
 895 static const struct of_device_id armv8_pmu_of_device_ids[] = {
 896         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
 897         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
 898         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
 899         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
 900         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
 901         {},
 902 };
 903
 904 static int armv8_pmu_device_probe(struct platform_device *pdev)
 905 {
 906         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
 907 }
 908
 909 static struct platform_driver armv8_pmu_driver = {
 910         .driver         = {
 911                 .name   = "armv8-pmu",
 912                 .of_match_table = armv8_pmu_of_device_ids,
 913         },
 914         .probe          = armv8_pmu_device_probe,
 915 };
 916
 917 static int __init register_armv8_pmu_driver(void)
 918 {
 919         return platform_driver_register(&armv8_pmu_driver);
 920 }
 921 device_initcall(register_armv8_pmu_driver);