arch/arm64/kernel/perf_event.c

   1 /*
   2  * PMU support
   3  *
   4  * Copyright (C) 2012 ARM Limited
   5  * Author: Will Deacon <will.deacon@arm.com>
   6  *
   7  * This code is based heavily on the ARMv7 perf event code.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <asm/irq_regs.h>
  23 #include <asm/perf_event.h>
  24 #include <asm/sysreg.h>
  25 #include <asm/virt.h>
  26
  27 #include <linux/acpi.h>
  28 #include <linux/of.h>
  29 #include <linux/perf/arm_pmu.h>
  30 #include <linux/platform_device.h>
  31
  32 /*
  33  * ARMv8 PMUv3 Performance Events handling code.
  34  * Common event types (some are defined in asm/perf_event.h).
  35  */
  36
  37 /* At least one of the following is required. */
  38 #define ARMV8_PMUV3_PERFCTR_INST_RETIRED                        0x08
  39 #define ARMV8_PMUV3_PERFCTR_INST_SPEC                           0x1B
  40
  41 /* Common architectural events. */
  42 #define ARMV8_PMUV3_PERFCTR_LD_RETIRED                          0x06
  43 #define ARMV8_PMUV3_PERFCTR_ST_RETIRED                          0x07
  44 #define ARMV8_PMUV3_PERFCTR_EXC_TAKEN                           0x09
  45 #define ARMV8_PMUV3_PERFCTR_EXC_RETURN                          0x0A
  46 #define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED                   0x0B
  47 #define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED                    0x0C
  48 #define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED                    0x0D
  49 #define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED                   0x0E
  50 #define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED              0x0F
  51 #define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED                  0x1C
  52 #define ARMV8_PMUV3_PERFCTR_CHAIN                               0x1E
  53 #define ARMV8_PMUV3_PERFCTR_BR_RETIRED                          0x21
  54
  55 /* Common microarchitectural events. */
  56 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL                    0x01
  57 #define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL                      0x02
  58 #define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL                      0x05
  59 #define ARMV8_PMUV3_PERFCTR_MEM_ACCESS                          0x13
  60 #define ARMV8_PMUV3_PERFCTR_L1I_CACHE                           0x14
  61 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB                        0x15
  62 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE                           0x16
  63 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL                    0x17
  64 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB                        0x18
  65 #define ARMV8_PMUV3_PERFCTR_BUS_ACCESS                          0x19
  66 #define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR                        0x1A
  67 #define ARMV8_PMUV3_PERFCTR_BUS_CYCLES                          0x1D
  68 #define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE                  0x1F
  69 #define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE                  0x20
  70 #define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED                 0x22
  71 #define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND                      0x23
  72 #define ARMV8_PMUV3_PERFCTR_STALL_BACKEND                       0x24
  73 #define ARMV8_PMUV3_PERFCTR_L1D_TLB                             0x25
  74 #define ARMV8_PMUV3_PERFCTR_L1I_TLB                             0x26
  75 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE                           0x27
  76 #define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL                    0x28
  77 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE                  0x29
  78 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL                    0x2A
  79 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE                           0x2B
  80 #define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB                        0x2C
  81 #define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL                      0x2D
  82 #define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL                      0x2E
  83 #define ARMV8_PMUV3_PERFCTR_L2D_TLB                             0x2F
  84 #define ARMV8_PMUV3_PERFCTR_L2I_TLB                             0x30
  85
  86 /* ARMv8 recommended implementation defined event types */
  87 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD                       0x40
  88 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR                       0x41
  89 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD                0x42
  90 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR                0x43
  91 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER             0x44
  92 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER             0x45
  93 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM                0x46
  94 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN                 0x47
  95 #define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL                    0x48
  96
  97 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD                  0x4C
  98 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR                  0x4D
  99 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD                         0x4E
 100 #define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR                         0x4F
 101 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD                       0x50
 102 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR                       0x51
 103 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD                0x52
 104 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR                0x53
 105
 106 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM                0x56
 107 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN                 0x57
 108 #define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL                    0x58
 109
 110 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD                  0x5C
 111 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR                  0x5D
 112 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD                         0x5E
 113 #define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR                         0x5F
 114
 115 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD                      0x60
 116 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR                      0x61
 117 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED                  0x62
 118 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED              0x63
 119 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL                  0x64
 120 #define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH                  0x65
 121
 122 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD                      0x66
 123 #define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR                      0x67
 124 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC                  0x68
 125 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC                  0x69
 126 #define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC                0x6A
 127
 128 #define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC                         0x6C
 129 #define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC                    0x6D
 130 #define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC                    0x6E
 131 #define ARMV8_IMPDEF_PERFCTR_STREX_SPEC                         0x6F
 132 #define ARMV8_IMPDEF_PERFCTR_LD_SPEC                            0x70
 133 #define ARMV8_IMPDEF_PERFCTR_ST_SPEC                            0x71
 134 #define ARMV8_IMPDEF_PERFCTR_LDST_SPEC                          0x72
 135 #define ARMV8_IMPDEF_PERFCTR_DP_SPEC                            0x73
 136 #define ARMV8_IMPDEF_PERFCTR_ASE_SPEC                           0x74
 137 #define ARMV8_IMPDEF_PERFCTR_VFP_SPEC                           0x75
 138 #define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC                      0x76
 139 #define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC                        0x77
 140 #define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC                      0x78
 141 #define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC                     0x79
 142 #define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC                   0x7A
 143
 144 #define ARMV8_IMPDEF_PERFCTR_ISB_SPEC                           0x7C
 145 #define ARMV8_IMPDEF_PERFCTR_DSB_SPEC                           0x7D
 146 #define ARMV8_IMPDEF_PERFCTR_DMB_SPEC                           0x7E
 147
 148 #define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF                          0x81
 149 #define ARMV8_IMPDEF_PERFCTR_EXC_SVC                            0x82
 150 #define ARMV8_IMPDEF_PERFCTR_EXC_PABORT                         0x83
 151 #define ARMV8_IMPDEF_PERFCTR_EXC_DABORT                         0x84
 152
 153 #define ARMV8_IMPDEF_PERFCTR_EXC_IRQ                            0x86
 154 #define ARMV8_IMPDEF_PERFCTR_EXC_FIQ                            0x87
 155 #define ARMV8_IMPDEF_PERFCTR_EXC_SMC                            0x88
 156
 157 #define ARMV8_IMPDEF_PERFCTR_EXC_HVC                            0x8A
 158 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT                    0x8B
 159 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT                    0x8C
 160 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER                     0x8D
 161 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ                       0x8E
 162 #define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ                       0x8F
 163 #define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC                         0x90
 164 #define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC                         0x91
 165
 166 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD                       0xA0
 167 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR                       0xA1
 168 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD                0xA2
 169 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR                0xA3
 170
 171 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM                0xA6
 172 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN                 0xA7
 173 #define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL                    0xA8
 174
 175 /* ARMv8 Cortex-A53 specific event types. */
 176 #define ARMV8_A53_PERFCTR_PREF_LINEFILL                         0xC2
 177
 178 /* ARMv8 Cavium ThunderX specific event types. */
 179 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST                 0xE9
 180 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS             0xEA
 181 #define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS               0xEB
 182 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS             0xEC
 183 #define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS               0xED
 184
 185 /* PMUv3 HW events mapping. */
 186
 187 /*
 188  * ARMv8 Architectural defined events, not all of these may
 189  * be supported on any given implementation. Undefined events will
 190  * be disabled at run-time.
 191  */
 192 static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
 193         PERF_MAP_ALL_UNSUPPORTED,
 194         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 195         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 196         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 197         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 198         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 199         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 200         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 201         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 202         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 203 };
 204
 205 /* ARM Cortex-A53 HW events mapping. */
 206 static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = {
 207         PERF_MAP_ALL_UNSUPPORTED,
 208         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 209         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 210         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 211         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 212         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 213         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 214         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 215 };
 216
 217 /* ARM Cortex-A57 and Cortex-A72 events mapping. */
 218 static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = {
 219         PERF_MAP_ALL_UNSUPPORTED,
 220         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 221         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 222         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 223         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 224         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 225         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 226 };
 227
 228 static const unsigned armv8_thunder_perf_map[PERF_COUNT_HW_MAX] = {
 229         PERF_MAP_ALL_UNSUPPORTED,
 230         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 231         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 232         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 233         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 234         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
 235         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 236         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 237         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 238 };
 239
 240 /* Broadcom Vulcan events mapping */
 241 static const unsigned armv8_vulcan_perf_map[PERF_COUNT_HW_MAX] = {
 242         PERF_MAP_ALL_UNSUPPORTED,
 243         [PERF_COUNT_HW_CPU_CYCLES]              = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
 244         [PERF_COUNT_HW_INSTRUCTIONS]            = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
 245         [PERF_COUNT_HW_CACHE_REFERENCES]        = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 246         [PERF_COUNT_HW_CACHE_MISSES]            = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 247         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]     = ARMV8_PMUV3_PERFCTR_BR_RETIRED,
 248         [PERF_COUNT_HW_BRANCH_MISSES]           = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 249         [PERF_COUNT_HW_BUS_CYCLES]              = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
 250         [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
 251         [PERF_COUNT_HW_STALLED_CYCLES_BACKEND]  = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
 252 };
 253
 254 static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 255                                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 256                                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 257         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 258
 259         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 260         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 261         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 262         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 263
 264         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 265         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 266
 267         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
 268         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
 269
 270         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 271         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
 272
 273         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 274         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 275         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 276         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 277 };
 278
 279 static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 280                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 281                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 282         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 283
 284         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 285         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 286         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
 287         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
 288         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
 289
 290         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 291         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 292
 293         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 294
 295         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 296         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 297         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 298         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 299 };
 300
 301 static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 302                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 303                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 304         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 305
 306         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 307         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 308         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 309         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 310
 311         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 312         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 313
 314         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 315         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 316
 317         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 318
 319         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 320         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 321         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 322         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 323 };
 324
 325 static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 326                                                    [PERF_COUNT_HW_CACHE_OP_MAX]
 327                                                    [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 328         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 329
 330         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 331         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 332         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 333         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
 334         [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
 335         [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
 336
 337         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 338         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 339         [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
 340         [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
 341
 342         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 343         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 344         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 345         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 346
 347         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 348
 349         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 350         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 351         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 352         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 353 };
 354
 355 static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 356                                               [PERF_COUNT_HW_CACHE_OP_MAX]
 357                                               [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
 358         PERF_CACHE_MAP_ALL_UNSUPPORTED,
 359
 360         [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
 361         [C(L1D)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
 362         [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
 363         [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
 364
 365         [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
 366         [C(L1I)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
 367
 368         [C(ITLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
 369         [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
 370
 371         [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
 372         [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
 373         [C(DTLB)][C(OP_READ)][C(RESULT_MISS)]   = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
 374         [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)]  = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
 375
 376         [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)]  = ARMV8_PMUV3_PERFCTR_BR_PRED,
 377         [C(BPU)][C(OP_READ)][C(RESULT_MISS)]    = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 378         [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
 379         [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)]   = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
 380
 381         [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
 382         [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
 383 };
 384
 385 static ssize_t
 386 armv8pmu_events_sysfs_show(struct device *dev,
 387                            struct device_attribute *attr, char *page)
 388 {
 389         struct perf_pmu_events_attr *pmu_attr;
 390
 391         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
 392
 393         return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
 394 }
 395
 396 #define ARMV8_EVENT_ATTR_RESOLVE(m) #m
 397 #define ARMV8_EVENT_ATTR(name, config) \
 398         PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
 399                        config, armv8pmu_events_sysfs_show)
 400
 401 ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
 402 ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
 403 ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
 404 ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
 405 ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
 406 ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
 407 ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
 408 ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
 409 ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
 410 ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
 411 ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
 412 ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
 413 ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
 414 ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
 415 ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
 416 ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
 417 ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
 418 ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
 419 ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
 420 ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
 421 ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
 422 ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
 423 ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
 424 ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
 425 ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
 426 ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
 427 ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
 428 ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
 429 ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
 430 ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
 431 /* Don't expose the chain event in /sys, since it's useless in isolation */
 432 ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
 433 ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
 434 ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
 435 ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
 436 ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
 437 ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
 438 ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
 439 ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
 440 ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
 441 ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
 442 ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
 443 ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
 444 ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
 445 ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
 446 ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
 447 ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
 448 ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
 449 ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
 450
 451 static struct attribute *armv8_pmuv3_event_attrs[] = {
 452         &armv8_event_attr_sw_incr.attr.attr,
 453         &armv8_event_attr_l1i_cache_refill.attr.attr,
 454         &armv8_event_attr_l1i_tlb_refill.attr.attr,
 455         &armv8_event_attr_l1d_cache_refill.attr.attr,
 456         &armv8_event_attr_l1d_cache.attr.attr,
 457         &armv8_event_attr_l1d_tlb_refill.attr.attr,
 458         &armv8_event_attr_ld_retired.attr.attr,
 459         &armv8_event_attr_st_retired.attr.attr,
 460         &armv8_event_attr_inst_retired.attr.attr,
 461         &armv8_event_attr_exc_taken.attr.attr,
 462         &armv8_event_attr_exc_return.attr.attr,
 463         &armv8_event_attr_cid_write_retired.attr.attr,
 464         &armv8_event_attr_pc_write_retired.attr.attr,
 465         &armv8_event_attr_br_immed_retired.attr.attr,
 466         &armv8_event_attr_br_return_retired.attr.attr,
 467         &armv8_event_attr_unaligned_ldst_retired.attr.attr,
 468         &armv8_event_attr_br_mis_pred.attr.attr,
 469         &armv8_event_attr_cpu_cycles.attr.attr,
 470         &armv8_event_attr_br_pred.attr.attr,
 471         &armv8_event_attr_mem_access.attr.attr,
 472         &armv8_event_attr_l1i_cache.attr.attr,
 473         &armv8_event_attr_l1d_cache_wb.attr.attr,
 474         &armv8_event_attr_l2d_cache.attr.attr,
 475         &armv8_event_attr_l2d_cache_refill.attr.attr,
 476         &armv8_event_attr_l2d_cache_wb.attr.attr,
 477         &armv8_event_attr_bus_access.attr.attr,
 478         &armv8_event_attr_memory_error.attr.attr,
 479         &armv8_event_attr_inst_spec.attr.attr,
 480         &armv8_event_attr_ttbr_write_retired.attr.attr,
 481         &armv8_event_attr_bus_cycles.attr.attr,
 482         &armv8_event_attr_l1d_cache_allocate.attr.attr,
 483         &armv8_event_attr_l2d_cache_allocate.attr.attr,
 484         &armv8_event_attr_br_retired.attr.attr,
 485         &armv8_event_attr_br_mis_pred_retired.attr.attr,
 486         &armv8_event_attr_stall_frontend.attr.attr,
 487         &armv8_event_attr_stall_backend.attr.attr,
 488         &armv8_event_attr_l1d_tlb.attr.attr,
 489         &armv8_event_attr_l1i_tlb.attr.attr,
 490         &armv8_event_attr_l2i_cache.attr.attr,
 491         &armv8_event_attr_l2i_cache_refill.attr.attr,
 492         &armv8_event_attr_l3d_cache_allocate.attr.attr,
 493         &armv8_event_attr_l3d_cache_refill.attr.attr,
 494         &armv8_event_attr_l3d_cache.attr.attr,
 495         &armv8_event_attr_l3d_cache_wb.attr.attr,
 496         &armv8_event_attr_l2d_tlb_refill.attr.attr,
 497         &armv8_event_attr_l2i_tlb_refill.attr.attr,
 498         &armv8_event_attr_l2d_tlb.attr.attr,
 499         &armv8_event_attr_l2i_tlb.attr.attr,
 500         NULL,
 501 };
 502
 503 static umode_t
 504 armv8pmu_event_attr_is_visible(struct kobject *kobj,
 505                                struct attribute *attr, int unused)
 506 {
 507         struct device *dev = kobj_to_dev(kobj);
 508         struct pmu *pmu = dev_get_drvdata(dev);
 509         struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
 510         struct perf_pmu_events_attr *pmu_attr;
 511
 512         pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
 513
 514         if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
 515                 return attr->mode;
 516
 517         return 0;
 518 }
 519
 520 static struct attribute_group armv8_pmuv3_events_attr_group = {
 521         .name = "events",
 522         .attrs = armv8_pmuv3_event_attrs,
 523         .is_visible = armv8pmu_event_attr_is_visible,
 524 };
 525
 526 PMU_FORMAT_ATTR(event, "config:0-9");
 527
 528 static struct attribute *armv8_pmuv3_format_attrs[] = {
 529         &format_attr_event.attr,
 530         NULL,
 531 };
 532
 533 static struct attribute_group armv8_pmuv3_format_attr_group = {
 534         .name = "format",
 535         .attrs = armv8_pmuv3_format_attrs,
 536 };
 537
 538 /*
 539  * Perf Events' indices
 540  */
 541 #define ARMV8_IDX_CYCLE_COUNTER 0
 542 #define ARMV8_IDX_COUNTER0      1
 543 #define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
 544         (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
 545
 546 /*
 547  * ARMv8 low level PMU access
 548  */
 549
 550 /*
 551  * Perf Event to low level counters mapping
 552  */
 553 #define ARMV8_IDX_TO_COUNTER(x) \
 554         (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
 555
 556 static inline u32 armv8pmu_pmcr_read(void)
 557 {
 558         return read_sysreg(pmcr_el0);
 559 }
 560
 561 static inline void armv8pmu_pmcr_write(u32 val)
 562 {
 563         val &= ARMV8_PMU_PMCR_MASK;
 564         isb();
 565         write_sysreg(val, pmcr_el0);
 566 }
 567
 568 static inline int armv8pmu_has_overflowed(u32 pmovsr)
 569 {
 570         return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
 571 }
 572
 573 static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
 574 {
 575         return idx >= ARMV8_IDX_CYCLE_COUNTER &&
 576                 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
 577 }
 578
 579 static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
 580 {
 581         return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
 582 }
 583
 584 static inline int armv8pmu_select_counter(int idx)
 585 {
 586         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 587         write_sysreg(counter, pmselr_el0);
 588         isb();
 589
 590         return idx;
 591 }
 592
 593 static inline u32 armv8pmu_read_counter(struct perf_event *event)
 594 {
 595         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 596         struct hw_perf_event *hwc = &event->hw;
 597         int idx = hwc->idx;
 598         u32 value = 0;
 599
 600         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 601                 pr_err("CPU%u reading wrong counter %d\n",
 602                         smp_processor_id(), idx);
 603         else if (idx == ARMV8_IDX_CYCLE_COUNTER)
 604                 value = read_sysreg(pmccntr_el0);
 605         else if (armv8pmu_select_counter(idx) == idx)
 606                 value = read_sysreg(pmxevcntr_el0);
 607
 608         return value;
 609 }
 610
 611 static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
 612 {
 613         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 614         struct hw_perf_event *hwc = &event->hw;
 615         int idx = hwc->idx;
 616
 617         if (!armv8pmu_counter_valid(cpu_pmu, idx))
 618                 pr_err("CPU%u writing wrong counter %d\n",
 619                         smp_processor_id(), idx);
 620         else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
 621                 /*
 622                  * Set the upper 32bits as this is a 64bit counter but we only
 623                  * count using the lower 32bits and we want an interrupt when
 624                  * it overflows.
 625                  */
 626                 u64 value64 = 0xffffffff00000000ULL | value;
 627
 628                 write_sysreg(value64, pmccntr_el0);
 629         } else if (armv8pmu_select_counter(idx) == idx)
 630                 write_sysreg(value, pmxevcntr_el0);
 631 }
 632
 633 static inline void armv8pmu_write_evtype(int idx, u32 val)
 634 {
 635         if (armv8pmu_select_counter(idx) == idx) {
 636                 val &= ARMV8_PMU_EVTYPE_MASK;
 637                 write_sysreg(val, pmxevtyper_el0);
 638         }
 639 }
 640
 641 static inline int armv8pmu_enable_counter(int idx)
 642 {
 643         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 644         write_sysreg(BIT(counter), pmcntenset_el0);
 645         return idx;
 646 }
 647
 648 static inline int armv8pmu_disable_counter(int idx)
 649 {
 650         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 651         write_sysreg(BIT(counter), pmcntenclr_el0);
 652         return idx;
 653 }
 654
 655 static inline int armv8pmu_enable_intens(int idx)
 656 {
 657         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 658         write_sysreg(BIT(counter), pmintenset_el1);
 659         return idx;
 660 }
 661
 662 static inline int armv8pmu_disable_intens(int idx)
 663 {
 664         u32 counter = ARMV8_IDX_TO_COUNTER(idx);
 665         write_sysreg(BIT(counter), pmintenclr_el1);
 666         isb();
 667         /* Clear the overflow flag in case an interrupt is pending. */
 668         write_sysreg(BIT(counter), pmovsclr_el0);
 669         isb();
 670
 671         return idx;
 672 }
 673
 674 static inline u32 armv8pmu_getreset_flags(void)
 675 {
 676         u32 value;
 677
 678         /* Read */
 679         value = read_sysreg(pmovsclr_el0);
 680
 681         /* Write to clear flags */
 682         value &= ARMV8_PMU_OVSR_MASK;
 683         write_sysreg(value, pmovsclr_el0);
 684
 685         return value;
 686 }
 687
 688 static void armv8pmu_enable_event(struct perf_event *event)
 689 {
 690         unsigned long flags;
 691         struct hw_perf_event *hwc = &event->hw;
 692         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 693         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 694         int idx = hwc->idx;
 695
 696         /*
 697          * Enable counter and interrupt, and set the counter to count
 698          * the event that we're interested in.
 699          */
 700         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 701
 702         /*
 703          * Disable counter
 704          */
 705         armv8pmu_disable_counter(idx);
 706
 707         /*
 708          * Set event (if destined for PMNx counters).
 709          */
 710         armv8pmu_write_evtype(idx, hwc->config_base);
 711
 712         /*
 713          * Enable interrupt for this counter
 714          */
 715         armv8pmu_enable_intens(idx);
 716
 717         /*
 718          * Enable counter
 719          */
 720         armv8pmu_enable_counter(idx);
 721
 722         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 723 }
 724
 725 static void armv8pmu_disable_event(struct perf_event *event)
 726 {
 727         unsigned long flags;
 728         struct hw_perf_event *hwc = &event->hw;
 729         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 730         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 731         int idx = hwc->idx;
 732
 733         /*
 734          * Disable counter and interrupt
 735          */
 736         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 737
 738         /*
 739          * Disable counter
 740          */
 741         armv8pmu_disable_counter(idx);
 742
 743         /*
 744          * Disable interrupt for this counter
 745          */
 746         armv8pmu_disable_intens(idx);
 747
 748         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 749 }
 750
 751 static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
 752 {
 753         u32 pmovsr;
 754         struct perf_sample_data data;
 755         struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
 756         struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
 757         struct pt_regs *regs;
 758         int idx;
 759
 760         /*
 761          * Get and reset the IRQ flags
 762          */
 763         pmovsr = armv8pmu_getreset_flags();
 764
 765         /*
 766          * Did an overflow occur?
 767          */
 768         if (!armv8pmu_has_overflowed(pmovsr))
 769                 return IRQ_NONE;
 770
 771         /*
 772          * Handle the counter(s) overflow(s)
 773          */
 774         regs = get_irq_regs();
 775
 776         for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
 777                 struct perf_event *event = cpuc->events[idx];
 778                 struct hw_perf_event *hwc;
 779
 780                 /* Ignore if we don't have an event. */
 781                 if (!event)
 782                         continue;
 783
 784                 /*
 785                  * We have a single interrupt for all counters. Check that
 786                  * each counter has overflowed before we process it.
 787                  */
 788                 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
 789                         continue;
 790
 791                 hwc = &event->hw;
 792                 armpmu_event_update(event);
 793                 perf_sample_data_init(&data, 0, hwc->last_period);
 794                 if (!armpmu_event_set_period(event))
 795                         continue;
 796
 797                 if (perf_event_overflow(event, &data, regs))
 798                         cpu_pmu->disable(event);
 799         }
 800
 801         /*
 802          * Handle the pending perf events.
 803          *
 804          * Note: this call *must* be run with interrupts disabled. For
 805          * platforms that can have the PMU interrupts raised as an NMI, this
 806          * will not work.
 807          */
 808         irq_work_run();
 809
 810         return IRQ_HANDLED;
 811 }
 812
 813 static void armv8pmu_start(struct arm_pmu *cpu_pmu)
 814 {
 815         unsigned long flags;
 816         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 817
 818         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 819         /* Enable all counters */
 820         armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
 821         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 822 }
 823
 824 static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
 825 {
 826         unsigned long flags;
 827         struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
 828
 829         raw_spin_lock_irqsave(&events->pmu_lock, flags);
 830         /* Disable all counters */
 831         armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
 832         raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
 833 }
 834
 835 static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
 836                                   struct perf_event *event)
 837 {
 838         int idx;
 839         struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
 840         struct hw_perf_event *hwc = &event->hw;
 841         unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
 842
 843         /* Always place a cycle counter into the cycle counter. */
 844         if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
 845                 if (test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
 846                         return -EAGAIN;
 847
 848                 return ARMV8_IDX_CYCLE_COUNTER;
 849         }
 850
 851         /*
 852          * For anything other than a cycle counter, try and use
 853          * the events counters
 854          */
 855         for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
 856                 if (!test_and_set_bit(idx, cpuc->used_mask))
 857                         return idx;
 858         }
 859
 860         /* The counters are all in use. */
 861         return -EAGAIN;
 862 }
 863
 864 /*
 865  * Add an event filter to a given event. This will only work for PMUv2 PMUs.
 866  */
 867 static int armv8pmu_set_event_filter(struct hw_perf_event *event,
 868                                      struct perf_event_attr *attr)
 869 {
 870         unsigned long config_base = 0;
 871
 872         if (attr->exclude_idle)
 873                 return -EPERM;
 874         if (is_kernel_in_hyp_mode() &&
 875             attr->exclude_kernel != attr->exclude_hv)
 876                 return -EINVAL;
 877         if (attr->exclude_user)
 878                 config_base |= ARMV8_PMU_EXCLUDE_EL0;
 879         if (!is_kernel_in_hyp_mode() && attr->exclude_kernel)
 880                 config_base |= ARMV8_PMU_EXCLUDE_EL1;
 881         if (!attr->exclude_hv)
 882                 config_base |= ARMV8_PMU_INCLUDE_EL2;
 883
 884         /*
 885          * Install the filter into config_base as this is used to
 886          * construct the event type.
 887          */
 888         event->config_base = config_base;
 889
 890         return 0;
 891 }
 892
 893 static void armv8pmu_reset(void *info)
 894 {
 895         struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
 896         u32 idx, nb_cnt = cpu_pmu->num_events;
 897
 898         /* The counter and interrupt enable registers are unknown at reset. */
 899         for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
 900                 armv8pmu_disable_counter(idx);
 901                 armv8pmu_disable_intens(idx);
 902         }
 903
 904         /*
 905          * Initialize & Reset PMNC. Request overflow interrupt for
 906          * 64 bit cycle counter but cheat in armv8pmu_write_counter().
 907          */
 908         armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
 909                             ARMV8_PMU_PMCR_LC);
 910 }
 911
 912 static int armv8_pmuv3_map_event(struct perf_event *event)
 913 {
 914         int hw_event_id;
 915         struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
 916
 917         hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
 918                                        &armv8_pmuv3_perf_cache_map,
 919                                        ARMV8_PMU_EVTYPE_EVENT);
 920         if (hw_event_id < 0)
 921                 return hw_event_id;
 922
 923         /* disable micro/arch events not supported by this PMU */
 924         if ((hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS) &&
 925                 !test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
 926                         return -EOPNOTSUPP;
 927         }
 928
 929         return hw_event_id;
 930 }
 931
 932 static int armv8_a53_map_event(struct perf_event *event)
 933 {
 934         return armpmu_map_event(event, &armv8_a53_perf_map,
 935                                 &armv8_a53_perf_cache_map,
 936                                 ARMV8_PMU_EVTYPE_EVENT);
 937 }
 938
 939 static int armv8_a57_map_event(struct perf_event *event)
 940 {
 941         return armpmu_map_event(event, &armv8_a57_perf_map,
 942                                 &armv8_a57_perf_cache_map,
 943                                 ARMV8_PMU_EVTYPE_EVENT);
 944 }
 945
 946 static int armv8_thunder_map_event(struct perf_event *event)
 947 {
 948         return armpmu_map_event(event, &armv8_thunder_perf_map,
 949                                 &armv8_thunder_perf_cache_map,
 950                                 ARMV8_PMU_EVTYPE_EVENT);
 951 }
 952
 953 static int armv8_vulcan_map_event(struct perf_event *event)
 954 {
 955         return armpmu_map_event(event, &armv8_vulcan_perf_map,
 956                                 &armv8_vulcan_perf_cache_map,
 957                                 ARMV8_PMU_EVTYPE_EVENT);
 958 }
 959
 960 static void __armv8pmu_probe_pmu(void *info)
 961 {
 962         struct arm_pmu *cpu_pmu = info;
 963         u32 pmceid[2];
 964
 965         /* Read the nb of CNTx counters supported from PMNC */
 966         cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
 967                 & ARMV8_PMU_PMCR_N_MASK;
 968
 969         /* Add the CPU cycles counter */
 970         cpu_pmu->num_events += 1;
 971
 972         pmceid[0] = read_sysreg(pmceid0_el0);
 973         pmceid[1] = read_sysreg(pmceid1_el0);
 974
 975         bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
 976                              ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
 977                              ARRAY_SIZE(pmceid));
 978 }
 979
 980 static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
 981 {
 982         return smp_call_function_any(&cpu_pmu->supported_cpus,
 983                                     __armv8pmu_probe_pmu,
 984                                     cpu_pmu, 1);
 985 }
 986
 987 static void armv8_pmu_init(struct arm_pmu *cpu_pmu)
 988 {
 989         cpu_pmu->handle_irq             = armv8pmu_handle_irq,
 990         cpu_pmu->enable                 = armv8pmu_enable_event,
 991         cpu_pmu->disable                = armv8pmu_disable_event,
 992         cpu_pmu->read_counter           = armv8pmu_read_counter,
 993         cpu_pmu->write_counter          = armv8pmu_write_counter,
 994         cpu_pmu->get_event_idx          = armv8pmu_get_event_idx,
 995         cpu_pmu->start                  = armv8pmu_start,
 996         cpu_pmu->stop                   = armv8pmu_stop,
 997         cpu_pmu->reset                  = armv8pmu_reset,
 998         cpu_pmu->max_period             = (1LLU << 32) - 1,
 999         cpu_pmu->set_event_filter       = armv8pmu_set_event_filter;
1000 }
1001
1002 static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
1003 {
1004         armv8_pmu_init(cpu_pmu);
1005         cpu_pmu->name                   = "armv8_pmuv3";
1006         cpu_pmu->map_event              = armv8_pmuv3_map_event;
1007         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1008                 &armv8_pmuv3_events_attr_group;
1009         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1010                 &armv8_pmuv3_format_attr_group;
1011         return armv8pmu_probe_pmu(cpu_pmu);
1012 }
1013
1014 static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1015 {
1016         armv8_pmu_init(cpu_pmu);
1017         cpu_pmu->name                   = "armv8_cortex_a53";
1018         cpu_pmu->map_event              = armv8_a53_map_event;
1019         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1020                 &armv8_pmuv3_events_attr_group;
1021         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1022                 &armv8_pmuv3_format_attr_group;
1023         return armv8pmu_probe_pmu(cpu_pmu);
1024 }
1025
1026 static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1027 {
1028         armv8_pmu_init(cpu_pmu);
1029         cpu_pmu->name                   = "armv8_cortex_a57";
1030         cpu_pmu->map_event              = armv8_a57_map_event;
1031         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1032                 &armv8_pmuv3_events_attr_group;
1033         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1034                 &armv8_pmuv3_format_attr_group;
1035         return armv8pmu_probe_pmu(cpu_pmu);
1036 }
1037
1038 static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1039 {
1040         armv8_pmu_init(cpu_pmu);
1041         cpu_pmu->name                   = "armv8_cortex_a72";
1042         cpu_pmu->map_event              = armv8_a57_map_event;
1043         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1044                 &armv8_pmuv3_events_attr_group;
1045         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1046                 &armv8_pmuv3_format_attr_group;
1047         return armv8pmu_probe_pmu(cpu_pmu);
1048 }
1049
1050 static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1051 {
1052         armv8_pmu_init(cpu_pmu);
1053         cpu_pmu->name                   = "armv8_cavium_thunder";
1054         cpu_pmu->map_event              = armv8_thunder_map_event;
1055         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1056                 &armv8_pmuv3_events_attr_group;
1057         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1058                 &armv8_pmuv3_format_attr_group;
1059         return armv8pmu_probe_pmu(cpu_pmu);
1060 }
1061
1062 static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1063 {
1064         armv8_pmu_init(cpu_pmu);
1065         cpu_pmu->name                   = "armv8_brcm_vulcan";
1066         cpu_pmu->map_event              = armv8_vulcan_map_event;
1067         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1068                 &armv8_pmuv3_events_attr_group;
1069         cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1070                 &armv8_pmuv3_format_attr_group;
1071         return armv8pmu_probe_pmu(cpu_pmu);
1072 }
1073
1074 static const struct of_device_id armv8_pmu_of_device_ids[] = {
1075         {.compatible = "arm,armv8-pmuv3",       .data = armv8_pmuv3_init},
1076         {.compatible = "arm,cortex-a53-pmu",    .data = armv8_a53_pmu_init},
1077         {.compatible = "arm,cortex-a57-pmu",    .data = armv8_a57_pmu_init},
1078         {.compatible = "arm,cortex-a72-pmu",    .data = armv8_a72_pmu_init},
1079         {.compatible = "cavium,thunder-pmu",    .data = armv8_thunder_pmu_init},
1080         {.compatible = "brcm,vulcan-pmu",       .data = armv8_vulcan_pmu_init},
1081         {},
1082 };
1083
1084 /*
1085  * Non DT systems have their micro/arch events probed at run-time.
1086  * A fairly complete list of generic events are provided and ones that
1087  * aren't supported by the current PMU are disabled.
1088  */
1089 static const struct pmu_probe_info armv8_pmu_probe_table[] = {
1090         PMU_PROBE(0, 0, armv8_pmuv3_init), /* enable all defined counters */
1091         { /* sentinel value */ }
1092 };
1093
1094 static int armv8_pmu_device_probe(struct platform_device *pdev)
1095 {
1096         if (acpi_disabled)
1097                 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids,
1098                                             NULL);
1099
1100         return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids,
1101                                     armv8_pmu_probe_table);
1102 }
1103
1104 static struct platform_driver armv8_pmu_driver = {
1105         .driver         = {
1106                 .name   = ARMV8_PMU_PDEV_NAME,
1107                 .of_match_table = armv8_pmu_of_device_ids,
1108         },
1109         .probe          = armv8_pmu_device_probe,
1110 };
1111
1112 builtin_platform_driver(armv8_pmu_driver);