2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
32 #include <asm/ptrace.h>
33 #include <asm/thread_info.h>
34 #include <asm/asm-uaccess.h>
35 #include <asm/unistd.h>
38 * Context tracking subsystem. Used to instrument transitions
39 * between user and kernel mode.
41 .macro ct_user_exit, syscall = 0
42 #ifdef CONFIG_CONTEXT_TRACKING
43 bl context_tracking_user_exit
46 * Save/restore needed during syscalls. Restore syscall arguments from
47 * the values already saved on stack during kernel_entry.
50 ldp x2, x3, [sp, #S_X2]
51 ldp x4, x5, [sp, #S_X4]
52 ldp x6, x7, [sp, #S_X6]
58 #ifdef CONFIG_CONTEXT_TRACKING
59 bl context_tracking_user_enter
72 .macro kernel_ventry label
74 sub sp, sp, #S_FRAME_SIZE
75 #ifdef CONFIG_VMAP_STACK
77 * Test whether the SP has overflowed, without corrupting a GPR.
78 * Task and IRQ stacks are aligned to (1 << THREAD_SHIFT).
80 add sp, sp, x0 // sp' = sp + x0
81 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
82 tbnz x0, #THREAD_SHIFT, 0f
83 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
84 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
89 * Either we've just detected an overflow, or we've taken an exception
90 * while on the overflow stack. Either way, we won't return to
91 * userspace, and can clobber EL0 registers to free up GPRs.
94 /* Stash the original SP (minus S_FRAME_SIZE) in tpidr_el0. */
97 /* Recover the original x0 value and stash it in tpidrro_el0 */
101 /* Switch to the overflow stack */
102 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
105 * Check whether we were already on the overflow stack. This may happen
106 * after panic() re-enables interrupts.
108 mrs x0, tpidr_el0 // sp of interrupted context
109 sub x0, sp, x0 // delta with top of overflow stack
110 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
111 b.ne __bad_stack // no? -> bad stack pointer
113 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
120 .macro kernel_entry, el, regsize = 64
122 mov w0, w0 // zero upper 32 bits of x0
124 stp x0, x1, [sp, #16 * 0]
125 stp x2, x3, [sp, #16 * 1]
126 stp x4, x5, [sp, #16 * 2]
127 stp x6, x7, [sp, #16 * 3]
128 stp x8, x9, [sp, #16 * 4]
129 stp x10, x11, [sp, #16 * 5]
130 stp x12, x13, [sp, #16 * 6]
131 stp x14, x15, [sp, #16 * 7]
132 stp x16, x17, [sp, #16 * 8]
133 stp x18, x19, [sp, #16 * 9]
134 stp x20, x21, [sp, #16 * 10]
135 stp x22, x23, [sp, #16 * 11]
136 stp x24, x25, [sp, #16 * 12]
137 stp x26, x27, [sp, #16 * 13]
138 stp x28, x29, [sp, #16 * 14]
142 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
143 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
144 disable_step_tsk x19, x20 // exceptions when scheduling.
146 mov x29, xzr // fp pointed to user-space
148 add x21, sp, #S_FRAME_SIZE
150 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
151 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
152 str x20, [sp, #S_ORIG_ADDR_LIMIT]
153 mov x20, #TASK_SIZE_64
154 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
155 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
156 .endif /* \el == 0 */
159 stp lr, x21, [sp, #S_LR]
162 * In order to be able to dump the contents of struct pt_regs at the
163 * time the exception was taken (in case we attempt to walk the call
164 * stack later), chain it together with the stack frames.
167 stp xzr, xzr, [sp, #S_STACKFRAME]
169 stp x29, x22, [sp, #S_STACKFRAME]
171 add x29, sp, #S_STACKFRAME
173 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
175 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
176 * EL0, there is no need to check the state of TTBR0_EL1 since
177 * accesses are always enabled.
178 * Note that the meaning of this bit differs from the ARMv8.1 PAN
179 * feature as all TTBR0_EL1 accesses are disabled, not just those to
182 alternative_if ARM64_HAS_PAN
183 b 1f // skip TTBR0 PAN
184 alternative_else_nop_endif
188 tst x21, #0xffff << 48 // Check for the reserved ASID
189 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
190 b.eq 1f // TTBR0 access already disabled
191 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
194 __uaccess_ttbr0_disable x21
198 stp x22, x23, [sp, #S_PC]
200 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
203 str w21, [sp, #S_SYSCALLNO]
207 * Set sp_el0 to current thread_info.
214 * Registers that may be useful after this macro is invoked:
218 * x23 - aborted PSTATE
222 .macro kernel_exit, el
224 /* Restore the task's original addr_limit. */
225 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
226 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
228 /* No need to restore UAO, it will be restored from SPSR_EL1 */
231 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
236 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
238 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
241 alternative_if ARM64_HAS_PAN
242 b 2f // skip TTBR0 PAN
243 alternative_else_nop_endif
246 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
249 __uaccess_ttbr0_enable x0
253 * Enable errata workarounds only if returning to user. The only
254 * workaround currently required for TTBR0_EL1 changes are for the
255 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
258 post_ttbr0_update_workaround
262 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
268 ldr x23, [sp, #S_SP] // load return stack pointer
270 #ifdef CONFIG_ARM64_ERRATUM_845719
271 alternative_if ARM64_WORKAROUND_845719
273 #ifdef CONFIG_PID_IN_CONTEXTIDR
274 mrs x29, contextidr_el1
275 msr contextidr_el1, x29
277 msr contextidr_el1, xzr
280 alternative_else_nop_endif
284 msr elr_el1, x21 // set up the return data
286 ldp x0, x1, [sp, #16 * 0]
287 ldp x2, x3, [sp, #16 * 1]
288 ldp x4, x5, [sp, #16 * 2]
289 ldp x6, x7, [sp, #16 * 3]
290 ldp x8, x9, [sp, #16 * 4]
291 ldp x10, x11, [sp, #16 * 5]
292 ldp x12, x13, [sp, #16 * 6]
293 ldp x14, x15, [sp, #16 * 7]
294 ldp x16, x17, [sp, #16 * 8]
295 ldp x18, x19, [sp, #16 * 9]
296 ldp x20, x21, [sp, #16 * 10]
297 ldp x22, x23, [sp, #16 * 11]
298 ldp x24, x25, [sp, #16 * 12]
299 ldp x26, x27, [sp, #16 * 13]
300 ldp x28, x29, [sp, #16 * 14]
302 add sp, sp, #S_FRAME_SIZE // restore sp
303 eret // return to kernel
306 .macro irq_stack_entry
307 mov x19, sp // preserve the original sp
310 * Compare sp with the base of the task stack.
311 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
312 * and should switch to the irq stack.
314 ldr x25, [tsk, TSK_STACK]
316 and x25, x25, #~(THREAD_SIZE - 1)
319 ldr_this_cpu x25, irq_stack_ptr, x26
320 mov x26, #IRQ_STACK_SIZE
323 /* switch to the irq stack */
329 * x19 should be preserved between irq_stack_entry and
332 .macro irq_stack_exit
337 * These are the registers used in the syscall handler, and allow us to
338 * have in theory up to 7 arguments to a function - x0 to x6.
340 * x7 is reserved for the system call number in 32-bit mode.
342 wsc_nr .req w25 // number of system calls
343 wscno .req w26 // syscall number
344 xscno .req x26 // syscall number (zero-extended)
345 stbl .req x27 // syscall table pointer
346 tsk .req x28 // current thread_info
349 * Interrupt handling.
352 ldr_l x1, handle_arch_irq
364 .pushsection ".entry.text", "ax"
368 kernel_ventry el1_sync_invalid // Synchronous EL1t
369 kernel_ventry el1_irq_invalid // IRQ EL1t
370 kernel_ventry el1_fiq_invalid // FIQ EL1t
371 kernel_ventry el1_error_invalid // Error EL1t
373 kernel_ventry el1_sync // Synchronous EL1h
374 kernel_ventry el1_irq // IRQ EL1h
375 kernel_ventry el1_fiq_invalid // FIQ EL1h
376 kernel_ventry el1_error_invalid // Error EL1h
378 kernel_ventry el0_sync // Synchronous 64-bit EL0
379 kernel_ventry el0_irq // IRQ 64-bit EL0
380 kernel_ventry el0_fiq_invalid // FIQ 64-bit EL0
381 kernel_ventry el0_error_invalid // Error 64-bit EL0
384 kernel_ventry el0_sync_compat // Synchronous 32-bit EL0
385 kernel_ventry el0_irq_compat // IRQ 32-bit EL0
386 kernel_ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
387 kernel_ventry el0_error_invalid_compat // Error 32-bit EL0
389 kernel_ventry el0_sync_invalid // Synchronous 32-bit EL0
390 kernel_ventry el0_irq_invalid // IRQ 32-bit EL0
391 kernel_ventry el0_fiq_invalid // FIQ 32-bit EL0
392 kernel_ventry el0_error_invalid // Error 32-bit EL0
396 #ifdef CONFIG_VMAP_STACK
398 * We detected an overflow in kernel_ventry, which switched to the
399 * overflow stack. Stash the exception regs, and head to our overflow
403 /* Restore the original x0 value */
407 * Store the original GPRs to the new stack. The orginal SP (minus
408 * S_FRAME_SIZE) was stashed in tpidr_el0 by kernel_ventry.
410 sub sp, sp, #S_FRAME_SIZE
413 add x0, x0, #S_FRAME_SIZE
416 /* Stash the regs for handle_bad_stack */
422 #endif /* CONFIG_VMAP_STACK */
425 * Invalid mode handlers
427 .macro inv_entry, el, reason, regsize = 64
428 kernel_entry \el, \regsize
437 inv_entry 0, BAD_SYNC
438 ENDPROC(el0_sync_invalid)
442 ENDPROC(el0_irq_invalid)
446 ENDPROC(el0_fiq_invalid)
449 inv_entry 0, BAD_ERROR
450 ENDPROC(el0_error_invalid)
453 el0_fiq_invalid_compat:
454 inv_entry 0, BAD_FIQ, 32
455 ENDPROC(el0_fiq_invalid_compat)
457 el0_error_invalid_compat:
458 inv_entry 0, BAD_ERROR, 32
459 ENDPROC(el0_error_invalid_compat)
463 inv_entry 1, BAD_SYNC
464 ENDPROC(el1_sync_invalid)
468 ENDPROC(el1_irq_invalid)
472 ENDPROC(el1_fiq_invalid)
475 inv_entry 1, BAD_ERROR
476 ENDPROC(el1_error_invalid)
484 mrs x1, esr_el1 // read the syndrome register
485 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
486 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
488 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
490 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
492 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
494 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
496 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
498 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
504 * Fall through to the Data abort case
508 * Data abort handling
512 // re-enable interrupts if they were enabled in the aborted context
513 tbnz x23, #7, 1f // PSR_I_BIT
516 clear_address_tag x0, x3
517 mov x2, sp // struct pt_regs
520 // disable interrupts before pulling preserved data off the stack
525 * Stack or PC alignment exception handling
534 * Undefined instruction
542 * Debug exception handling
544 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
545 cinc x24, x24, eq // set bit '0'
546 tbz x24, #0, el1_inv // EL1 only
548 mov x2, sp // struct pt_regs
549 bl do_debug_exception
552 // TODO: add support for undefined instructions in kernel mode
565 #ifdef CONFIG_TRACE_IRQFLAGS
566 bl trace_hardirqs_off
571 #ifdef CONFIG_PREEMPT
572 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
573 cbnz w24, 1f // preempt count != 0
574 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
575 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
579 #ifdef CONFIG_TRACE_IRQFLAGS
585 #ifdef CONFIG_PREEMPT
588 1: bl preempt_schedule_irq // irq en/disable is done inside
589 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
590 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
600 mrs x25, esr_el1 // read the syndrome register
601 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
602 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
604 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
606 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
608 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
610 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
612 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
614 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
616 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
618 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
620 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
628 mrs x25, esr_el1 // read the syndrome register
629 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
630 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
632 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
634 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
636 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
638 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
640 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
642 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
644 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
646 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
648 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
650 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
652 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
654 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
659 * AArch32 syscall handling
661 adrp stbl, compat_sys_call_table // load compat syscall table pointer
662 mov wscno, w7 // syscall number in w7 (r7)
663 mov wsc_nr, #__NR_compat_syscalls
674 * Data abort handling
677 // enable interrupts before calling the main handler
680 clear_address_tag x0, x26
687 * Instruction abort handling
690 // enable interrupts before calling the main handler
700 * Floating Point or Advanced SIMD access
710 * Floating Point or Advanced SIMD exception
720 * Stack or PC alignment exception handling
723 // enable interrupts before calling the main handler
733 * Undefined instruction
735 // enable interrupts before calling the main handler
743 * System instructions, for trapped cache maintenance instructions
753 * Debug exception handling
755 tbnz x24, #0, el0_inv // EL0 only
759 bl do_debug_exception
778 #ifdef CONFIG_TRACE_IRQFLAGS
779 bl trace_hardirqs_off
785 #ifdef CONFIG_TRACE_IRQFLAGS
792 * This is the fast syscall return path. We do as little as possible here,
793 * and this includes saving x0 back into the kernel stack.
796 disable_irq // disable interrupts
797 str x0, [sp, #S_X0] // returned x0
798 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
799 and x2, x1, #_TIF_SYSCALL_WORK
800 cbnz x2, ret_fast_syscall_trace
801 and x2, x1, #_TIF_WORK_MASK
802 cbnz x2, work_pending
803 enable_step_tsk x1, x2
805 ret_fast_syscall_trace:
806 enable_irq // enable interrupts
807 b __sys_trace_return_skipped // we already saved x0
810 * Ok, we need to do extra processing, enter the slow path.
815 #ifdef CONFIG_TRACE_IRQFLAGS
816 bl trace_hardirqs_on // enabled while in userspace
818 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
821 * "slow" syscall return path.
824 disable_irq // disable interrupts
825 ldr x1, [tsk, #TSK_TI_FLAGS]
826 and x2, x1, #_TIF_WORK_MASK
827 cbnz x2, work_pending
829 enable_step_tsk x1, x2
838 adrp stbl, sys_call_table // load syscall table pointer
839 mov wscno, w8 // syscall number in w8
840 mov wsc_nr, #__NR_syscalls
841 el0_svc_naked: // compat entry point
842 stp x0, xscno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
846 ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks
847 tst x16, #_TIF_SYSCALL_WORK
849 cmp wscno, wsc_nr // check upper syscall limit
851 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
852 blr x16 // call sys_* routine
861 * This is the really slow path. We're going to be doing context
862 * switches, and waiting for our parent to respond.
865 cmp wscno, #NO_SYSCALL // user-issued syscall(-1)?
867 mov x0, #-ENOSYS // set default errno if so
870 bl syscall_trace_enter
871 cmp w0, #NO_SYSCALL // skip the syscall?
872 b.eq __sys_trace_return_skipped
873 mov wscno, w0 // syscall number (possibly new)
874 mov x1, sp // pointer to regs
875 cmp wscno, wsc_nr // check upper syscall limit
877 ldp x0, x1, [sp] // restore the syscall args
878 ldp x2, x3, [sp, #S_X2]
879 ldp x4, x5, [sp, #S_X4]
880 ldp x6, x7, [sp, #S_X6]
881 ldr x16, [stbl, xscno, lsl #3] // address in the syscall table
882 blr x16 // call sys_* routine
885 str x0, [sp, #S_X0] // save returned x0
886 __sys_trace_return_skipped:
888 bl syscall_trace_exit
896 .popsection // .entry.text
899 * Special system call wrappers.
901 ENTRY(sys_rt_sigreturn_wrapper)
904 ENDPROC(sys_rt_sigreturn_wrapper)
907 * Register switch for AArch64. The callee-saved registers need to be saved
908 * and restored. On entry:
909 * x0 = previous task_struct (must be preserved across the switch)
910 * x1 = next task_struct
911 * Previous and next are guaranteed not to be the same.
915 mov x10, #THREAD_CPU_CONTEXT
918 stp x19, x20, [x8], #16 // store callee-saved registers
919 stp x21, x22, [x8], #16
920 stp x23, x24, [x8], #16
921 stp x25, x26, [x8], #16
922 stp x27, x28, [x8], #16
923 stp x29, x9, [x8], #16
926 ldp x19, x20, [x8], #16 // restore callee-saved registers
927 ldp x21, x22, [x8], #16
928 ldp x23, x24, [x8], #16
929 ldp x25, x26, [x8], #16
930 ldp x27, x28, [x8], #16
931 ldp x29, x9, [x8], #16
936 ENDPROC(cpu_switch_to)
937 NOKPROBE(cpu_switch_to)
940 * This is how we return from a fork.
944 cbz x19, 1f // not a kernel thread
947 1: get_thread_info tsk
949 ENDPROC(ret_from_fork)
950 NOKPROBE(ret_from_fork)