arch/arm64/kernel/cpuinfo.c

   1 /*
   2  * Record and handle CPU attributes.
   3  *
   4  * Copyright (C) 2014 ARM Ltd.
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17 #include <asm/arch_timer.h>
  18 #include <asm/cache.h>
  19 #include <asm/cpu.h>
  20 #include <asm/cputype.h>
  21 #include <asm/cpufeature.h>
  22
  23 #include <linux/bitops.h>
  24 #include <linux/bug.h>
  25 #include <linux/compat.h>
  26 #include <linux/elf.h>
  27 #include <linux/init.h>
  28 #include <linux/kernel.h>
  29 #include <linux/personality.h>
  30 #include <linux/preempt.h>
  31 #include <linux/printk.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/sched.h>
  34 #include <linux/smp.h>
  35 #include <linux/delay.h>
  36
  37 /*
  38  * In case the boot CPU is hotpluggable, we record its initial state and
  39  * current state separately. Certain system registers may contain different
  40  * values depending on configuration at or after reset.
  41  */
  42 DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data);
  43 static struct cpuinfo_arm64 boot_cpu_data;
  44
  45 static char *icache_policy_str[] = {
  46         [0 ... ICACHE_POLICY_PIPT]      = "RESERVED/UNKNOWN",
  47         [ICACHE_POLICY_VIPT]            = "VIPT",
  48         [ICACHE_POLICY_PIPT]            = "PIPT",
  49         [ICACHE_POLICY_VPIPT]           = "VPIPT",
  50 };
  51
  52 unsigned long __icache_flags;
  53
  54 static const char *const hwcap_str[] = {
  55         "fp",
  56         "asimd",
  57         "evtstrm",
  58         "aes",
  59         "pmull",
  60         "sha1",
  61         "sha2",
  62         "crc32",
  63         "atomics",
  64         "fphp",
  65         "asimdhp",
  66         "cpuid",
  67         "asimdrdm",
  68         "jscvt",
  69         "fcma",
  70         "lrcpc",
  71         "dcpop",
  72         NULL
  73 };
  74
  75 #ifdef CONFIG_COMPAT
  76 static const char *const compat_hwcap_str[] = {
  77         "swp",
  78         "half",
  79         "thumb",
  80         "26bit",
  81         "fastmult",
  82         "fpa",
  83         "vfp",
  84         "edsp",
  85         "java",
  86         "iwmmxt",
  87         "crunch",
  88         "thumbee",
  89         "neon",
  90         "vfpv3",
  91         "vfpv3d16",
  92         "tls",
  93         "vfpv4",
  94         "idiva",
  95         "idivt",
  96         "vfpd32",
  97         "lpae",
  98         "evtstrm",
  99         NULL
 100 };
 101
 102 static const char *const compat_hwcap2_str[] = {
 103         "aes",
 104         "pmull",
 105         "sha1",
 106         "sha2",
 107         "crc32",
 108         NULL
 109 };
 110 #endif /* CONFIG_COMPAT */
 111
 112 static int c_show(struct seq_file *m, void *v)
 113 {
 114         int i, j;
 115         bool compat = personality(current->personality) == PER_LINUX32;
 116
 117         for_each_online_cpu(i) {
 118                 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i);
 119                 u32 midr = cpuinfo->reg_midr;
 120
 121                 /*
 122                  * glibc reads /proc/cpuinfo to determine the number of
 123                  * online processors, looking for lines beginning with
 124                  * "processor".  Give glibc what it expects.
 125                  */
 126                 seq_printf(m, "processor\t: %d\n", i);
 127                 if (compat)
 128                         seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
 129                                    MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
 130
 131                 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
 132                            loops_per_jiffy / (500000UL/HZ),
 133                            loops_per_jiffy / (5000UL/HZ) % 100);
 134
 135                 /*
 136                  * Dump out the common processor features in a single line.
 137                  * Userspace should read the hwcaps with getauxval(AT_HWCAP)
 138                  * rather than attempting to parse this, but there's a body of
 139                  * software which does already (at least for 32-bit).
 140                  */
 141                 seq_puts(m, "Features\t:");
 142                 if (compat) {
 143 #ifdef CONFIG_COMPAT
 144                         for (j = 0; compat_hwcap_str[j]; j++)
 145                                 if (compat_elf_hwcap & (1 << j))
 146                                         seq_printf(m, " %s", compat_hwcap_str[j]);
 147
 148                         for (j = 0; compat_hwcap2_str[j]; j++)
 149                                 if (compat_elf_hwcap2 & (1 << j))
 150                                         seq_printf(m, " %s", compat_hwcap2_str[j]);
 151 #endif /* CONFIG_COMPAT */
 152                 } else {
 153                         for (j = 0; hwcap_str[j]; j++)
 154                                 if (elf_hwcap & (1 << j))
 155                                         seq_printf(m, " %s", hwcap_str[j]);
 156                 }
 157                 seq_puts(m, "\n");
 158
 159                 seq_printf(m, "CPU implementer\t: 0x%02x\n",
 160                            MIDR_IMPLEMENTOR(midr));
 161                 seq_printf(m, "CPU architecture: 8\n");
 162                 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr));
 163                 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr));
 164                 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr));
 165         }
 166
 167         return 0;
 168 }
 169
 170 static void *c_start(struct seq_file *m, loff_t *pos)
 171 {
 172         return *pos < 1 ? (void *)1 : NULL;
 173 }
 174
 175 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 176 {
 177         ++*pos;
 178         return NULL;
 179 }
 180
 181 static void c_stop(struct seq_file *m, void *v)
 182 {
 183 }
 184
 185 const struct seq_operations cpuinfo_op = {
 186         .start  = c_start,
 187         .next   = c_next,
 188         .stop   = c_stop,
 189         .show   = c_show
 190 };
 191
 192
 193 static struct kobj_type cpuregs_kobj_type = {
 194         .sysfs_ops = &kobj_sysfs_ops,
 195 };
 196
 197 /*
 198  * The ARM ARM uses the phrase "32-bit register" to describe a register
 199  * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however
 200  * no statement is made as to whether the upper 32 bits will or will not
 201  * be made use of in future, and between ARM DDI 0487A.c and ARM DDI
 202  * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit.
 203  *
 204  * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit
 205  * registers, we expose them both as 64 bit values to cater for possible
 206  * future expansion without an ABI break.
 207  */
 208 #define kobj_to_cpuinfo(kobj)   container_of(kobj, struct cpuinfo_arm64, kobj)
 209 #define CPUREGS_ATTR_RO(_name, _field)                                          \
 210         static ssize_t _name##_show(struct kobject *kobj,                       \
 211                         struct kobj_attribute *attr, char *buf)                 \
 212         {                                                                       \
 213                 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj);             \
 214                                                                                 \
 215                 if (info->reg_midr)                                             \
 216                         return sprintf(buf, "0x%016x\n", info->reg_##_field);   \
 217                 else                                                            \
 218                         return 0;                                               \
 219         }                                                                       \
 220         static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name)
 221
 222 CPUREGS_ATTR_RO(midr_el1, midr);
 223 CPUREGS_ATTR_RO(revidr_el1, revidr);
 224
 225 static struct attribute *cpuregs_id_attrs[] = {
 226         &cpuregs_attr_midr_el1.attr,
 227         &cpuregs_attr_revidr_el1.attr,
 228         NULL
 229 };
 230
 231 static const struct attribute_group cpuregs_attr_group = {
 232         .attrs = cpuregs_id_attrs,
 233         .name = "identification"
 234 };
 235
 236 static int cpuid_cpu_online(unsigned int cpu)
 237 {
 238         int rc;
 239         struct device *dev;
 240         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 241
 242         dev = get_cpu_device(cpu);
 243         if (!dev) {
 244                 rc = -ENODEV;
 245                 goto out;
 246         }
 247         rc = kobject_add(&info->kobj, &dev->kobj, "regs");
 248         if (rc)
 249                 goto out;
 250         rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group);
 251         if (rc)
 252                 kobject_del(&info->kobj);
 253 out:
 254         return rc;
 255 }
 256
 257 static int cpuid_cpu_offline(unsigned int cpu)
 258 {
 259         struct device *dev;
 260         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 261
 262         dev = get_cpu_device(cpu);
 263         if (!dev)
 264                 return -ENODEV;
 265         if (info->kobj.parent) {
 266                 sysfs_remove_group(&info->kobj, &cpuregs_attr_group);
 267                 kobject_del(&info->kobj);
 268         }
 269
 270         return 0;
 271 }
 272
 273 static int __init cpuinfo_regs_init(void)
 274 {
 275         int cpu, ret;
 276
 277         for_each_possible_cpu(cpu) {
 278                 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu);
 279
 280                 kobject_init(&info->kobj, &cpuregs_kobj_type);
 281         }
 282
 283         ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online",
 284                                 cpuid_cpu_online, cpuid_cpu_offline);
 285         if (ret < 0) {
 286                 pr_err("cpuinfo: failed to register hotplug callbacks.\n");
 287                 return ret;
 288         }
 289         return 0;
 290 }
 291 static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
 292 {
 293         unsigned int cpu = smp_processor_id();
 294         u32 l1ip = CTR_L1IP(info->reg_ctr);
 295
 296         switch (l1ip) {
 297         case ICACHE_POLICY_PIPT:
 298                 break;
 299         case ICACHE_POLICY_VPIPT:
 300                 set_bit(ICACHEF_VPIPT, &__icache_flags);
 301                 break;
 302         default:
 303                 /* Fallthrough */
 304         case ICACHE_POLICY_VIPT:
 305                 /* Assume aliasing */
 306                 set_bit(ICACHEF_ALIASING, &__icache_flags);
 307         }
 308
 309         pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
 310 }
 311
 312 static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
 313 {
 314         info->reg_cntfrq = arch_timer_get_cntfrq();
 315         info->reg_ctr = read_cpuid_cachetype();
 316         info->reg_dczid = read_cpuid(DCZID_EL0);
 317         info->reg_midr = read_cpuid_id();
 318         info->reg_revidr = read_cpuid(REVIDR_EL1);
 319
 320         info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1);
 321         info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
 322         info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
 323         info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
 324         info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
 325         info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
 326         info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
 327         info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1);
 328         info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1);
 329
 330         /* Update the 32bit ID registers only if AArch32 is implemented */
 331         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 332                 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
 333                 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
 334                 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
 335                 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
 336                 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1);
 337                 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1);
 338                 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1);
 339                 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1);
 340                 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1);
 341                 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1);
 342                 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1);
 343                 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1);
 344                 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1);
 345
 346                 info->reg_mvfr0 = read_cpuid(MVFR0_EL1);
 347                 info->reg_mvfr1 = read_cpuid(MVFR1_EL1);
 348                 info->reg_mvfr2 = read_cpuid(MVFR2_EL1);
 349         }
 350
 351         cpuinfo_detect_icache_policy(info);
 352 }
 353
 354 void cpuinfo_store_cpu(void)
 355 {
 356         struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
 357         __cpuinfo_store_cpu(info);
 358         update_cpu_features(smp_processor_id(), info, &boot_cpu_data);
 359 }
 360
 361 void __init cpuinfo_store_boot_cpu(void)
 362 {
 363         struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0);
 364         __cpuinfo_store_cpu(info);
 365
 366         boot_cpu_data = *info;
 367         init_cpu_features(&boot_cpu_data);
 368 }
 369
 370 device_initcall(cpuinfo_regs_init);