arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/crash_dump.h>
  24 #include <linux/sort.h>
  25 #include <linux/stop_machine.h>
  26 #include <linux/types.h>
  27 #include <linux/mm.h>
  28 #include <linux/cpu.h>
  29 #include <asm/cpu.h>
  30 #include <asm/cpufeature.h>
  31 #include <asm/cpu_ops.h>
  32 #include <asm/fpsimd.h>
  33 #include <asm/mmu_context.h>
  34 #include <asm/processor.h>
  35 #include <asm/sysreg.h>
  36 #include <asm/traps.h>
  37 #include <asm/virt.h>
  38
  39 /* Kernel representation of AT_HWCAP and AT_HWCAP2 */
  40 static unsigned long elf_hwcap __read_mostly;
  41
  42 #ifdef CONFIG_COMPAT
  43 #define COMPAT_ELF_HWCAP_DEFAULT        \
  44                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  45                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  46                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  47                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  48                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  49                                  COMPAT_HWCAP_LPAE)
  50 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  51 unsigned int compat_elf_hwcap2 __read_mostly;
  52 #endif
  53
  54 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  55 EXPORT_SYMBOL(cpu_hwcaps);
  56 static struct arm64_cpu_capabilities const __ro_after_init *cpu_hwcaps_ptrs[ARM64_NCAPS];
  57
  58 /* Need also bit for ARM64_CB_PATCH */
  59 DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
  60
  61 /*
  62  * Flag to indicate if we have computed the system wide
  63  * capabilities based on the boot time active CPUs. This
  64  * will be used to determine if a new booting CPU should
  65  * go through the verification process to make sure that it
  66  * supports the system capabilities, without using a hotplug
  67  * notifier.
  68  */
  69 static bool sys_caps_initialised;
  70
  71 static inline void set_sys_caps_initialised(void)
  72 {
  73         sys_caps_initialised = true;
  74 }
  75
  76 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  77 {
  78         /* file-wide pr_fmt adds "CPU features: " prefix */
  79         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  80         return 0;
  81 }
  82
  83 static struct notifier_block cpu_hwcaps_notifier = {
  84         .notifier_call = dump_cpu_hwcaps
  85 };
  86
  87 static int __init register_cpu_hwcaps_dumper(void)
  88 {
  89         atomic_notifier_chain_register(&panic_notifier_list,
  90                                        &cpu_hwcaps_notifier);
  91         return 0;
  92 }
  93 __initcall(register_cpu_hwcaps_dumper);
  94
  95 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  96 EXPORT_SYMBOL(cpu_hwcap_keys);
  97
  98 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  99         {                                               \
 100                 .sign = SIGNED,                         \
 101                 .visible = VISIBLE,                     \
 102                 .strict = STRICT,                       \
 103                 .type = TYPE,                           \
 104                 .shift = SHIFT,                         \
 105                 .width = WIDTH,                         \
 106                 .safe_val = SAFE_VAL,                   \
 107         }
 108
 109 /* Define a feature with unsigned values */
 110 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 111         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 112
 113 /* Define a feature with a signed value */
 114 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 115         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 116
 117 #define ARM64_FTR_END                                   \
 118         {                                               \
 119                 .width = 0,                             \
 120         }
 121
 122 /* meta feature for alternatives */
 123 static bool __maybe_unused
 124 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 125
 126 static void cpu_enable_cnp(struct arm64_cpu_capabilities const *cap);
 127
 128 /*
 129  * NOTE: Any changes to the visibility of features should be kept in
 130  * sync with the documentation of the CPU feature register ABI.
 131  */
 132 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 137         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 138         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 139         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 140         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 141         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 145         ARM64_FTR_END,
 146 };
 147
 148 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 149         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_SB_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 151                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPI_SHIFT, 4, 0),
 152         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 153                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_GPA_SHIFT, 4, 0),
 154         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 155         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 156         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 157         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 158                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_API_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_PTR_AUTH),
 160                        FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_APA_SHIFT, 4, 0),
 161         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 162         ARM64_FTR_END,
 163 };
 164
 165 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 166         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 167         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 168         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
 169         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 170                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 172         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 173         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 174         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 175         /* Linux doesn't care about the EL3 */
 176         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 177         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 178         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 179         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 180         ARM64_FTR_END,
 181 };
 182
 183 static const struct arm64_ftr_bits ftr_id_aa64pfr1[] = {
 184         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR1_SSBS_SHIFT, 4, ID_AA64PFR1_SSBS_PSTATE_NI),
 185         ARM64_FTR_END,
 186 };
 187
 188 static const struct arm64_ftr_bits ftr_id_aa64zfr0[] = {
 189         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SM4_SHIFT, 4, 0),
 190         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SHA3_SHIFT, 4, 0),
 191         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_BITPERM_SHIFT, 4, 0),
 192         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_AES_SHIFT, 4, 0),
 193         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ZFR0_SVEVER_SHIFT, 4, 0),
 194         ARM64_FTR_END,
 195 };
 196
 197 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 198         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 199         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 200         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 201         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 202         /* Linux shouldn't care about secure memory */
 203         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 204         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 205         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 206         /*
 207          * Differing PARange is fine as long as all peripherals and memory are mapped
 208          * within the minimum PARange of all CPUs
 209          */
 210         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 211         ARM64_FTR_END,
 212 };
 213
 214 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 215         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 216         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 217         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 218         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 219         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 220         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 221         ARM64_FTR_END,
 222 };
 223
 224 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 225         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
 226         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
 227         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 228         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 229         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 232         ARM64_FTR_END,
 233 };
 234
 235 static const struct arm64_ftr_bits ftr_ctr[] = {
 236         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1), /* RES1 */
 237         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DIC_SHIFT, 1, 1),
 238         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IDC_SHIFT, 1, 1),
 239         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_CWG_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, CTR_ERG_SHIFT, 4, 0),
 241         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_DMINLINE_SHIFT, 4, 1),
 242         /*
 243          * Linux can handle differing I-cache policies. Userspace JITs will
 244          * make use of *minLine.
 245          * If we have differing I-cache policies, report it as the weakest - VIPT.
 246          */
 247         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 248         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, CTR_IMINLINE_SHIFT, 4, 0),
 249         ARM64_FTR_END,
 250 };
 251
 252 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 253         .name           = "SYS_CTR_EL0",
 254         .ftr_bits       = ftr_ctr
 255 };
 256
 257 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 258         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 259         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 260         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 261         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 262         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 263         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 264         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 266         ARM64_FTR_END,
 267 };
 268
 269 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 270         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 271         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 272         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 273         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 274         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 275         /*
 276          * We can instantiate multiple PMU instances with different levels
 277          * of support.
 278          */
 279         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 282         ARM64_FTR_END,
 283 };
 284
 285 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 286         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 287         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 288         ARM64_FTR_END,
 289 };
 290
 291 static const struct arm64_ftr_bits ftr_dczid[] = {
 292         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 293         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 294         ARM64_FTR_END,
 295 };
 296
 297
 298 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 299         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 301         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 302         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 303         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 304         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 305         ARM64_FTR_END,
 306 };
 307
 308 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 309         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 310         ARM64_FTR_END,
 311 };
 312
 313 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 314         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 318         ARM64_FTR_END,
 319 };
 320
 321 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 322         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 323         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 324         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 326         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 327         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 328         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 329         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 330         ARM64_FTR_END,
 331 };
 332
 333 static const struct arm64_ftr_bits ftr_zcr[] = {
 334         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 335                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 336         ARM64_FTR_END,
 337 };
 338
 339 /*
 340  * Common ftr bits for a 32bit register with all hidden, strict
 341  * attributes, with 4bit feature fields and a default safe value of
 342  * 0. Covers the following 32bit registers:
 343  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 344  */
 345 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 346         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 347         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 348         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 349         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 350         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 351         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 352         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 353         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 354         ARM64_FTR_END,
 355 };
 356
 357 /* Table for a single 32bit feature value */
 358 static const struct arm64_ftr_bits ftr_single32[] = {
 359         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 360         ARM64_FTR_END,
 361 };
 362
 363 static const struct arm64_ftr_bits ftr_raz[] = {
 364         ARM64_FTR_END,
 365 };
 366
 367 #define ARM64_FTR_REG(id, table) {              \
 368         .sys_id = id,                           \
 369         .reg =  &(struct arm64_ftr_reg){        \
 370                 .name = #id,                    \
 371                 .ftr_bits = &((table)[0]),      \
 372         }}
 373
 374 static const struct __ftr_reg_entry {
 375         u32                     sys_id;
 376         struct arm64_ftr_reg    *reg;
 377 } arm64_ftr_regs[] = {
 378
 379         /* Op1 = 0, CRn = 0, CRm = 1 */
 380         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 381         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 382         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 383         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 384         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 385         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 386         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 387
 388         /* Op1 = 0, CRn = 0, CRm = 2 */
 389         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 390         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 391         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 392         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 393         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 394         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 395         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 396
 397         /* Op1 = 0, CRn = 0, CRm = 3 */
 398         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 399         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 400         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 401
 402         /* Op1 = 0, CRn = 0, CRm = 4 */
 403         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 404         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_id_aa64pfr1),
 405         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_id_aa64zfr0),
 406
 407         /* Op1 = 0, CRn = 0, CRm = 5 */
 408         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 409         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 410
 411         /* Op1 = 0, CRn = 0, CRm = 6 */
 412         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 413         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 414
 415         /* Op1 = 0, CRn = 0, CRm = 7 */
 416         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 417         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 418         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 419
 420         /* Op1 = 0, CRn = 1, CRm = 2 */
 421         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 422
 423         /* Op1 = 3, CRn = 0, CRm = 0 */
 424         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 425         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 426
 427         /* Op1 = 3, CRn = 14, CRm = 0 */
 428         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 429 };
 430
 431 static int search_cmp_ftr_reg(const void *id, const void *regp)
 432 {
 433         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 434 }
 435
 436 /*
 437  * get_arm64_ftr_reg - Lookup a feature register entry using its
 438  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 439  * ascending order of sys_id , we use binary search to find a matching
 440  * entry.
 441  *
 442  * returns - Upon success,  matching ftr_reg entry for id.
 443  *         - NULL on failure. It is upto the caller to decide
 444  *           the impact of a failure.
 445  */
 446 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 447 {
 448         const struct __ftr_reg_entry *ret;
 449
 450         ret = bsearch((const void *)(unsigned long)sys_id,
 451                         arm64_ftr_regs,
 452                         ARRAY_SIZE(arm64_ftr_regs),
 453                         sizeof(arm64_ftr_regs[0]),
 454                         search_cmp_ftr_reg);
 455         if (ret)
 456                 return ret->reg;
 457         return NULL;
 458 }
 459
 460 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 461                                s64 ftr_val)
 462 {
 463         u64 mask = arm64_ftr_mask(ftrp);
 464
 465         reg &= ~mask;
 466         reg |= (ftr_val << ftrp->shift) & mask;
 467         return reg;
 468 }
 469
 470 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 471                                 s64 cur)
 472 {
 473         s64 ret = 0;
 474
 475         switch (ftrp->type) {
 476         case FTR_EXACT:
 477                 ret = ftrp->safe_val;
 478                 break;
 479         case FTR_LOWER_SAFE:
 480                 ret = new < cur ? new : cur;
 481                 break;
 482         case FTR_HIGHER_SAFE:
 483                 ret = new > cur ? new : cur;
 484                 break;
 485         default:
 486                 BUG();
 487         }
 488
 489         return ret;
 490 }
 491
 492 static void __init sort_ftr_regs(void)
 493 {
 494         int i;
 495
 496         /* Check that the array is sorted so that we can do the binary search */
 497         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 498                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 499 }
 500
 501 /*
 502  * Initialise the CPU feature register from Boot CPU values.
 503  * Also initiliases the strict_mask for the register.
 504  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 505  * RES0 for the system-wide value, and must strictly match.
 506  */
 507 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 508 {
 509         u64 val = 0;
 510         u64 strict_mask = ~0x0ULL;
 511         u64 user_mask = 0;
 512         u64 valid_mask = 0;
 513
 514         const struct arm64_ftr_bits *ftrp;
 515         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 516
 517         BUG_ON(!reg);
 518
 519         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 520                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 521                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 522
 523                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 524
 525                 valid_mask |= ftr_mask;
 526                 if (!ftrp->strict)
 527                         strict_mask &= ~ftr_mask;
 528                 if (ftrp->visible)
 529                         user_mask |= ftr_mask;
 530                 else
 531                         reg->user_val = arm64_ftr_set_value(ftrp,
 532                                                             reg->user_val,
 533                                                             ftrp->safe_val);
 534         }
 535
 536         val &= valid_mask;
 537
 538         reg->sys_val = val;
 539         reg->strict_mask = strict_mask;
 540         reg->user_mask = user_mask;
 541 }
 542
 543 extern const struct arm64_cpu_capabilities arm64_errata[];
 544 static const struct arm64_cpu_capabilities arm64_features[];
 545
 546 static void __init
 547 init_cpu_hwcaps_indirect_list_from_array(const struct arm64_cpu_capabilities *caps)
 548 {
 549         for (; caps->matches; caps++) {
 550                 if (WARN(caps->capability >= ARM64_NCAPS,
 551                         "Invalid capability %d\n", caps->capability))
 552                         continue;
 553                 if (WARN(cpu_hwcaps_ptrs[caps->capability],
 554                         "Duplicate entry for capability %d\n",
 555                         caps->capability))
 556                         continue;
 557                 cpu_hwcaps_ptrs[caps->capability] = caps;
 558         }
 559 }
 560
 561 static void __init init_cpu_hwcaps_indirect_list(void)
 562 {
 563         init_cpu_hwcaps_indirect_list_from_array(arm64_features);
 564         init_cpu_hwcaps_indirect_list_from_array(arm64_errata);
 565 }
 566
 567 static void __init setup_boot_cpu_capabilities(void);
 568
 569 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 570 {
 571         /* Before we start using the tables, make sure it is sorted */
 572         sort_ftr_regs();
 573
 574         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 575         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 576         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 577         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 578         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 579         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 580         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 581         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 582         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 583         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 584         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 585         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 586         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 587
 588         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 589                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 590                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 591                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 592                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 593                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 594                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 595                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 596                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 597                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 598                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 599                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 600                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 601                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 602                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 603                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 604                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 605         }
 606
 607         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 608                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 609                 sve_init_vq_map();
 610         }
 611
 612         /*
 613          * Initialize the indirect array of CPU hwcaps capabilities pointers
 614          * before we handle the boot CPU below.
 615          */
 616         init_cpu_hwcaps_indirect_list();
 617
 618         /*
 619          * Detect and enable early CPU capabilities based on the boot CPU,
 620          * after we have initialised the CPU feature infrastructure.
 621          */
 622         setup_boot_cpu_capabilities();
 623 }
 624
 625 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 626 {
 627         const struct arm64_ftr_bits *ftrp;
 628
 629         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 630                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 631                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 632
 633                 if (ftr_cur == ftr_new)
 634                         continue;
 635                 /* Find a safe value */
 636                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 637                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 638         }
 639
 640 }
 641
 642 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 643 {
 644         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 645
 646         BUG_ON(!regp);
 647         update_cpu_ftr_reg(regp, val);
 648         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 649                 return 0;
 650         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 651                         regp->name, boot, cpu, val);
 652         return 1;
 653 }
 654
 655 /*
 656  * Update system wide CPU feature registers with the values from a
 657  * non-boot CPU. Also performs SANITY checks to make sure that there
 658  * aren't any insane variations from that of the boot CPU.
 659  */
 660 void update_cpu_features(int cpu,
 661                          struct cpuinfo_arm64 *info,
 662                          struct cpuinfo_arm64 *boot)
 663 {
 664         int taint = 0;
 665
 666         /*
 667          * The kernel can handle differing I-cache policies, but otherwise
 668          * caches should look identical. Userspace JITs will make use of
 669          * *minLine.
 670          */
 671         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 672                                       info->reg_ctr, boot->reg_ctr);
 673
 674         /*
 675          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 676          * could result in too much or too little memory being zeroed if a
 677          * process is preempted and migrated between CPUs.
 678          */
 679         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 680                                       info->reg_dczid, boot->reg_dczid);
 681
 682         /* If different, timekeeping will be broken (especially with KVM) */
 683         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 684                                       info->reg_cntfrq, boot->reg_cntfrq);
 685
 686         /*
 687          * The kernel uses self-hosted debug features and expects CPUs to
 688          * support identical debug features. We presently need CTX_CMPs, WRPs,
 689          * and BRPs to be identical.
 690          * ID_AA64DFR1 is currently RES0.
 691          */
 692         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 693                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 694         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 695                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 696         /*
 697          * Even in big.LITTLE, processors should be identical instruction-set
 698          * wise.
 699          */
 700         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 701                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 702         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 703                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 704
 705         /*
 706          * Differing PARange support is fine as long as all peripherals and
 707          * memory are mapped within the minimum PARange of all CPUs.
 708          * Linux should not care about secure memory.
 709          */
 710         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 711                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 712         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 713                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 714         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 715                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 716
 717         /*
 718          * EL3 is not our concern.
 719          */
 720         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 721                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 722         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 723                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 724
 725         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 726                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 727
 728         /*
 729          * If we have AArch32, we care about 32-bit features for compat.
 730          * If the system doesn't support AArch32, don't update them.
 731          */
 732         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 733                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 734
 735                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 736                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 737                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 738                                         info->reg_id_isar0, boot->reg_id_isar0);
 739                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 740                                         info->reg_id_isar1, boot->reg_id_isar1);
 741                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 742                                         info->reg_id_isar2, boot->reg_id_isar2);
 743                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 744                                         info->reg_id_isar3, boot->reg_id_isar3);
 745                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 746                                         info->reg_id_isar4, boot->reg_id_isar4);
 747                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 748                                         info->reg_id_isar5, boot->reg_id_isar5);
 749
 750                 /*
 751                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 752                  * ACTLR formats could differ across CPUs and therefore would have to
 753                  * be trapped for virtualization anyway.
 754                  */
 755                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 756                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 757                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 758                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 759                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 760                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 761                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 762                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 763                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 764                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 765                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 766                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 767                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 768                                         info->reg_mvfr0, boot->reg_mvfr0);
 769                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 770                                         info->reg_mvfr1, boot->reg_mvfr1);
 771                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 772                                         info->reg_mvfr2, boot->reg_mvfr2);
 773         }
 774
 775         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 776                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 777                                         info->reg_zcr, boot->reg_zcr);
 778
 779                 /* Probe vector lengths, unless we already gave up on SVE */
 780                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 781                     !sys_caps_initialised)
 782                         sve_update_vq_map();
 783         }
 784
 785         /*
 786          * Mismatched CPU features are a recipe for disaster. Don't even
 787          * pretend to support them.
 788          */
 789         if (taint) {
 790                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 791                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 792         }
 793 }
 794
 795 u64 read_sanitised_ftr_reg(u32 id)
 796 {
 797         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 798
 799         /* We shouldn't get a request for an unsupported register */
 800         BUG_ON(!regp);
 801         return regp->sys_val;
 802 }
 803
 804 #define read_sysreg_case(r)     \
 805         case r:         return read_sysreg_s(r)
 806
 807 /*
 808  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 809  * Read the system register on the current CPU
 810  */
 811 static u64 __read_sysreg_by_encoding(u32 sys_id)
 812 {
 813         switch (sys_id) {
 814         read_sysreg_case(SYS_ID_PFR0_EL1);
 815         read_sysreg_case(SYS_ID_PFR1_EL1);
 816         read_sysreg_case(SYS_ID_DFR0_EL1);
 817         read_sysreg_case(SYS_ID_MMFR0_EL1);
 818         read_sysreg_case(SYS_ID_MMFR1_EL1);
 819         read_sysreg_case(SYS_ID_MMFR2_EL1);
 820         read_sysreg_case(SYS_ID_MMFR3_EL1);
 821         read_sysreg_case(SYS_ID_ISAR0_EL1);
 822         read_sysreg_case(SYS_ID_ISAR1_EL1);
 823         read_sysreg_case(SYS_ID_ISAR2_EL1);
 824         read_sysreg_case(SYS_ID_ISAR3_EL1);
 825         read_sysreg_case(SYS_ID_ISAR4_EL1);
 826         read_sysreg_case(SYS_ID_ISAR5_EL1);
 827         read_sysreg_case(SYS_MVFR0_EL1);
 828         read_sysreg_case(SYS_MVFR1_EL1);
 829         read_sysreg_case(SYS_MVFR2_EL1);
 830
 831         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 832         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 833         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 834         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 835         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 836         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 837         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 838         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 839         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 840
 841         read_sysreg_case(SYS_CNTFRQ_EL0);
 842         read_sysreg_case(SYS_CTR_EL0);
 843         read_sysreg_case(SYS_DCZID_EL0);
 844
 845         default:
 846                 BUG();
 847                 return 0;
 848         }
 849 }
 850
 851 #include <linux/irqchip/arm-gic-v3.h>
 852
 853 static bool
 854 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 855 {
 856         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 857
 858         return val >= entry->min_field_value;
 859 }
 860
 861 static bool
 862 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 863 {
 864         u64 val;
 865
 866         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 867         if (scope == SCOPE_SYSTEM)
 868                 val = read_sanitised_ftr_reg(entry->sys_reg);
 869         else
 870                 val = __read_sysreg_by_encoding(entry->sys_reg);
 871
 872         return feature_matches(val, entry);
 873 }
 874
 875 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 876 {
 877         bool has_sre;
 878
 879         if (!has_cpuid_feature(entry, scope))
 880                 return false;
 881
 882         has_sre = gic_enable_sre();
 883         if (!has_sre)
 884                 pr_warn_once("%s present but disabled by higher exception level\n",
 885                              entry->desc);
 886
 887         return has_sre;
 888 }
 889
 890 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 891 {
 892         u32 midr = read_cpuid_id();
 893
 894         /* Cavium ThunderX pass 1.x and 2.x */
 895         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 896                 MIDR_CPU_VAR_REV(0, 0),
 897                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 898 }
 899
 900 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 901 {
 902         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 903
 904         return cpuid_feature_extract_signed_field(pfr0,
 905                                         ID_AA64PFR0_FP_SHIFT) < 0;
 906 }
 907
 908 static bool has_cache_idc(const struct arm64_cpu_capabilities *entry,
 909                           int scope)
 910 {
 911         u64 ctr;
 912
 913         if (scope == SCOPE_SYSTEM)
 914                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 915         else
 916                 ctr = read_cpuid_effective_cachetype();
 917
 918         return ctr & BIT(CTR_IDC_SHIFT);
 919 }
 920
 921 static void cpu_emulate_effective_ctr(const struct arm64_cpu_capabilities *__unused)
 922 {
 923         /*
 924          * If the CPU exposes raw CTR_EL0.IDC = 0, while effectively
 925          * CTR_EL0.IDC = 1 (from CLIDR values), we need to trap accesses
 926          * to the CTR_EL0 on this CPU and emulate it with the real/safe
 927          * value.
 928          */
 929         if (!(read_cpuid_cachetype() & BIT(CTR_IDC_SHIFT)))
 930                 sysreg_clear_set(sctlr_el1, SCTLR_EL1_UCT, 0);
 931 }
 932
 933 static bool has_cache_dic(const struct arm64_cpu_capabilities *entry,
 934                           int scope)
 935 {
 936         u64 ctr;
 937
 938         if (scope == SCOPE_SYSTEM)
 939                 ctr = arm64_ftr_reg_ctrel0.sys_val;
 940         else
 941                 ctr = read_cpuid_cachetype();
 942
 943         return ctr & BIT(CTR_DIC_SHIFT);
 944 }
 945
 946 static bool __maybe_unused
 947 has_useable_cnp(const struct arm64_cpu_capabilities *entry, int scope)
 948 {
 949         /*
 950          * Kdump isn't guaranteed to power-off all secondary CPUs, CNP
 951          * may share TLB entries with a CPU stuck in the crashed
 952          * kernel.
 953          */
 954          if (is_kdump_kernel())
 955                 return false;
 956
 957         return has_cpuid_feature(entry, scope);
 958 }
 959
 960 static bool __meltdown_safe = true;
 961 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 962
 963 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 964                                 int scope)
 965 {
 966         /* List of CPUs that are not vulnerable and don't need KPTI */
 967         static const struct midr_range kpti_safe_list[] = {
 968                 MIDR_ALL_VERSIONS(MIDR_CAVIUM_THUNDERX2),
 969                 MIDR_ALL_VERSIONS(MIDR_BRCM_VULCAN),
 970                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A35),
 971                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A53),
 972                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
 973                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A57),
 974                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A72),
 975                 MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
 976                 MIDR_ALL_VERSIONS(MIDR_HISI_TSV110),
 977                 { /* sentinel */ }
 978         };
 979         char const *str = "kpti command line option";
 980         bool meltdown_safe;
 981
 982         meltdown_safe = is_midr_in_range_list(read_cpuid_id(), kpti_safe_list);
 983
 984         /* Defer to CPU feature registers */
 985         if (has_cpuid_feature(entry, scope))
 986                 meltdown_safe = true;
 987
 988         if (!meltdown_safe)
 989                 __meltdown_safe = false;
 990
 991         /*
 992          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 993          * ThunderX leads to apparent I-cache corruption of kernel text, which
 994          * ends as well as you might imagine. Don't even try.
 995          */
 996         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 997                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 998                 __kpti_forced = -1;
 999         }
1000
1001         /* Useful for KASLR robustness */
1002         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE) && kaslr_offset() > 0) {
1003                 if (!__kpti_forced) {
1004                         str = "KASLR";
1005                         __kpti_forced = 1;
1006                 }
1007         }
1008
1009         if (cpu_mitigations_off() && !__kpti_forced) {
1010                 str = "mitigations=off";
1011                 __kpti_forced = -1;
1012         }
1013
1014         if (!IS_ENABLED(CONFIG_UNMAP_KERNEL_AT_EL0)) {
1015                 pr_info_once("kernel page table isolation disabled by kernel configuration\n");
1016                 return false;
1017         }
1018
1019         /* Forced? */
1020         if (__kpti_forced) {
1021                 pr_info_once("kernel page table isolation forced %s by %s\n",
1022                              __kpti_forced > 0 ? "ON" : "OFF", str);
1023                 return __kpti_forced > 0;
1024         }
1025
1026         return !meltdown_safe;
1027 }
1028
1029 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1030 static void
1031 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1032 {
1033         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
1034         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
1035         kpti_remap_fn *remap_fn;
1036
1037         static bool kpti_applied = false;
1038         int cpu = smp_processor_id();
1039
1040         /*
1041          * We don't need to rewrite the page-tables if either we've done
1042          * it already or we have KASLR enabled and therefore have not
1043          * created any global mappings at all.
1044          */
1045         if (kpti_applied || kaslr_offset() > 0)
1046                 return;
1047
1048         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
1049
1050         cpu_install_idmap();
1051         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
1052         cpu_uninstall_idmap();
1053
1054         if (!cpu)
1055                 kpti_applied = true;
1056
1057         return;
1058 }
1059 #else
1060 static void
1061 kpti_install_ng_mappings(const struct arm64_cpu_capabilities *__unused)
1062 {
1063 }
1064 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
1065
1066 static int __init parse_kpti(char *str)
1067 {
1068         bool enabled;
1069         int ret = strtobool(str, &enabled);
1070
1071         if (ret)
1072                 return ret;
1073
1074         __kpti_forced = enabled ? 1 : -1;
1075         return 0;
1076 }
1077 early_param("kpti", parse_kpti);
1078
1079 #ifdef CONFIG_ARM64_HW_AFDBM
1080 static inline void __cpu_enable_hw_dbm(void)
1081 {
1082         u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
1083
1084         write_sysreg(tcr, tcr_el1);
1085         isb();
1086 }
1087
1088 static bool cpu_has_broken_dbm(void)
1089 {
1090         /* List of CPUs which have broken DBM support. */
1091         static const struct midr_range cpus[] = {
1092 #ifdef CONFIG_ARM64_ERRATUM_1024718
1093                 MIDR_RANGE(MIDR_CORTEX_A55, 0, 0, 1, 0),  // A55 r0p0 -r1p0
1094 #endif
1095                 {},
1096         };
1097
1098         return is_midr_in_range_list(read_cpuid_id(), cpus);
1099 }
1100
1101 static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap)
1102 {
1103         return has_cpuid_feature(cap, SCOPE_LOCAL_CPU) &&
1104                !cpu_has_broken_dbm();
1105 }
1106
1107 static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap)
1108 {
1109         if (cpu_can_use_dbm(cap))
1110                 __cpu_enable_hw_dbm();
1111 }
1112
1113 static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
1114                        int __unused)
1115 {
1116         static bool detected = false;
1117         /*
1118          * DBM is a non-conflicting feature. i.e, the kernel can safely
1119          * run a mix of CPUs with and without the feature. So, we
1120          * unconditionally enable the capability to allow any late CPU
1121          * to use the feature. We only enable the control bits on the
1122          * CPU, if it actually supports.
1123          *
1124          * We have to make sure we print the "feature" detection only
1125          * when at least one CPU actually uses it. So check if this CPU
1126          * can actually use it and print the message exactly once.
1127          *
1128          * This is safe as all CPUs (including secondary CPUs - due to the
1129          * LOCAL_CPU scope - and the hotplugged CPUs - via verification)
1130          * goes through the "matches" check exactly once. Also if a CPU
1131          * matches the criteria, it is guaranteed that the CPU will turn
1132          * the DBM on, as the capability is unconditionally enabled.
1133          */
1134         if (!detected && cpu_can_use_dbm(cap)) {
1135                 detected = true;
1136                 pr_info("detected: Hardware dirty bit management\n");
1137         }
1138
1139         return true;
1140 }
1141
1142 #endif
1143
1144 #ifdef CONFIG_ARM64_VHE
1145 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
1146 {
1147         return is_kernel_in_hyp_mode();
1148 }
1149
1150 static void cpu_copy_el2regs(const struct arm64_cpu_capabilities *__unused)
1151 {
1152         /*
1153          * Copy register values that aren't redirected by hardware.
1154          *
1155          * Before code patching, we only set tpidr_el1, all CPUs need to copy
1156          * this value to tpidr_el2 before we patch the code. Once we've done
1157          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
1158          * do anything here.
1159          */
1160         if (!alternative_is_applied(ARM64_HAS_VIRT_HOST_EXTN))
1161                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
1162 }
1163 #endif
1164
1165 static void cpu_has_fwb(const struct arm64_cpu_capabilities *__unused)
1166 {
1167         u64 val = read_sysreg_s(SYS_CLIDR_EL1);
1168
1169         /* Check that CLIDR_EL1.LOU{U,IS} are both 0 */
1170         WARN_ON(val & (7 << 27 | 7 << 21));
1171 }
1172
1173 #ifdef CONFIG_ARM64_SSBD
1174 static int ssbs_emulation_handler(struct pt_regs *regs, u32 instr)
1175 {
1176         if (user_mode(regs))
1177                 return 1;
1178
1179         if (instr & BIT(PSTATE_Imm_shift))
1180                 regs->pstate |= PSR_SSBS_BIT;
1181         else
1182                 regs->pstate &= ~PSR_SSBS_BIT;
1183
1184         arm64_skip_faulting_instruction(regs, 4);
1185         return 0;
1186 }
1187
1188 static struct undef_hook ssbs_emulation_hook = {
1189         .instr_mask     = ~(1U << PSTATE_Imm_shift),
1190         .instr_val      = 0xd500401f | PSTATE_SSBS,
1191         .fn             = ssbs_emulation_handler,
1192 };
1193
1194 static void cpu_enable_ssbs(const struct arm64_cpu_capabilities *__unused)
1195 {
1196         static bool undef_hook_registered = false;
1197         static DEFINE_SPINLOCK(hook_lock);
1198
1199         spin_lock(&hook_lock);
1200         if (!undef_hook_registered) {
1201                 register_undef_hook(&ssbs_emulation_hook);
1202                 undef_hook_registered = true;
1203         }
1204         spin_unlock(&hook_lock);
1205
1206         if (arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
1207                 sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_DSSBS);
1208                 arm64_set_ssbd_mitigation(false);
1209         } else {
1210                 arm64_set_ssbd_mitigation(true);
1211         }
1212 }
1213 #endif /* CONFIG_ARM64_SSBD */
1214
1215 #ifdef CONFIG_ARM64_PAN
1216 static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused)
1217 {
1218         /*
1219          * We modify PSTATE. This won't work from irq context as the PSTATE
1220          * is discarded once we return from the exception.
1221          */
1222         WARN_ON_ONCE(in_interrupt());
1223
1224         sysreg_clear_set(sctlr_el1, SCTLR_EL1_SPAN, 0);
1225         asm(SET_PSTATE_PAN(1));
1226 }
1227 #endif /* CONFIG_ARM64_PAN */
1228
1229 #ifdef CONFIG_ARM64_RAS_EXTN
1230 static void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused)
1231 {
1232         /* Firmware may have left a deferred SError in this register. */
1233         write_sysreg_s(0, SYS_DISR_EL1);
1234 }
1235 #endif /* CONFIG_ARM64_RAS_EXTN */
1236
1237 #ifdef CONFIG_ARM64_PTR_AUTH
1238 static void cpu_enable_address_auth(struct arm64_cpu_capabilities const *cap)
1239 {
1240         sysreg_clear_set(sctlr_el1, 0, SCTLR_ELx_ENIA | SCTLR_ELx_ENIB |
1241                                        SCTLR_ELx_ENDA | SCTLR_ELx_ENDB);
1242 }
1243 #endif /* CONFIG_ARM64_PTR_AUTH */
1244
1245 #ifdef CONFIG_ARM64_PSEUDO_NMI
1246 static bool enable_pseudo_nmi;
1247
1248 static int __init early_enable_pseudo_nmi(char *p)
1249 {
1250         return strtobool(p, &enable_pseudo_nmi);
1251 }
1252 early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi);
1253
1254 static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry,
1255                                    int scope)
1256 {
1257         return enable_pseudo_nmi && has_useable_gicv3_cpuif(entry, scope);
1258 }
1259 #endif
1260
1261 static const struct arm64_cpu_capabilities arm64_features[] = {
1262         {
1263                 .desc = "GIC system register CPU interface",
1264                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
1265                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1266                 .matches = has_useable_gicv3_cpuif,
1267                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1268                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1269                 .sign = FTR_UNSIGNED,
1270                 .min_field_value = 1,
1271         },
1272 #ifdef CONFIG_ARM64_PAN
1273         {
1274                 .desc = "Privileged Access Never",
1275                 .capability = ARM64_HAS_PAN,
1276                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1277                 .matches = has_cpuid_feature,
1278                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1279                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
1280                 .sign = FTR_UNSIGNED,
1281                 .min_field_value = 1,
1282                 .cpu_enable = cpu_enable_pan,
1283         },
1284 #endif /* CONFIG_ARM64_PAN */
1285 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
1286         {
1287                 .desc = "LSE atomic instructions",
1288                 .capability = ARM64_HAS_LSE_ATOMICS,
1289                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1290                 .matches = has_cpuid_feature,
1291                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1292                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
1293                 .sign = FTR_UNSIGNED,
1294                 .min_field_value = 2,
1295         },
1296 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
1297         {
1298                 .desc = "Software prefetching using PRFM",
1299                 .capability = ARM64_HAS_NO_HW_PREFETCH,
1300                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1301                 .matches = has_no_hw_prefetch,
1302         },
1303 #ifdef CONFIG_ARM64_UAO
1304         {
1305                 .desc = "User Access Override",
1306                 .capability = ARM64_HAS_UAO,
1307                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1308                 .matches = has_cpuid_feature,
1309                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1310                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1311                 .min_field_value = 1,
1312                 /*
1313                  * We rely on stop_machine() calling uao_thread_switch() to set
1314                  * UAO immediately after patching.
1315                  */
1316         },
1317 #endif /* CONFIG_ARM64_UAO */
1318 #ifdef CONFIG_ARM64_PAN
1319         {
1320                 .capability = ARM64_ALT_PAN_NOT_UAO,
1321                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1322                 .matches = cpufeature_pan_not_uao,
1323         },
1324 #endif /* CONFIG_ARM64_PAN */
1325 #ifdef CONFIG_ARM64_VHE
1326         {
1327                 .desc = "Virtualization Host Extensions",
1328                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1329                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1330                 .matches = runs_at_el2,
1331                 .cpu_enable = cpu_copy_el2regs,
1332         },
1333 #endif  /* CONFIG_ARM64_VHE */
1334         {
1335                 .desc = "32-bit EL0 Support",
1336                 .capability = ARM64_HAS_32BIT_EL0,
1337                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1338                 .matches = has_cpuid_feature,
1339                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1340                 .sign = FTR_UNSIGNED,
1341                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1342                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1343         },
1344         {
1345                 .desc = "Kernel page table isolation (KPTI)",
1346                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1347                 .type = ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE,
1348                 /*
1349                  * The ID feature fields below are used to indicate that
1350                  * the CPU doesn't need KPTI. See unmap_kernel_at_el0 for
1351                  * more details.
1352                  */
1353                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1354                 .field_pos = ID_AA64PFR0_CSV3_SHIFT,
1355                 .min_field_value = 1,
1356                 .matches = unmap_kernel_at_el0,
1357                 .cpu_enable = kpti_install_ng_mappings,
1358         },
1359         {
1360                 /* FP/SIMD is not implemented */
1361                 .capability = ARM64_HAS_NO_FPSIMD,
1362                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1363                 .min_field_value = 0,
1364                 .matches = has_no_fpsimd,
1365         },
1366 #ifdef CONFIG_ARM64_PMEM
1367         {
1368                 .desc = "Data cache clean to Point of Persistence",
1369                 .capability = ARM64_HAS_DCPOP,
1370                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1371                 .matches = has_cpuid_feature,
1372                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1373                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1374                 .min_field_value = 1,
1375         },
1376         {
1377                 .desc = "Data cache clean to Point of Deep Persistence",
1378                 .capability = ARM64_HAS_DCPODP,
1379                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1380                 .matches = has_cpuid_feature,
1381                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1382                 .sign = FTR_UNSIGNED,
1383                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1384                 .min_field_value = 2,
1385         },
1386 #endif
1387 #ifdef CONFIG_ARM64_SVE
1388         {
1389                 .desc = "Scalable Vector Extension",
1390                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1391                 .capability = ARM64_SVE,
1392                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1393                 .sign = FTR_UNSIGNED,
1394                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1395                 .min_field_value = ID_AA64PFR0_SVE,
1396                 .matches = has_cpuid_feature,
1397                 .cpu_enable = sve_kernel_enable,
1398         },
1399 #endif /* CONFIG_ARM64_SVE */
1400 #ifdef CONFIG_ARM64_RAS_EXTN
1401         {
1402                 .desc = "RAS Extension Support",
1403                 .capability = ARM64_HAS_RAS_EXTN,
1404                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1405                 .matches = has_cpuid_feature,
1406                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1407                 .sign = FTR_UNSIGNED,
1408                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1409                 .min_field_value = ID_AA64PFR0_RAS_V1,
1410                 .cpu_enable = cpu_clear_disr,
1411         },
1412 #endif /* CONFIG_ARM64_RAS_EXTN */
1413         {
1414                 .desc = "Data cache clean to the PoU not required for I/D coherence",
1415                 .capability = ARM64_HAS_CACHE_IDC,
1416                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1417                 .matches = has_cache_idc,
1418                 .cpu_enable = cpu_emulate_effective_ctr,
1419         },
1420         {
1421                 .desc = "Instruction cache invalidation not required for I/D coherence",
1422                 .capability = ARM64_HAS_CACHE_DIC,
1423                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1424                 .matches = has_cache_dic,
1425         },
1426         {
1427                 .desc = "Stage-2 Force Write-Back",
1428                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1429                 .capability = ARM64_HAS_STAGE2_FWB,
1430                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1431                 .sign = FTR_UNSIGNED,
1432                 .field_pos = ID_AA64MMFR2_FWB_SHIFT,
1433                 .min_field_value = 1,
1434                 .matches = has_cpuid_feature,
1435                 .cpu_enable = cpu_has_fwb,
1436         },
1437 #ifdef CONFIG_ARM64_HW_AFDBM
1438         {
1439                 /*
1440                  * Since we turn this on always, we don't want the user to
1441                  * think that the feature is available when it may not be.
1442                  * So hide the description.
1443                  *
1444                  * .desc = "Hardware pagetable Dirty Bit Management",
1445                  *
1446                  */
1447                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1448                 .capability = ARM64_HW_DBM,
1449                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
1450                 .sign = FTR_UNSIGNED,
1451                 .field_pos = ID_AA64MMFR1_HADBS_SHIFT,
1452                 .min_field_value = 2,
1453                 .matches = has_hw_dbm,
1454                 .cpu_enable = cpu_enable_hw_dbm,
1455         },
1456 #endif
1457         {
1458                 .desc = "CRC32 instructions",
1459                 .capability = ARM64_HAS_CRC32,
1460                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1461                 .matches = has_cpuid_feature,
1462                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
1463                 .field_pos = ID_AA64ISAR0_CRC32_SHIFT,
1464                 .min_field_value = 1,
1465         },
1466 #ifdef CONFIG_ARM64_SSBD
1467         {
1468                 .desc = "Speculative Store Bypassing Safe (SSBS)",
1469                 .capability = ARM64_SSBS,
1470                 .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
1471                 .matches = has_cpuid_feature,
1472                 .sys_reg = SYS_ID_AA64PFR1_EL1,
1473                 .field_pos = ID_AA64PFR1_SSBS_SHIFT,
1474                 .sign = FTR_UNSIGNED,
1475                 .min_field_value = ID_AA64PFR1_SSBS_PSTATE_ONLY,
1476                 .cpu_enable = cpu_enable_ssbs,
1477         },
1478 #endif
1479 #ifdef CONFIG_ARM64_CNP
1480         {
1481                 .desc = "Common not Private translations",
1482                 .capability = ARM64_HAS_CNP,
1483                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1484                 .matches = has_useable_cnp,
1485                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1486                 .sign = FTR_UNSIGNED,
1487                 .field_pos = ID_AA64MMFR2_CNP_SHIFT,
1488                 .min_field_value = 1,
1489                 .cpu_enable = cpu_enable_cnp,
1490         },
1491 #endif
1492         {
1493                 .desc = "Speculation barrier (SB)",
1494                 .capability = ARM64_HAS_SB,
1495                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1496                 .matches = has_cpuid_feature,
1497                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1498                 .field_pos = ID_AA64ISAR1_SB_SHIFT,
1499                 .sign = FTR_UNSIGNED,
1500                 .min_field_value = 1,
1501         },
1502 #ifdef CONFIG_ARM64_PTR_AUTH
1503         {
1504                 .desc = "Address authentication (architected algorithm)",
1505                 .capability = ARM64_HAS_ADDRESS_AUTH_ARCH,
1506                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1507                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1508                 .sign = FTR_UNSIGNED,
1509                 .field_pos = ID_AA64ISAR1_APA_SHIFT,
1510                 .min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
1511                 .matches = has_cpuid_feature,
1512                 .cpu_enable = cpu_enable_address_auth,
1513         },
1514         {
1515                 .desc = "Address authentication (IMP DEF algorithm)",
1516                 .capability = ARM64_HAS_ADDRESS_AUTH_IMP_DEF,
1517                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1518                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1519                 .sign = FTR_UNSIGNED,
1520                 .field_pos = ID_AA64ISAR1_API_SHIFT,
1521                 .min_field_value = ID_AA64ISAR1_API_IMP_DEF,
1522                 .matches = has_cpuid_feature,
1523                 .cpu_enable = cpu_enable_address_auth,
1524         },
1525         {
1526                 .desc = "Generic authentication (architected algorithm)",
1527                 .capability = ARM64_HAS_GENERIC_AUTH_ARCH,
1528                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1529                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1530                 .sign = FTR_UNSIGNED,
1531                 .field_pos = ID_AA64ISAR1_GPA_SHIFT,
1532                 .min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
1533                 .matches = has_cpuid_feature,
1534         },
1535         {
1536                 .desc = "Generic authentication (IMP DEF algorithm)",
1537                 .capability = ARM64_HAS_GENERIC_AUTH_IMP_DEF,
1538                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,
1539                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1540                 .sign = FTR_UNSIGNED,
1541                 .field_pos = ID_AA64ISAR1_GPI_SHIFT,
1542                 .min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
1543                 .matches = has_cpuid_feature,
1544         },
1545 #endif /* CONFIG_ARM64_PTR_AUTH */
1546 #ifdef CONFIG_ARM64_PSEUDO_NMI
1547         {
1548                 /*
1549                  * Depends on having GICv3
1550                  */
1551                 .desc = "IRQ priority masking",
1552                 .capability = ARM64_HAS_IRQ_PRIO_MASKING,
1553                 .type = ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE,
1554                 .matches = can_use_gic_priorities,
1555                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1556                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
1557                 .sign = FTR_UNSIGNED,
1558                 .min_field_value = 1,
1559         },
1560 #endif
1561         {},
1562 };
1563
1564 #define HWCAP_CPUID_MATCH(reg, field, s, min_value)                             \
1565                 .matches = has_cpuid_feature,                                   \
1566                 .sys_reg = reg,                                                 \
1567                 .field_pos = field,                                             \
1568                 .sign = s,                                                      \
1569                 .min_field_value = min_value,
1570
1571 #define __HWCAP_CAP(name, cap_type, cap)                                        \
1572                 .desc = name,                                                   \
1573                 .type = ARM64_CPUCAP_SYSTEM_FEATURE,                            \
1574                 .hwcap_type = cap_type,                                         \
1575                 .hwcap = cap,                                                   \
1576
1577 #define HWCAP_CAP(reg, field, s, min_value, cap_type, cap)                      \
1578         {                                                                       \
1579                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1580                 HWCAP_CPUID_MATCH(reg, field, s, min_value)                     \
1581         }
1582
1583 #define HWCAP_MULTI_CAP(list, cap_type, cap)                                    \
1584         {                                                                       \
1585                 __HWCAP_CAP(#cap, cap_type, cap)                                \
1586                 .matches = cpucap_multi_entry_cap_matches,                      \
1587                 .match_list = list,                                             \
1588         }
1589
1590 #ifdef CONFIG_ARM64_PTR_AUTH
1591 static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
1592         {
1593                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
1594                                   FTR_UNSIGNED, ID_AA64ISAR1_APA_ARCHITECTED)
1595         },
1596         {
1597                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
1598                                   FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
1599         },
1600         {},
1601 };
1602
1603 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
1604         {
1605                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
1606                                   FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
1607         },
1608         {
1609                 HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
1610                                   FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
1611         },
1612         {},
1613 };
1614 #endif
1615
1616 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1617         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL),
1618         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES),
1619         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1),
1620         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2),
1621         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512),
1622         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32),
1623         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS),
1624         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM),
1625         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3),
1626         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3),
1627         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4),
1628         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP),
1629         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM),
1630         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM),
1631         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP),
1632         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP),
1633         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD),
1634         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDHP),
1635         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_DIT_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DIT),
1636         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_DCPOP),
1637         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_DCPODP),
1638         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_JSCVT),
1639         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FCMA),
1640         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_LRCPC),
1641         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ILRCPC),
1642         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_SB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SB),
1643         HWCAP_CAP(SYS_ID_AA64MMFR2_EL1, ID_AA64MMFR2_AT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_USCAT),
1644 #ifdef CONFIG_ARM64_SVE
1645         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, KERNEL_HWCAP_SVE),
1646         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SVEVER_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SVEVER_SVE2, CAP_HWCAP, KERNEL_HWCAP_SVE2),
1647         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES, CAP_HWCAP, KERNEL_HWCAP_SVEAES),
1648         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_AES_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_AES_PMULL, CAP_HWCAP, KERNEL_HWCAP_SVEPMULL),
1649         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_BITPERM_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_BITPERM, CAP_HWCAP, KERNEL_HWCAP_SVEBITPERM),
1650         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SHA3_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SHA3, CAP_HWCAP, KERNEL_HWCAP_SVESHA3),
1651         HWCAP_CAP(SYS_ID_AA64ZFR0_EL1, ID_AA64ZFR0_SM4_SHIFT, FTR_UNSIGNED, ID_AA64ZFR0_SM4, CAP_HWCAP, KERNEL_HWCAP_SVESM4),
1652 #endif
1653         HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_SSBS_SHIFT, FTR_UNSIGNED, ID_AA64PFR1_SSBS_PSTATE_INSNS, CAP_HWCAP, KERNEL_HWCAP_SSBS),
1654 #ifdef CONFIG_ARM64_PTR_AUTH
1655         HWCAP_MULTI_CAP(ptr_auth_hwcap_addr_matches, CAP_HWCAP, KERNEL_HWCAP_PACA),
1656         HWCAP_MULTI_CAP(ptr_auth_hwcap_gen_matches, CAP_HWCAP, KERNEL_HWCAP_PACG),
1657 #endif
1658         {},
1659 };
1660
1661 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1662 #ifdef CONFIG_COMPAT
1663         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1664         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1665         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1666         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1667         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1668 #endif
1669         {},
1670 };
1671
1672 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1673 {
1674         switch (cap->hwcap_type) {
1675         case CAP_HWCAP:
1676                 cpu_set_feature(cap->hwcap);
1677                 break;
1678 #ifdef CONFIG_COMPAT
1679         case CAP_COMPAT_HWCAP:
1680                 compat_elf_hwcap |= (u32)cap->hwcap;
1681                 break;
1682         case CAP_COMPAT_HWCAP2:
1683                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1684                 break;
1685 #endif
1686         default:
1687                 WARN_ON(1);
1688                 break;
1689         }
1690 }
1691
1692 /* Check if we have a particular HWCAP enabled */
1693 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1694 {
1695         bool rc;
1696
1697         switch (cap->hwcap_type) {
1698         case CAP_HWCAP:
1699                 rc = cpu_have_feature(cap->hwcap);
1700                 break;
1701 #ifdef CONFIG_COMPAT
1702         case CAP_COMPAT_HWCAP:
1703                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1704                 break;
1705         case CAP_COMPAT_HWCAP2:
1706                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1707                 break;
1708 #endif
1709         default:
1710                 WARN_ON(1);
1711                 rc = false;
1712         }
1713
1714         return rc;
1715 }
1716
1717 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1718 {
1719         /* We support emulation of accesses to CPU ID feature registers */
1720         cpu_set_named_feature(CPUID);
1721         for (; hwcaps->matches; hwcaps++)
1722                 if (hwcaps->matches(hwcaps, cpucap_default_scope(hwcaps)))
1723                         cap_set_elf_hwcap(hwcaps);
1724 }
1725
1726 static void update_cpu_capabilities(u16 scope_mask)
1727 {
1728         int i;
1729         const struct arm64_cpu_capabilities *caps;
1730
1731         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1732         for (i = 0; i < ARM64_NCAPS; i++) {
1733                 caps = cpu_hwcaps_ptrs[i];
1734                 if (!caps || !(caps->type & scope_mask) ||
1735                     cpus_have_cap(caps->capability) ||
1736                     !caps->matches(caps, cpucap_default_scope(caps)))
1737                         continue;
1738
1739                 if (caps->desc)
1740                         pr_info("detected: %s\n", caps->desc);
1741                 cpus_set_cap(caps->capability);
1742
1743                 if ((scope_mask & SCOPE_BOOT_CPU) && (caps->type & SCOPE_BOOT_CPU))
1744                         set_bit(caps->capability, boot_capabilities);
1745         }
1746 }
1747
1748 /*
1749  * Enable all the available capabilities on this CPU. The capabilities
1750  * with BOOT_CPU scope are handled separately and hence skipped here.
1751  */
1752 static int cpu_enable_non_boot_scope_capabilities(void *__unused)
1753 {
1754         int i;
1755         u16 non_boot_scope = SCOPE_ALL & ~SCOPE_BOOT_CPU;
1756
1757         for_each_available_cap(i) {
1758                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[i];
1759
1760                 if (WARN_ON(!cap))
1761                         continue;
1762
1763                 if (!(cap->type & non_boot_scope))
1764                         continue;
1765
1766                 if (cap->cpu_enable)
1767                         cap->cpu_enable(cap);
1768         }
1769         return 0;
1770 }
1771
1772 /*
1773  * Run through the enabled capabilities and enable() it on all active
1774  * CPUs
1775  */
1776 static void __init enable_cpu_capabilities(u16 scope_mask)
1777 {
1778         int i;
1779         const struct arm64_cpu_capabilities *caps;
1780         bool boot_scope;
1781
1782         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1783         boot_scope = !!(scope_mask & SCOPE_BOOT_CPU);
1784
1785         for (i = 0; i < ARM64_NCAPS; i++) {
1786                 unsigned int num;
1787
1788                 caps = cpu_hwcaps_ptrs[i];
1789                 if (!caps || !(caps->type & scope_mask))
1790                         continue;
1791                 num = caps->capability;
1792                 if (!cpus_have_cap(num))
1793                         continue;
1794
1795                 /* Ensure cpus_have_const_cap(num) works */
1796                 static_branch_enable(&cpu_hwcap_keys[num]);
1797
1798                 if (boot_scope && caps->cpu_enable)
1799                         /*
1800                          * Capabilities with SCOPE_BOOT_CPU scope are finalised
1801                          * before any secondary CPU boots. Thus, each secondary
1802                          * will enable the capability as appropriate via
1803                          * check_local_cpu_capabilities(). The only exception is
1804                          * the boot CPU, for which the capability must be
1805                          * enabled here. This approach avoids costly
1806                          * stop_machine() calls for this case.
1807                          */
1808                         caps->cpu_enable(caps);
1809         }
1810
1811         /*
1812          * For all non-boot scope capabilities, use stop_machine()
1813          * as it schedules the work allowing us to modify PSTATE,
1814          * instead of on_each_cpu() which uses an IPI, giving us a
1815          * PSTATE that disappears when we return.
1816          */
1817         if (!boot_scope)
1818                 stop_machine(cpu_enable_non_boot_scope_capabilities,
1819                              NULL, cpu_online_mask);
1820 }
1821
1822 /*
1823  * Run through the list of capabilities to check for conflicts.
1824  * If the system has already detected a capability, take necessary
1825  * action on this CPU.
1826  *
1827  * Returns "false" on conflicts.
1828  */
1829 static bool verify_local_cpu_caps(u16 scope_mask)
1830 {
1831         int i;
1832         bool cpu_has_cap, system_has_cap;
1833         const struct arm64_cpu_capabilities *caps;
1834
1835         scope_mask &= ARM64_CPUCAP_SCOPE_MASK;
1836
1837         for (i = 0; i < ARM64_NCAPS; i++) {
1838                 caps = cpu_hwcaps_ptrs[i];
1839                 if (!caps || !(caps->type & scope_mask))
1840                         continue;
1841
1842                 cpu_has_cap = caps->matches(caps, SCOPE_LOCAL_CPU);
1843                 system_has_cap = cpus_have_cap(caps->capability);
1844
1845                 if (system_has_cap) {
1846                         /*
1847                          * Check if the new CPU misses an advertised feature,
1848                          * which is not safe to miss.
1849                          */
1850                         if (!cpu_has_cap && !cpucap_late_cpu_optional(caps))
1851                                 break;
1852                         /*
1853                          * We have to issue cpu_enable() irrespective of
1854                          * whether the CPU has it or not, as it is enabeld
1855                          * system wide. It is upto the call back to take
1856                          * appropriate action on this CPU.
1857                          */
1858                         if (caps->cpu_enable)
1859                                 caps->cpu_enable(caps);
1860                 } else {
1861                         /*
1862                          * Check if the CPU has this capability if it isn't
1863                          * safe to have when the system doesn't.
1864                          */
1865                         if (cpu_has_cap && !cpucap_late_cpu_permitted(caps))
1866                                 break;
1867                 }
1868         }
1869
1870         if (i < ARM64_NCAPS) {
1871                 pr_crit("CPU%d: Detected conflict for capability %d (%s), System: %d, CPU: %d\n",
1872                         smp_processor_id(), caps->capability,
1873                         caps->desc, system_has_cap, cpu_has_cap);
1874                 return false;
1875         }
1876
1877         return true;
1878 }
1879
1880 /*
1881  * Check for CPU features that are used in early boot
1882  * based on the Boot CPU value.
1883  */
1884 static void check_early_cpu_features(void)
1885 {
1886         verify_cpu_asid_bits();
1887         /*
1888          * Early features are used by the kernel already. If there
1889          * is a conflict, we cannot proceed further.
1890          */
1891         if (!verify_local_cpu_caps(SCOPE_BOOT_CPU))
1892                 cpu_panic_kernel();
1893 }
1894
1895 static void
1896 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1897 {
1898
1899         for (; caps->matches; caps++)
1900                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1901                         pr_crit("CPU%d: missing HWCAP: %s\n",
1902                                         smp_processor_id(), caps->desc);
1903                         cpu_die_early();
1904                 }
1905 }
1906
1907 static void verify_sve_features(void)
1908 {
1909         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1910         u64 zcr = read_zcr_features();
1911
1912         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1913         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1914
1915         if (len < safe_len || sve_verify_vq_map()) {
1916                 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1917                         smp_processor_id());
1918                 cpu_die_early();
1919         }
1920
1921         /* Add checks on other ZCR bits here if necessary */
1922 }
1923
1924
1925 /*
1926  * Run through the enabled system capabilities and enable() it on this CPU.
1927  * The capabilities were decided based on the available CPUs at the boot time.
1928  * Any new CPU should match the system wide status of the capability. If the
1929  * new CPU doesn't have a capability which the system now has enabled, we
1930  * cannot do anything to fix it up and could cause unexpected failures. So
1931  * we park the CPU.
1932  */
1933 static void verify_local_cpu_capabilities(void)
1934 {
1935         /*
1936          * The capabilities with SCOPE_BOOT_CPU are checked from
1937          * check_early_cpu_features(), as they need to be verified
1938          * on all secondary CPUs.
1939          */
1940         if (!verify_local_cpu_caps(SCOPE_ALL & ~SCOPE_BOOT_CPU))
1941                 cpu_die_early();
1942
1943         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1944
1945         if (system_supports_32bit_el0())
1946                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1947
1948         if (system_supports_sve())
1949                 verify_sve_features();
1950 }
1951
1952 void check_local_cpu_capabilities(void)
1953 {
1954         /*
1955          * All secondary CPUs should conform to the early CPU features
1956          * in use by the kernel based on boot CPU.
1957          */
1958         check_early_cpu_features();
1959
1960         /*
1961          * If we haven't finalised the system capabilities, this CPU gets
1962          * a chance to update the errata work arounds and local features.
1963          * Otherwise, this CPU should verify that it has all the system
1964          * advertised capabilities.
1965          */
1966         if (!sys_caps_initialised)
1967                 update_cpu_capabilities(SCOPE_LOCAL_CPU);
1968         else
1969                 verify_local_cpu_capabilities();
1970 }
1971
1972 static void __init setup_boot_cpu_capabilities(void)
1973 {
1974         /* Detect capabilities with either SCOPE_BOOT_CPU or SCOPE_LOCAL_CPU */
1975         update_cpu_capabilities(SCOPE_BOOT_CPU | SCOPE_LOCAL_CPU);
1976         /* Enable the SCOPE_BOOT_CPU capabilities alone right away */
1977         enable_cpu_capabilities(SCOPE_BOOT_CPU);
1978 }
1979
1980 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1981 EXPORT_SYMBOL(arm64_const_caps_ready);
1982
1983 static void __init mark_const_caps_ready(void)
1984 {
1985         static_branch_enable(&arm64_const_caps_ready);
1986 }
1987
1988 bool this_cpu_has_cap(unsigned int n)
1989 {
1990         if (!WARN_ON(preemptible()) && n < ARM64_NCAPS) {
1991                 const struct arm64_cpu_capabilities *cap = cpu_hwcaps_ptrs[n];
1992
1993                 if (cap)
1994                         return cap->matches(cap, SCOPE_LOCAL_CPU);
1995         }
1996
1997         return false;
1998 }
1999
2000 void cpu_set_feature(unsigned int num)
2001 {
2002         WARN_ON(num >= MAX_CPU_FEATURES);
2003         elf_hwcap |= BIT(num);
2004 }
2005 EXPORT_SYMBOL_GPL(cpu_set_feature);
2006
2007 bool cpu_have_feature(unsigned int num)
2008 {
2009         WARN_ON(num >= MAX_CPU_FEATURES);
2010         return elf_hwcap & BIT(num);
2011 }
2012 EXPORT_SYMBOL_GPL(cpu_have_feature);
2013
2014 unsigned long cpu_get_elf_hwcap(void)
2015 {
2016         /*
2017          * We currently only populate the first 32 bits of AT_HWCAP. Please
2018          * note that for userspace compatibility we guarantee that bits 62
2019          * and 63 will always be returned as 0.
2020          */
2021         return lower_32_bits(elf_hwcap);
2022 }
2023
2024 unsigned long cpu_get_elf_hwcap2(void)
2025 {
2026         return upper_32_bits(elf_hwcap);
2027 }
2028
2029 static void __init setup_system_capabilities(void)
2030 {
2031         /*
2032          * We have finalised the system-wide safe feature
2033          * registers, finalise the capabilities that depend
2034          * on it. Also enable all the available capabilities,
2035          * that are not enabled already.
2036          */
2037         update_cpu_capabilities(SCOPE_SYSTEM);
2038         enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU);
2039 }
2040
2041 void __init setup_cpu_features(void)
2042 {
2043         u32 cwg;
2044
2045         setup_system_capabilities();
2046         mark_const_caps_ready();
2047         setup_elf_hwcaps(arm64_elf_hwcaps);
2048
2049         if (system_supports_32bit_el0())
2050                 setup_elf_hwcaps(compat_elf_hwcaps);
2051
2052         if (system_uses_ttbr0_pan())
2053                 pr_info("emulated: Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
2054
2055         sve_setup();
2056         minsigstksz_setup();
2057
2058         /* Advertise that we have computed the system capabilities */
2059         set_sys_caps_initialised();
2060
2061         /*
2062          * Check for sane CTR_EL0.CWG value.
2063          */
2064         cwg = cache_type_cwg();
2065         if (!cwg)
2066                 pr_warn("No Cache Writeback Granule information, assuming %d\n",
2067                         ARCH_DMA_MINALIGN);
2068 }
2069
2070 static bool __maybe_unused
2071 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
2072 {
2073         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
2074 }
2075
2076 static void __maybe_unused cpu_enable_cnp(struct arm64_cpu_capabilities const *cap)
2077 {
2078         cpu_replace_ttbr1(lm_alias(swapper_pg_dir));
2079 }
2080
2081 /*
2082  * We emulate only the following system register space.
2083  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
2084  * See Table C5-6 System instruction encodings for System register accesses,
2085  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
2086  */
2087 static inline bool __attribute_const__ is_emulated(u32 id)
2088 {
2089         return (sys_reg_Op0(id) == 0x3 &&
2090                 sys_reg_CRn(id) == 0x0 &&
2091                 sys_reg_Op1(id) == 0x0 &&
2092                 (sys_reg_CRm(id) == 0 ||
2093                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
2094 }
2095
2096 /*
2097  * With CRm == 0, reg should be one of :
2098  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
2099  */
2100 static inline int emulate_id_reg(u32 id, u64 *valp)
2101 {
2102         switch (id) {
2103         case SYS_MIDR_EL1:
2104                 *valp = read_cpuid_id();
2105                 break;
2106         case SYS_MPIDR_EL1:
2107                 *valp = SYS_MPIDR_SAFE_VAL;
2108                 break;
2109         case SYS_REVIDR_EL1:
2110                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
2111                 *valp = 0;
2112                 break;
2113         default:
2114                 return -EINVAL;
2115         }
2116
2117         return 0;
2118 }
2119
2120 static int emulate_sys_reg(u32 id, u64 *valp)
2121 {
2122         struct arm64_ftr_reg *regp;
2123
2124         if (!is_emulated(id))
2125                 return -EINVAL;
2126
2127         if (sys_reg_CRm(id) == 0)
2128                 return emulate_id_reg(id, valp);
2129
2130         regp = get_arm64_ftr_reg(id);
2131         if (regp)
2132                 *valp = arm64_ftr_reg_user_value(regp);
2133         else
2134                 /*
2135                  * The untracked registers are either IMPLEMENTATION DEFINED
2136                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
2137                  */
2138                 *valp = 0;
2139         return 0;
2140 }
2141
2142 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt)
2143 {
2144         int rc;
2145         u64 val;
2146
2147         rc = emulate_sys_reg(sys_reg, &val);
2148         if (!rc) {
2149                 pt_regs_write_reg(regs, rt, val);
2150                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
2151         }
2152         return rc;
2153 }
2154
2155 static int emulate_mrs(struct pt_regs *regs, u32 insn)
2156 {
2157         u32 sys_reg, rt;
2158
2159         /*
2160          * sys_reg values are defined as used in mrs/msr instruction.
2161          * shift the imm value to get the encoding.
2162          */
2163         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
2164         rt = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
2165         return do_emulate_mrs(regs, sys_reg, rt);
2166 }
2167
2168 static struct undef_hook mrs_hook = {
2169         .instr_mask = 0xfff00000,
2170         .instr_val  = 0xd5300000,
2171         .pstate_mask = PSR_AA32_MODE_MASK,
2172         .pstate_val = PSR_MODE_EL0t,
2173         .fn = emulate_mrs,
2174 };
2175
2176 static int __init enable_mrs_emulation(void)
2177 {
2178         register_undef_hook(&mrs_hook);
2179         return 0;
2180 }
2181
2182 core_initcall(enable_mrs_emulation);
2183
2184 ssize_t cpu_show_meltdown(struct device *dev, struct device_attribute *attr,
2185                           char *buf)
2186 {
2187         if (__meltdown_safe)
2188                 return sprintf(buf, "Not affected\n");
2189
2190         if (arm64_kernel_unmapped_at_el0())
2191                 return sprintf(buf, "Mitigation: PTI\n");
2192
2193         return sprintf(buf, "Vulnerable\n");
2194 }