arch/arm64/kernel/cpufeature.c

   1 /*
   2  * Contains CPU feature definitions
   3  *
   4  * Copyright (C) 2015 ARM Ltd.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #define pr_fmt(fmt) "CPU features: " fmt
  20
  21 #include <linux/bsearch.h>
  22 #include <linux/cpumask.h>
  23 #include <linux/sort.h>
  24 #include <linux/stop_machine.h>
  25 #include <linux/types.h>
  26 #include <linux/mm.h>
  27 #include <asm/cpu.h>
  28 #include <asm/cpufeature.h>
  29 #include <asm/cpu_ops.h>
  30 #include <asm/fpsimd.h>
  31 #include <asm/mmu_context.h>
  32 #include <asm/processor.h>
  33 #include <asm/sysreg.h>
  34 #include <asm/traps.h>
  35 #include <asm/virt.h>
  36
  37 unsigned long elf_hwcap __read_mostly;
  38 EXPORT_SYMBOL_GPL(elf_hwcap);
  39
  40 #ifdef CONFIG_COMPAT
  41 #define COMPAT_ELF_HWCAP_DEFAULT        \
  42                                 (COMPAT_HWCAP_HALF|COMPAT_HWCAP_THUMB|\
  43                                  COMPAT_HWCAP_FAST_MULT|COMPAT_HWCAP_EDSP|\
  44                                  COMPAT_HWCAP_TLS|COMPAT_HWCAP_VFP|\
  45                                  COMPAT_HWCAP_VFPv3|COMPAT_HWCAP_VFPv4|\
  46                                  COMPAT_HWCAP_NEON|COMPAT_HWCAP_IDIV|\
  47                                  COMPAT_HWCAP_LPAE)
  48 unsigned int compat_elf_hwcap __read_mostly = COMPAT_ELF_HWCAP_DEFAULT;
  49 unsigned int compat_elf_hwcap2 __read_mostly;
  50 #endif
  51
  52 DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
  53 EXPORT_SYMBOL(cpu_hwcaps);
  54
  55 /*
  56  * Flag to indicate if we have computed the system wide
  57  * capabilities based on the boot time active CPUs. This
  58  * will be used to determine if a new booting CPU should
  59  * go through the verification process to make sure that it
  60  * supports the system capabilities, without using a hotplug
  61  * notifier.
  62  */
  63 static bool sys_caps_initialised;
  64
  65 static inline void set_sys_caps_initialised(void)
  66 {
  67         sys_caps_initialised = true;
  68 }
  69
  70 static int dump_cpu_hwcaps(struct notifier_block *self, unsigned long v, void *p)
  71 {
  72         /* file-wide pr_fmt adds "CPU features: " prefix */
  73         pr_emerg("0x%*pb\n", ARM64_NCAPS, &cpu_hwcaps);
  74         return 0;
  75 }
  76
  77 static struct notifier_block cpu_hwcaps_notifier = {
  78         .notifier_call = dump_cpu_hwcaps
  79 };
  80
  81 static int __init register_cpu_hwcaps_dumper(void)
  82 {
  83         atomic_notifier_chain_register(&panic_notifier_list,
  84                                        &cpu_hwcaps_notifier);
  85         return 0;
  86 }
  87 __initcall(register_cpu_hwcaps_dumper);
  88
  89 DEFINE_STATIC_KEY_ARRAY_FALSE(cpu_hwcap_keys, ARM64_NCAPS);
  90 EXPORT_SYMBOL(cpu_hwcap_keys);
  91
  92 #define __ARM64_FTR_BITS(SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
  93         {                                               \
  94                 .sign = SIGNED,                         \
  95                 .visible = VISIBLE,                     \
  96                 .strict = STRICT,                       \
  97                 .type = TYPE,                           \
  98                 .shift = SHIFT,                         \
  99                 .width = WIDTH,                         \
 100                 .safe_val = SAFE_VAL,                   \
 101         }
 102
 103 /* Define a feature with unsigned values */
 104 #define ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 105         __ARM64_FTR_BITS(FTR_UNSIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 106
 107 /* Define a feature with a signed value */
 108 #define S_ARM64_FTR_BITS(VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL) \
 109         __ARM64_FTR_BITS(FTR_SIGNED, VISIBLE, STRICT, TYPE, SHIFT, WIDTH, SAFE_VAL)
 110
 111 #define ARM64_FTR_END                                   \
 112         {                                               \
 113                 .width = 0,                             \
 114         }
 115
 116 /* meta feature for alternatives */
 117 static bool __maybe_unused
 118 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused);
 119
 120
 121 /*
 122  * NOTE: Any changes to the visibility of features should be kept in
 123  * sync with the documentation of the CPU feature register ABI.
 124  */
 125 static const struct arm64_ftr_bits ftr_id_aa64isar0[] = {
 126         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0),
 127         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0),
 128         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0),
 129         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0),
 130         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0),
 131         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0),
 132         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0),
 133         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0),
 134         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0),
 135         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0),
 136         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0),
 137         ARM64_FTR_END,
 138 };
 139
 140 static const struct arm64_ftr_bits ftr_id_aa64isar1[] = {
 141         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_LRCPC_SHIFT, 4, 0),
 142         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_FCMA_SHIFT, 4, 0),
 143         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_JSCVT_SHIFT, 4, 0),
 144         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR1_DPB_SHIFT, 4, 0),
 145         ARM64_FTR_END,
 146 };
 147
 148 static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
 149         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
 150         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
 151         ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
 152                                    FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
 153         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
 154         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_GIC_SHIFT, 4, 0),
 155         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_ASIMD_SHIFT, 4, ID_AA64PFR0_ASIMD_NI),
 156         S_ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_FP_SHIFT, 4, ID_AA64PFR0_FP_NI),
 157         /* Linux doesn't care about the EL3 */
 158         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0),
 159         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0),
 160         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY),
 161         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY),
 162         ARM64_FTR_END,
 163 };
 164
 165 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
 166         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
 167         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
 168         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
 169         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
 170         /* Linux shouldn't care about secure memory */
 171         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
 172         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
 173         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
 174         /*
 175          * Differing PARange is fine as long as all peripherals and memory are mapped
 176          * within the minimum PARange of all CPUs
 177          */
 178         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
 179         ARM64_FTR_END,
 180 };
 181
 182 static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
 183         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_PAN_SHIFT, 4, 0),
 184         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_LOR_SHIFT, 4, 0),
 185         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HPD_SHIFT, 4, 0),
 186         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VHE_SHIFT, 4, 0),
 187         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_VMIDBITS_SHIFT, 4, 0),
 188         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR1_HADBS_SHIFT, 4, 0),
 189         ARM64_FTR_END,
 190 };
 191
 192 static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
 193         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
 194         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_IESB_SHIFT, 4, 0),
 195         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LSM_SHIFT, 4, 0),
 196         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_UAO_SHIFT, 4, 0),
 197         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_CNP_SHIFT, 4, 0),
 198         ARM64_FTR_END,
 199 };
 200
 201 static const struct arm64_ftr_bits ftr_ctr[] = {
 202         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 31, 1, 1),           /* RES1 */
 203         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 29, 1, 1),      /* DIC */
 204         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 28, 1, 1),      /* IDC */
 205         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 24, 4, 0),     /* CWG */
 206         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_HIGHER_SAFE, 20, 4, 0),     /* ERG */
 207         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 1),      /* DminLine */
 208         /*
 209          * Linux can handle differing I-cache policies. Userspace JITs will
 210          * make use of *minLine.
 211          * If we have differing I-cache policies, report it as the weakest - VIPT.
 212          */
 213         ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_EXACT, 14, 2, ICACHE_POLICY_VIPT),       /* L1Ip */
 214         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* IminLine */
 215         ARM64_FTR_END,
 216 };
 217
 218 struct arm64_ftr_reg arm64_ftr_reg_ctrel0 = {
 219         .name           = "SYS_CTR_EL0",
 220         .ftr_bits       = ftr_ctr
 221 };
 222
 223 static const struct arm64_ftr_bits ftr_id_mmfr0[] = {
 224         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0xf),   /* InnerShr */
 225         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),       /* FCSE */
 226         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, 20, 4, 0),    /* AuxReg */
 227         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),       /* TCM */
 228         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),       /* ShareLvl */
 229         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0xf),    /* OuterShr */
 230         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* PMSA */
 231         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),        /* VMSA */
 232         ARM64_FTR_END,
 233 };
 234
 235 static const struct arm64_ftr_bits ftr_id_aa64dfr0[] = {
 236         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 36, 28, 0),
 237         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64DFR0_PMSVER_SHIFT, 4, 0),
 238         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_CTX_CMPS_SHIFT, 4, 0),
 239         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_WRPS_SHIFT, 4, 0),
 240         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64DFR0_BRPS_SHIFT, 4, 0),
 241         /*
 242          * We can instantiate multiple PMU instances with different levels
 243          * of support.
 244          */
 245         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64DFR0_PMUVER_SHIFT, 4, 0),
 246         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_TRACEVER_SHIFT, 4, 0),
 247         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, ID_AA64DFR0_DEBUGVER_SHIFT, 4, 0x6),
 248         ARM64_FTR_END,
 249 };
 250
 251 static const struct arm64_ftr_bits ftr_mvfr2[] = {
 252         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* FPMisc */
 253         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* SIMDMisc */
 254         ARM64_FTR_END,
 255 };
 256
 257 static const struct arm64_ftr_bits ftr_dczid[] = {
 258         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, 4, 1, 1),            /* DZP */
 259         ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),       /* BS */
 260         ARM64_FTR_END,
 261 };
 262
 263
 264 static const struct arm64_ftr_bits ftr_id_isar5[] = {
 265         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_RDM_SHIFT, 4, 0),
 266         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_CRC32_SHIFT, 4, 0),
 267         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA2_SHIFT, 4, 0),
 268         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SHA1_SHIFT, 4, 0),
 269         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_AES_SHIFT, 4, 0),
 270         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_ISAR5_SEVL_SHIFT, 4, 0),
 271         ARM64_FTR_END,
 272 };
 273
 274 static const struct arm64_ftr_bits ftr_id_mmfr4[] = {
 275         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),        /* ac2 */
 276         ARM64_FTR_END,
 277 };
 278
 279 static const struct arm64_ftr_bits ftr_id_pfr0[] = {
 280         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),               /* State3 */
 281         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),                /* State2 */
 282         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),                /* State1 */
 283         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),                /* State0 */
 284         ARM64_FTR_END,
 285 };
 286
 287 static const struct arm64_ftr_bits ftr_id_dfr0[] = {
 288         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 289         S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0xf),   /* PerfMon */
 290         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 291         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 292         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 293         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 294         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 295         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 296         ARM64_FTR_END,
 297 };
 298
 299 static const struct arm64_ftr_bits ftr_zcr[] = {
 300         ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE,
 301                 ZCR_ELx_LEN_SHIFT, ZCR_ELx_LEN_SIZE, 0),        /* LEN */
 302         ARM64_FTR_END,
 303 };
 304
 305 /*
 306  * Common ftr bits for a 32bit register with all hidden, strict
 307  * attributes, with 4bit feature fields and a default safe value of
 308  * 0. Covers the following 32bit registers:
 309  * id_isar[0-4], id_mmfr[1-3], id_pfr1, mvfr[0-1]
 310  */
 311 static const struct arm64_ftr_bits ftr_generic_32bits[] = {
 312         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 28, 4, 0),
 313         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 24, 4, 0),
 314         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 20, 4, 0),
 315         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 16, 4, 0),
 316         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 12, 4, 0),
 317         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 8, 4, 0),
 318         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 4, 4, 0),
 319         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 0, 4, 0),
 320         ARM64_FTR_END,
 321 };
 322
 323 /* Table for a single 32bit feature value */
 324 static const struct arm64_ftr_bits ftr_single32[] = {
 325         ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_EXACT, 0, 32, 0),
 326         ARM64_FTR_END,
 327 };
 328
 329 static const struct arm64_ftr_bits ftr_raz[] = {
 330         ARM64_FTR_END,
 331 };
 332
 333 #define ARM64_FTR_REG(id, table) {              \
 334         .sys_id = id,                           \
 335         .reg =  &(struct arm64_ftr_reg){        \
 336                 .name = #id,                    \
 337                 .ftr_bits = &((table)[0]),      \
 338         }}
 339
 340 static const struct __ftr_reg_entry {
 341         u32                     sys_id;
 342         struct arm64_ftr_reg    *reg;
 343 } arm64_ftr_regs[] = {
 344
 345         /* Op1 = 0, CRn = 0, CRm = 1 */
 346         ARM64_FTR_REG(SYS_ID_PFR0_EL1, ftr_id_pfr0),
 347         ARM64_FTR_REG(SYS_ID_PFR1_EL1, ftr_generic_32bits),
 348         ARM64_FTR_REG(SYS_ID_DFR0_EL1, ftr_id_dfr0),
 349         ARM64_FTR_REG(SYS_ID_MMFR0_EL1, ftr_id_mmfr0),
 350         ARM64_FTR_REG(SYS_ID_MMFR1_EL1, ftr_generic_32bits),
 351         ARM64_FTR_REG(SYS_ID_MMFR2_EL1, ftr_generic_32bits),
 352         ARM64_FTR_REG(SYS_ID_MMFR3_EL1, ftr_generic_32bits),
 353
 354         /* Op1 = 0, CRn = 0, CRm = 2 */
 355         ARM64_FTR_REG(SYS_ID_ISAR0_EL1, ftr_generic_32bits),
 356         ARM64_FTR_REG(SYS_ID_ISAR1_EL1, ftr_generic_32bits),
 357         ARM64_FTR_REG(SYS_ID_ISAR2_EL1, ftr_generic_32bits),
 358         ARM64_FTR_REG(SYS_ID_ISAR3_EL1, ftr_generic_32bits),
 359         ARM64_FTR_REG(SYS_ID_ISAR4_EL1, ftr_generic_32bits),
 360         ARM64_FTR_REG(SYS_ID_ISAR5_EL1, ftr_id_isar5),
 361         ARM64_FTR_REG(SYS_ID_MMFR4_EL1, ftr_id_mmfr4),
 362
 363         /* Op1 = 0, CRn = 0, CRm = 3 */
 364         ARM64_FTR_REG(SYS_MVFR0_EL1, ftr_generic_32bits),
 365         ARM64_FTR_REG(SYS_MVFR1_EL1, ftr_generic_32bits),
 366         ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
 367
 368         /* Op1 = 0, CRn = 0, CRm = 4 */
 369         ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
 370         ARM64_FTR_REG(SYS_ID_AA64PFR1_EL1, ftr_raz),
 371         ARM64_FTR_REG(SYS_ID_AA64ZFR0_EL1, ftr_raz),
 372
 373         /* Op1 = 0, CRn = 0, CRm = 5 */
 374         ARM64_FTR_REG(SYS_ID_AA64DFR0_EL1, ftr_id_aa64dfr0),
 375         ARM64_FTR_REG(SYS_ID_AA64DFR1_EL1, ftr_raz),
 376
 377         /* Op1 = 0, CRn = 0, CRm = 6 */
 378         ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
 379         ARM64_FTR_REG(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1),
 380
 381         /* Op1 = 0, CRn = 0, CRm = 7 */
 382         ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
 383         ARM64_FTR_REG(SYS_ID_AA64MMFR1_EL1, ftr_id_aa64mmfr1),
 384         ARM64_FTR_REG(SYS_ID_AA64MMFR2_EL1, ftr_id_aa64mmfr2),
 385
 386         /* Op1 = 0, CRn = 1, CRm = 2 */
 387         ARM64_FTR_REG(SYS_ZCR_EL1, ftr_zcr),
 388
 389         /* Op1 = 3, CRn = 0, CRm = 0 */
 390         { SYS_CTR_EL0, &arm64_ftr_reg_ctrel0 },
 391         ARM64_FTR_REG(SYS_DCZID_EL0, ftr_dczid),
 392
 393         /* Op1 = 3, CRn = 14, CRm = 0 */
 394         ARM64_FTR_REG(SYS_CNTFRQ_EL0, ftr_single32),
 395 };
 396
 397 static int search_cmp_ftr_reg(const void *id, const void *regp)
 398 {
 399         return (int)(unsigned long)id - (int)((const struct __ftr_reg_entry *)regp)->sys_id;
 400 }
 401
 402 /*
 403  * get_arm64_ftr_reg - Lookup a feature register entry using its
 404  * sys_reg() encoding. With the array arm64_ftr_regs sorted in the
 405  * ascending order of sys_id , we use binary search to find a matching
 406  * entry.
 407  *
 408  * returns - Upon success,  matching ftr_reg entry for id.
 409  *         - NULL on failure. It is upto the caller to decide
 410  *           the impact of a failure.
 411  */
 412 static struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id)
 413 {
 414         const struct __ftr_reg_entry *ret;
 415
 416         ret = bsearch((const void *)(unsigned long)sys_id,
 417                         arm64_ftr_regs,
 418                         ARRAY_SIZE(arm64_ftr_regs),
 419                         sizeof(arm64_ftr_regs[0]),
 420                         search_cmp_ftr_reg);
 421         if (ret)
 422                 return ret->reg;
 423         return NULL;
 424 }
 425
 426 static u64 arm64_ftr_set_value(const struct arm64_ftr_bits *ftrp, s64 reg,
 427                                s64 ftr_val)
 428 {
 429         u64 mask = arm64_ftr_mask(ftrp);
 430
 431         reg &= ~mask;
 432         reg |= (ftr_val << ftrp->shift) & mask;
 433         return reg;
 434 }
 435
 436 static s64 arm64_ftr_safe_value(const struct arm64_ftr_bits *ftrp, s64 new,
 437                                 s64 cur)
 438 {
 439         s64 ret = 0;
 440
 441         switch (ftrp->type) {
 442         case FTR_EXACT:
 443                 ret = ftrp->safe_val;
 444                 break;
 445         case FTR_LOWER_SAFE:
 446                 ret = new < cur ? new : cur;
 447                 break;
 448         case FTR_HIGHER_SAFE:
 449                 ret = new > cur ? new : cur;
 450                 break;
 451         default:
 452                 BUG();
 453         }
 454
 455         return ret;
 456 }
 457
 458 static void __init sort_ftr_regs(void)
 459 {
 460         int i;
 461
 462         /* Check that the array is sorted so that we can do the binary search */
 463         for (i = 1; i < ARRAY_SIZE(arm64_ftr_regs); i++)
 464                 BUG_ON(arm64_ftr_regs[i].sys_id < arm64_ftr_regs[i - 1].sys_id);
 465 }
 466
 467 /*
 468  * Initialise the CPU feature register from Boot CPU values.
 469  * Also initiliases the strict_mask for the register.
 470  * Any bits that are not covered by an arm64_ftr_bits entry are considered
 471  * RES0 for the system-wide value, and must strictly match.
 472  */
 473 static void __init init_cpu_ftr_reg(u32 sys_reg, u64 new)
 474 {
 475         u64 val = 0;
 476         u64 strict_mask = ~0x0ULL;
 477         u64 user_mask = 0;
 478         u64 valid_mask = 0;
 479
 480         const struct arm64_ftr_bits *ftrp;
 481         struct arm64_ftr_reg *reg = get_arm64_ftr_reg(sys_reg);
 482
 483         BUG_ON(!reg);
 484
 485         for (ftrp  = reg->ftr_bits; ftrp->width; ftrp++) {
 486                 u64 ftr_mask = arm64_ftr_mask(ftrp);
 487                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 488
 489                 val = arm64_ftr_set_value(ftrp, val, ftr_new);
 490
 491                 valid_mask |= ftr_mask;
 492                 if (!ftrp->strict)
 493                         strict_mask &= ~ftr_mask;
 494                 if (ftrp->visible)
 495                         user_mask |= ftr_mask;
 496                 else
 497                         reg->user_val = arm64_ftr_set_value(ftrp,
 498                                                             reg->user_val,
 499                                                             ftrp->safe_val);
 500         }
 501
 502         val &= valid_mask;
 503
 504         reg->sys_val = val;
 505         reg->strict_mask = strict_mask;
 506         reg->user_mask = user_mask;
 507 }
 508
 509 void __init init_cpu_features(struct cpuinfo_arm64 *info)
 510 {
 511         /* Before we start using the tables, make sure it is sorted */
 512         sort_ftr_regs();
 513
 514         init_cpu_ftr_reg(SYS_CTR_EL0, info->reg_ctr);
 515         init_cpu_ftr_reg(SYS_DCZID_EL0, info->reg_dczid);
 516         init_cpu_ftr_reg(SYS_CNTFRQ_EL0, info->reg_cntfrq);
 517         init_cpu_ftr_reg(SYS_ID_AA64DFR0_EL1, info->reg_id_aa64dfr0);
 518         init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
 519         init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
 520         init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
 521         init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
 522         init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
 523         init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
 524         init_cpu_ftr_reg(SYS_ID_AA64PFR0_EL1, info->reg_id_aa64pfr0);
 525         init_cpu_ftr_reg(SYS_ID_AA64PFR1_EL1, info->reg_id_aa64pfr1);
 526         init_cpu_ftr_reg(SYS_ID_AA64ZFR0_EL1, info->reg_id_aa64zfr0);
 527
 528         if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 529                 init_cpu_ftr_reg(SYS_ID_DFR0_EL1, info->reg_id_dfr0);
 530                 init_cpu_ftr_reg(SYS_ID_ISAR0_EL1, info->reg_id_isar0);
 531                 init_cpu_ftr_reg(SYS_ID_ISAR1_EL1, info->reg_id_isar1);
 532                 init_cpu_ftr_reg(SYS_ID_ISAR2_EL1, info->reg_id_isar2);
 533                 init_cpu_ftr_reg(SYS_ID_ISAR3_EL1, info->reg_id_isar3);
 534                 init_cpu_ftr_reg(SYS_ID_ISAR4_EL1, info->reg_id_isar4);
 535                 init_cpu_ftr_reg(SYS_ID_ISAR5_EL1, info->reg_id_isar5);
 536                 init_cpu_ftr_reg(SYS_ID_MMFR0_EL1, info->reg_id_mmfr0);
 537                 init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
 538                 init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
 539                 init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
 540                 init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
 541                 init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
 542                 init_cpu_ftr_reg(SYS_MVFR0_EL1, info->reg_mvfr0);
 543                 init_cpu_ftr_reg(SYS_MVFR1_EL1, info->reg_mvfr1);
 544                 init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2);
 545         }
 546
 547         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 548                 init_cpu_ftr_reg(SYS_ZCR_EL1, info->reg_zcr);
 549                 sve_init_vq_map();
 550         }
 551 }
 552
 553 static void update_cpu_ftr_reg(struct arm64_ftr_reg *reg, u64 new)
 554 {
 555         const struct arm64_ftr_bits *ftrp;
 556
 557         for (ftrp = reg->ftr_bits; ftrp->width; ftrp++) {
 558                 s64 ftr_cur = arm64_ftr_value(ftrp, reg->sys_val);
 559                 s64 ftr_new = arm64_ftr_value(ftrp, new);
 560
 561                 if (ftr_cur == ftr_new)
 562                         continue;
 563                 /* Find a safe value */
 564                 ftr_new = arm64_ftr_safe_value(ftrp, ftr_new, ftr_cur);
 565                 reg->sys_val = arm64_ftr_set_value(ftrp, reg->sys_val, ftr_new);
 566         }
 567
 568 }
 569
 570 static int check_update_ftr_reg(u32 sys_id, int cpu, u64 val, u64 boot)
 571 {
 572         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(sys_id);
 573
 574         BUG_ON(!regp);
 575         update_cpu_ftr_reg(regp, val);
 576         if ((boot & regp->strict_mask) == (val & regp->strict_mask))
 577                 return 0;
 578         pr_warn("SANITY CHECK: Unexpected variation in %s. Boot CPU: %#016llx, CPU%d: %#016llx\n",
 579                         regp->name, boot, cpu, val);
 580         return 1;
 581 }
 582
 583 /*
 584  * Update system wide CPU feature registers with the values from a
 585  * non-boot CPU. Also performs SANITY checks to make sure that there
 586  * aren't any insane variations from that of the boot CPU.
 587  */
 588 void update_cpu_features(int cpu,
 589                          struct cpuinfo_arm64 *info,
 590                          struct cpuinfo_arm64 *boot)
 591 {
 592         int taint = 0;
 593
 594         /*
 595          * The kernel can handle differing I-cache policies, but otherwise
 596          * caches should look identical. Userspace JITs will make use of
 597          * *minLine.
 598          */
 599         taint |= check_update_ftr_reg(SYS_CTR_EL0, cpu,
 600                                       info->reg_ctr, boot->reg_ctr);
 601
 602         /*
 603          * Userspace may perform DC ZVA instructions. Mismatched block sizes
 604          * could result in too much or too little memory being zeroed if a
 605          * process is preempted and migrated between CPUs.
 606          */
 607         taint |= check_update_ftr_reg(SYS_DCZID_EL0, cpu,
 608                                       info->reg_dczid, boot->reg_dczid);
 609
 610         /* If different, timekeeping will be broken (especially with KVM) */
 611         taint |= check_update_ftr_reg(SYS_CNTFRQ_EL0, cpu,
 612                                       info->reg_cntfrq, boot->reg_cntfrq);
 613
 614         /*
 615          * The kernel uses self-hosted debug features and expects CPUs to
 616          * support identical debug features. We presently need CTX_CMPs, WRPs,
 617          * and BRPs to be identical.
 618          * ID_AA64DFR1 is currently RES0.
 619          */
 620         taint |= check_update_ftr_reg(SYS_ID_AA64DFR0_EL1, cpu,
 621                                       info->reg_id_aa64dfr0, boot->reg_id_aa64dfr0);
 622         taint |= check_update_ftr_reg(SYS_ID_AA64DFR1_EL1, cpu,
 623                                       info->reg_id_aa64dfr1, boot->reg_id_aa64dfr1);
 624         /*
 625          * Even in big.LITTLE, processors should be identical instruction-set
 626          * wise.
 627          */
 628         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR0_EL1, cpu,
 629                                       info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
 630         taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
 631                                       info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
 632
 633         /*
 634          * Differing PARange support is fine as long as all peripherals and
 635          * memory are mapped within the minimum PARange of all CPUs.
 636          * Linux should not care about secure memory.
 637          */
 638         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR0_EL1, cpu,
 639                                       info->reg_id_aa64mmfr0, boot->reg_id_aa64mmfr0);
 640         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR1_EL1, cpu,
 641                                       info->reg_id_aa64mmfr1, boot->reg_id_aa64mmfr1);
 642         taint |= check_update_ftr_reg(SYS_ID_AA64MMFR2_EL1, cpu,
 643                                       info->reg_id_aa64mmfr2, boot->reg_id_aa64mmfr2);
 644
 645         /*
 646          * EL3 is not our concern.
 647          * ID_AA64PFR1 is currently RES0.
 648          */
 649         taint |= check_update_ftr_reg(SYS_ID_AA64PFR0_EL1, cpu,
 650                                       info->reg_id_aa64pfr0, boot->reg_id_aa64pfr0);
 651         taint |= check_update_ftr_reg(SYS_ID_AA64PFR1_EL1, cpu,
 652                                       info->reg_id_aa64pfr1, boot->reg_id_aa64pfr1);
 653
 654         taint |= check_update_ftr_reg(SYS_ID_AA64ZFR0_EL1, cpu,
 655                                       info->reg_id_aa64zfr0, boot->reg_id_aa64zfr0);
 656
 657         /*
 658          * If we have AArch32, we care about 32-bit features for compat.
 659          * If the system doesn't support AArch32, don't update them.
 660          */
 661         if (id_aa64pfr0_32bit_el0(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 662                 id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
 663
 664                 taint |= check_update_ftr_reg(SYS_ID_DFR0_EL1, cpu,
 665                                         info->reg_id_dfr0, boot->reg_id_dfr0);
 666                 taint |= check_update_ftr_reg(SYS_ID_ISAR0_EL1, cpu,
 667                                         info->reg_id_isar0, boot->reg_id_isar0);
 668                 taint |= check_update_ftr_reg(SYS_ID_ISAR1_EL1, cpu,
 669                                         info->reg_id_isar1, boot->reg_id_isar1);
 670                 taint |= check_update_ftr_reg(SYS_ID_ISAR2_EL1, cpu,
 671                                         info->reg_id_isar2, boot->reg_id_isar2);
 672                 taint |= check_update_ftr_reg(SYS_ID_ISAR3_EL1, cpu,
 673                                         info->reg_id_isar3, boot->reg_id_isar3);
 674                 taint |= check_update_ftr_reg(SYS_ID_ISAR4_EL1, cpu,
 675                                         info->reg_id_isar4, boot->reg_id_isar4);
 676                 taint |= check_update_ftr_reg(SYS_ID_ISAR5_EL1, cpu,
 677                                         info->reg_id_isar5, boot->reg_id_isar5);
 678
 679                 /*
 680                  * Regardless of the value of the AuxReg field, the AIFSR, ADFSR, and
 681                  * ACTLR formats could differ across CPUs and therefore would have to
 682                  * be trapped for virtualization anyway.
 683                  */
 684                 taint |= check_update_ftr_reg(SYS_ID_MMFR0_EL1, cpu,
 685                                         info->reg_id_mmfr0, boot->reg_id_mmfr0);
 686                 taint |= check_update_ftr_reg(SYS_ID_MMFR1_EL1, cpu,
 687                                         info->reg_id_mmfr1, boot->reg_id_mmfr1);
 688                 taint |= check_update_ftr_reg(SYS_ID_MMFR2_EL1, cpu,
 689                                         info->reg_id_mmfr2, boot->reg_id_mmfr2);
 690                 taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
 691                                         info->reg_id_mmfr3, boot->reg_id_mmfr3);
 692                 taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
 693                                         info->reg_id_pfr0, boot->reg_id_pfr0);
 694                 taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
 695                                         info->reg_id_pfr1, boot->reg_id_pfr1);
 696                 taint |= check_update_ftr_reg(SYS_MVFR0_EL1, cpu,
 697                                         info->reg_mvfr0, boot->reg_mvfr0);
 698                 taint |= check_update_ftr_reg(SYS_MVFR1_EL1, cpu,
 699                                         info->reg_mvfr1, boot->reg_mvfr1);
 700                 taint |= check_update_ftr_reg(SYS_MVFR2_EL1, cpu,
 701                                         info->reg_mvfr2, boot->reg_mvfr2);
 702         }
 703
 704         if (id_aa64pfr0_sve(info->reg_id_aa64pfr0)) {
 705                 taint |= check_update_ftr_reg(SYS_ZCR_EL1, cpu,
 706                                         info->reg_zcr, boot->reg_zcr);
 707
 708                 /* Probe vector lengths, unless we already gave up on SVE */
 709                 if (id_aa64pfr0_sve(read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1)) &&
 710                     !sys_caps_initialised)
 711                         sve_update_vq_map();
 712         }
 713
 714         /*
 715          * Mismatched CPU features are a recipe for disaster. Don't even
 716          * pretend to support them.
 717          */
 718         if (taint) {
 719                 pr_warn_once("Unsupported CPU feature variation detected.\n");
 720                 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
 721         }
 722 }
 723
 724 u64 read_sanitised_ftr_reg(u32 id)
 725 {
 726         struct arm64_ftr_reg *regp = get_arm64_ftr_reg(id);
 727
 728         /* We shouldn't get a request for an unsupported register */
 729         BUG_ON(!regp);
 730         return regp->sys_val;
 731 }
 732
 733 #define read_sysreg_case(r)     \
 734         case r:         return read_sysreg_s(r)
 735
 736 /*
 737  * __read_sysreg_by_encoding() - Used by a STARTING cpu before cpuinfo is populated.
 738  * Read the system register on the current CPU
 739  */
 740 static u64 __read_sysreg_by_encoding(u32 sys_id)
 741 {
 742         switch (sys_id) {
 743         read_sysreg_case(SYS_ID_PFR0_EL1);
 744         read_sysreg_case(SYS_ID_PFR1_EL1);
 745         read_sysreg_case(SYS_ID_DFR0_EL1);
 746         read_sysreg_case(SYS_ID_MMFR0_EL1);
 747         read_sysreg_case(SYS_ID_MMFR1_EL1);
 748         read_sysreg_case(SYS_ID_MMFR2_EL1);
 749         read_sysreg_case(SYS_ID_MMFR3_EL1);
 750         read_sysreg_case(SYS_ID_ISAR0_EL1);
 751         read_sysreg_case(SYS_ID_ISAR1_EL1);
 752         read_sysreg_case(SYS_ID_ISAR2_EL1);
 753         read_sysreg_case(SYS_ID_ISAR3_EL1);
 754         read_sysreg_case(SYS_ID_ISAR4_EL1);
 755         read_sysreg_case(SYS_ID_ISAR5_EL1);
 756         read_sysreg_case(SYS_MVFR0_EL1);
 757         read_sysreg_case(SYS_MVFR1_EL1);
 758         read_sysreg_case(SYS_MVFR2_EL1);
 759
 760         read_sysreg_case(SYS_ID_AA64PFR0_EL1);
 761         read_sysreg_case(SYS_ID_AA64PFR1_EL1);
 762         read_sysreg_case(SYS_ID_AA64DFR0_EL1);
 763         read_sysreg_case(SYS_ID_AA64DFR1_EL1);
 764         read_sysreg_case(SYS_ID_AA64MMFR0_EL1);
 765         read_sysreg_case(SYS_ID_AA64MMFR1_EL1);
 766         read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
 767         read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
 768         read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
 769
 770         read_sysreg_case(SYS_CNTFRQ_EL0);
 771         read_sysreg_case(SYS_CTR_EL0);
 772         read_sysreg_case(SYS_DCZID_EL0);
 773
 774         default:
 775                 BUG();
 776                 return 0;
 777         }
 778 }
 779
 780 #include <linux/irqchip/arm-gic-v3.h>
 781
 782 static bool
 783 feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
 784 {
 785         int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
 786
 787         return val >= entry->min_field_value;
 788 }
 789
 790 static bool
 791 has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope)
 792 {
 793         u64 val;
 794
 795         WARN_ON(scope == SCOPE_LOCAL_CPU && preemptible());
 796         if (scope == SCOPE_SYSTEM)
 797                 val = read_sanitised_ftr_reg(entry->sys_reg);
 798         else
 799                 val = __read_sysreg_by_encoding(entry->sys_reg);
 800
 801         return feature_matches(val, entry);
 802 }
 803
 804 static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope)
 805 {
 806         bool has_sre;
 807
 808         if (!has_cpuid_feature(entry, scope))
 809                 return false;
 810
 811         has_sre = gic_enable_sre();
 812         if (!has_sre)
 813                 pr_warn_once("%s present but disabled by higher exception level\n",
 814                              entry->desc);
 815
 816         return has_sre;
 817 }
 818
 819 static bool has_no_hw_prefetch(const struct arm64_cpu_capabilities *entry, int __unused)
 820 {
 821         u32 midr = read_cpuid_id();
 822
 823         /* Cavium ThunderX pass 1.x and 2.x */
 824         return MIDR_IS_CPU_MODEL_RANGE(midr, MIDR_THUNDERX,
 825                 MIDR_CPU_VAR_REV(0, 0),
 826                 MIDR_CPU_VAR_REV(1, MIDR_REVISION_MASK));
 827 }
 828
 829 static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
 830 {
 831         return is_kernel_in_hyp_mode();
 832 }
 833
 834 static bool hyp_offset_low(const struct arm64_cpu_capabilities *entry,
 835                            int __unused)
 836 {
 837         phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
 838
 839         /*
 840          * Activate the lower HYP offset only if:
 841          * - the idmap doesn't clash with it,
 842          * - the kernel is not running at EL2.
 843          */
 844         return idmap_addr > GENMASK(VA_BITS - 2, 0) && !is_kernel_in_hyp_mode();
 845 }
 846
 847 static bool has_no_fpsimd(const struct arm64_cpu_capabilities *entry, int __unused)
 848 {
 849         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 850
 851         return cpuid_feature_extract_signed_field(pfr0,
 852                                         ID_AA64PFR0_FP_SHIFT) < 0;
 853 }
 854
 855 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
 856 static int __kpti_forced; /* 0: not forced, >0: forced on, <0: forced off */
 857
 858 static bool unmap_kernel_at_el0(const struct arm64_cpu_capabilities *entry,
 859                                 int __unused)
 860 {
 861         char const *str = "command line option";
 862         u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
 863
 864         /*
 865          * For reasons that aren't entirely clear, enabling KPTI on Cavium
 866          * ThunderX leads to apparent I-cache corruption of kernel text, which
 867          * ends as well as you might imagine. Don't even try.
 868          */
 869         if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_27456)) {
 870                 str = "ARM64_WORKAROUND_CAVIUM_27456";
 871                 __kpti_forced = -1;
 872         }
 873
 874         /* Forced? */
 875         if (__kpti_forced) {
 876                 pr_info_once("kernel page table isolation forced %s by %s\n",
 877                              __kpti_forced > 0 ? "ON" : "OFF", str);
 878                 return __kpti_forced > 0;
 879         }
 880
 881         /* Useful for KASLR robustness */
 882         if (IS_ENABLED(CONFIG_RANDOMIZE_BASE))
 883                 return true;
 884
 885         /* Don't force KPTI for CPUs that are not vulnerable */
 886         switch (read_cpuid_id() & MIDR_CPU_MODEL_MASK) {
 887         case MIDR_CAVIUM_THUNDERX2:
 888         case MIDR_BRCM_VULCAN:
 889                 return false;
 890         }
 891
 892         /* Defer to CPU feature registers */
 893         return !cpuid_feature_extract_unsigned_field(pfr0,
 894                                                      ID_AA64PFR0_CSV3_SHIFT);
 895 }
 896
 897 static int kpti_install_ng_mappings(void *__unused)
 898 {
 899         typedef void (kpti_remap_fn)(int, int, phys_addr_t);
 900         extern kpti_remap_fn idmap_kpti_install_ng_mappings;
 901         kpti_remap_fn *remap_fn;
 902
 903         static bool kpti_applied = false;
 904         int cpu = smp_processor_id();
 905
 906         if (kpti_applied)
 907                 return 0;
 908
 909         remap_fn = (void *)__pa_symbol(idmap_kpti_install_ng_mappings);
 910
 911         cpu_install_idmap();
 912         remap_fn(cpu, num_online_cpus(), __pa_symbol(swapper_pg_dir));
 913         cpu_uninstall_idmap();
 914
 915         if (!cpu)
 916                 kpti_applied = true;
 917
 918         return 0;
 919 }
 920
 921 static int __init parse_kpti(char *str)
 922 {
 923         bool enabled;
 924         int ret = strtobool(str, &enabled);
 925
 926         if (ret)
 927                 return ret;
 928
 929         __kpti_forced = enabled ? 1 : -1;
 930         return 0;
 931 }
 932 __setup("kpti=", parse_kpti);
 933 #endif  /* CONFIG_UNMAP_KERNEL_AT_EL0 */
 934
 935 static int cpu_copy_el2regs(void *__unused)
 936 {
 937         /*
 938          * Copy register values that aren't redirected by hardware.
 939          *
 940          * Before code patching, we only set tpidr_el1, all CPUs need to copy
 941          * this value to tpidr_el2 before we patch the code. Once we've done
 942          * that, freshly-onlined CPUs will set tpidr_el2, so we don't need to
 943          * do anything here.
 944          */
 945         if (!alternatives_applied)
 946                 write_sysreg(read_sysreg(tpidr_el1), tpidr_el2);
 947
 948         return 0;
 949 }
 950
 951 static const struct arm64_cpu_capabilities arm64_features[] = {
 952         {
 953                 .desc = "GIC system register CPU interface",
 954                 .capability = ARM64_HAS_SYSREG_GIC_CPUIF,
 955                 .def_scope = SCOPE_SYSTEM,
 956                 .matches = has_useable_gicv3_cpuif,
 957                 .sys_reg = SYS_ID_AA64PFR0_EL1,
 958                 .field_pos = ID_AA64PFR0_GIC_SHIFT,
 959                 .sign = FTR_UNSIGNED,
 960                 .min_field_value = 1,
 961         },
 962 #ifdef CONFIG_ARM64_PAN
 963         {
 964                 .desc = "Privileged Access Never",
 965                 .capability = ARM64_HAS_PAN,
 966                 .def_scope = SCOPE_SYSTEM,
 967                 .matches = has_cpuid_feature,
 968                 .sys_reg = SYS_ID_AA64MMFR1_EL1,
 969                 .field_pos = ID_AA64MMFR1_PAN_SHIFT,
 970                 .sign = FTR_UNSIGNED,
 971                 .min_field_value = 1,
 972                 .enable = cpu_enable_pan,
 973         },
 974 #endif /* CONFIG_ARM64_PAN */
 975 #if defined(CONFIG_AS_LSE) && defined(CONFIG_ARM64_LSE_ATOMICS)
 976         {
 977                 .desc = "LSE atomic instructions",
 978                 .capability = ARM64_HAS_LSE_ATOMICS,
 979                 .def_scope = SCOPE_SYSTEM,
 980                 .matches = has_cpuid_feature,
 981                 .sys_reg = SYS_ID_AA64ISAR0_EL1,
 982                 .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT,
 983                 .sign = FTR_UNSIGNED,
 984                 .min_field_value = 2,
 985         },
 986 #endif /* CONFIG_AS_LSE && CONFIG_ARM64_LSE_ATOMICS */
 987         {
 988                 .desc = "Software prefetching using PRFM",
 989                 .capability = ARM64_HAS_NO_HW_PREFETCH,
 990                 .def_scope = SCOPE_SYSTEM,
 991                 .matches = has_no_hw_prefetch,
 992         },
 993 #ifdef CONFIG_ARM64_UAO
 994         {
 995                 .desc = "User Access Override",
 996                 .capability = ARM64_HAS_UAO,
 997                 .def_scope = SCOPE_SYSTEM,
 998                 .matches = has_cpuid_feature,
 999                 .sys_reg = SYS_ID_AA64MMFR2_EL1,
1000                 .field_pos = ID_AA64MMFR2_UAO_SHIFT,
1001                 .min_field_value = 1,
1002                 /*
1003                  * We rely on stop_machine() calling uao_thread_switch() to set
1004                  * UAO immediately after patching.
1005                  */
1006         },
1007 #endif /* CONFIG_ARM64_UAO */
1008 #ifdef CONFIG_ARM64_PAN
1009         {
1010                 .capability = ARM64_ALT_PAN_NOT_UAO,
1011                 .def_scope = SCOPE_SYSTEM,
1012                 .matches = cpufeature_pan_not_uao,
1013         },
1014 #endif /* CONFIG_ARM64_PAN */
1015         {
1016                 .desc = "Virtualization Host Extensions",
1017                 .capability = ARM64_HAS_VIRT_HOST_EXTN,
1018                 .def_scope = SCOPE_SYSTEM,
1019                 .matches = runs_at_el2,
1020                 .enable = cpu_copy_el2regs,
1021         },
1022         {
1023                 .desc = "32-bit EL0 Support",
1024                 .capability = ARM64_HAS_32BIT_EL0,
1025                 .def_scope = SCOPE_SYSTEM,
1026                 .matches = has_cpuid_feature,
1027                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1028                 .sign = FTR_UNSIGNED,
1029                 .field_pos = ID_AA64PFR0_EL0_SHIFT,
1030                 .min_field_value = ID_AA64PFR0_EL0_32BIT_64BIT,
1031         },
1032         {
1033                 .desc = "Reduced HYP mapping offset",
1034                 .capability = ARM64_HYP_OFFSET_LOW,
1035                 .def_scope = SCOPE_SYSTEM,
1036                 .matches = hyp_offset_low,
1037         },
1038 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1039         {
1040                 .desc = "Kernel page table isolation (KPTI)",
1041                 .capability = ARM64_UNMAP_KERNEL_AT_EL0,
1042                 .def_scope = SCOPE_SYSTEM,
1043                 .matches = unmap_kernel_at_el0,
1044                 .enable = kpti_install_ng_mappings,
1045         },
1046 #endif
1047         {
1048                 /* FP/SIMD is not implemented */
1049                 .capability = ARM64_HAS_NO_FPSIMD,
1050                 .def_scope = SCOPE_SYSTEM,
1051                 .min_field_value = 0,
1052                 .matches = has_no_fpsimd,
1053         },
1054 #ifdef CONFIG_ARM64_PMEM
1055         {
1056                 .desc = "Data cache clean to Point of Persistence",
1057                 .capability = ARM64_HAS_DCPOP,
1058                 .def_scope = SCOPE_SYSTEM,
1059                 .matches = has_cpuid_feature,
1060                 .sys_reg = SYS_ID_AA64ISAR1_EL1,
1061                 .field_pos = ID_AA64ISAR1_DPB_SHIFT,
1062                 .min_field_value = 1,
1063         },
1064 #endif
1065 #ifdef CONFIG_ARM64_SVE
1066         {
1067                 .desc = "Scalable Vector Extension",
1068                 .capability = ARM64_SVE,
1069                 .def_scope = SCOPE_SYSTEM,
1070                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1071                 .sign = FTR_UNSIGNED,
1072                 .field_pos = ID_AA64PFR0_SVE_SHIFT,
1073                 .min_field_value = ID_AA64PFR0_SVE,
1074                 .matches = has_cpuid_feature,
1075                 .enable = sve_kernel_enable,
1076         },
1077 #endif /* CONFIG_ARM64_SVE */
1078 #ifdef CONFIG_ARM64_RAS_EXTN
1079         {
1080                 .desc = "RAS Extension Support",
1081                 .capability = ARM64_HAS_RAS_EXTN,
1082                 .def_scope = SCOPE_SYSTEM,
1083                 .matches = has_cpuid_feature,
1084                 .sys_reg = SYS_ID_AA64PFR0_EL1,
1085                 .sign = FTR_UNSIGNED,
1086                 .field_pos = ID_AA64PFR0_RAS_SHIFT,
1087                 .min_field_value = ID_AA64PFR0_RAS_V1,
1088                 .enable = cpu_clear_disr,
1089         },
1090 #endif /* CONFIG_ARM64_RAS_EXTN */
1091         {},
1092 };
1093
1094 #define HWCAP_CAP(reg, field, s, min_value, type, cap)  \
1095         {                                                       \
1096                 .desc = #cap,                                   \
1097                 .def_scope = SCOPE_SYSTEM,                      \
1098                 .matches = has_cpuid_feature,                   \
1099                 .sys_reg = reg,                                 \
1100                 .field_pos = field,                             \
1101                 .sign = s,                                      \
1102                 .min_field_value = min_value,                   \
1103                 .hwcap_type = type,                             \
1104                 .hwcap = cap,                                   \
1105         }
1106
1107 static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
1108         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_PMULL),
1109         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_AES),
1110         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA1),
1111         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA2),
1112         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_SHA512),
1113         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_CRC32),
1114         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, FTR_UNSIGNED, 2, CAP_HWCAP, HWCAP_ATOMICS),
1115         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDRDM),
1116         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SHA3),
1117         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM3),
1118         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_SM4),
1119         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDDP),
1120         HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_ASIMDFHM),
1121         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_FP),
1122         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_FPHP),
1123         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 0, CAP_HWCAP, HWCAP_ASIMD),
1124         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, FTR_SIGNED, 1, CAP_HWCAP, HWCAP_ASIMDHP),
1125         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_DPB_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_DCPOP),
1126         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_JSCVT_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_JSCVT),
1127         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_FCMA_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_FCMA),
1128         HWCAP_CAP(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_LRCPC_SHIFT, FTR_UNSIGNED, 1, CAP_HWCAP, HWCAP_LRCPC),
1129 #ifdef CONFIG_ARM64_SVE
1130         HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_SVE_SHIFT, FTR_UNSIGNED, ID_AA64PFR0_SVE, CAP_HWCAP, HWCAP_SVE),
1131 #endif
1132         {},
1133 };
1134
1135 static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = {
1136 #ifdef CONFIG_COMPAT
1137         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),
1138         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_AES_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),
1139         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA1_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),
1140         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_SHA2_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA2),
1141         HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_CRC32_SHIFT, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_CRC32),
1142 #endif
1143         {},
1144 };
1145
1146 static void __init cap_set_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1147 {
1148         switch (cap->hwcap_type) {
1149         case CAP_HWCAP:
1150                 elf_hwcap |= cap->hwcap;
1151                 break;
1152 #ifdef CONFIG_COMPAT
1153         case CAP_COMPAT_HWCAP:
1154                 compat_elf_hwcap |= (u32)cap->hwcap;
1155                 break;
1156         case CAP_COMPAT_HWCAP2:
1157                 compat_elf_hwcap2 |= (u32)cap->hwcap;
1158                 break;
1159 #endif
1160         default:
1161                 WARN_ON(1);
1162                 break;
1163         }
1164 }
1165
1166 /* Check if we have a particular HWCAP enabled */
1167 static bool cpus_have_elf_hwcap(const struct arm64_cpu_capabilities *cap)
1168 {
1169         bool rc;
1170
1171         switch (cap->hwcap_type) {
1172         case CAP_HWCAP:
1173                 rc = (elf_hwcap & cap->hwcap) != 0;
1174                 break;
1175 #ifdef CONFIG_COMPAT
1176         case CAP_COMPAT_HWCAP:
1177                 rc = (compat_elf_hwcap & (u32)cap->hwcap) != 0;
1178                 break;
1179         case CAP_COMPAT_HWCAP2:
1180                 rc = (compat_elf_hwcap2 & (u32)cap->hwcap) != 0;
1181                 break;
1182 #endif
1183         default:
1184                 WARN_ON(1);
1185                 rc = false;
1186         }
1187
1188         return rc;
1189 }
1190
1191 static void __init setup_elf_hwcaps(const struct arm64_cpu_capabilities *hwcaps)
1192 {
1193         /* We support emulation of accesses to CPU ID feature registers */
1194         elf_hwcap |= HWCAP_CPUID;
1195         for (; hwcaps->matches; hwcaps++)
1196                 if (hwcaps->matches(hwcaps, hwcaps->def_scope))
1197                         cap_set_elf_hwcap(hwcaps);
1198 }
1199
1200 /*
1201  * Check if the current CPU has a given feature capability.
1202  * Should be called from non-preemptible context.
1203  */
1204 static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
1205                                unsigned int cap)
1206 {
1207         const struct arm64_cpu_capabilities *caps;
1208
1209         if (WARN_ON(preemptible()))
1210                 return false;
1211
1212         for (caps = cap_array; caps->matches; caps++)
1213                 if (caps->capability == cap &&
1214                     caps->matches(caps, SCOPE_LOCAL_CPU))
1215                         return true;
1216         return false;
1217 }
1218
1219 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps,
1220                             const char *info)
1221 {
1222         for (; caps->matches; caps++) {
1223                 if (!caps->matches(caps, caps->def_scope))
1224                         continue;
1225
1226                 if (!cpus_have_cap(caps->capability) && caps->desc)
1227                         pr_info("%s %s\n", info, caps->desc);
1228                 cpus_set_cap(caps->capability);
1229         }
1230 }
1231
1232 /*
1233  * Run through the enabled capabilities and enable() it on all active
1234  * CPUs
1235  */
1236 void __init enable_cpu_capabilities(const struct arm64_cpu_capabilities *caps)
1237 {
1238         for (; caps->matches; caps++) {
1239                 unsigned int num = caps->capability;
1240
1241                 if (!cpus_have_cap(num))
1242                         continue;
1243
1244                 /* Ensure cpus_have_const_cap(num) works */
1245                 static_branch_enable(&cpu_hwcap_keys[num]);
1246
1247                 if (caps->enable) {
1248                         /*
1249                          * Use stop_machine() as it schedules the work allowing
1250                          * us to modify PSTATE, instead of on_each_cpu() which
1251                          * uses an IPI, giving us a PSTATE that disappears when
1252                          * we return.
1253                          */
1254                         stop_machine(caps->enable, (void *)caps, cpu_online_mask);
1255                 }
1256         }
1257 }
1258
1259 /*
1260  * Check for CPU features that are used in early boot
1261  * based on the Boot CPU value.
1262  */
1263 static void check_early_cpu_features(void)
1264 {
1265         verify_cpu_run_el();
1266         verify_cpu_asid_bits();
1267 }
1268
1269 static void
1270 verify_local_elf_hwcaps(const struct arm64_cpu_capabilities *caps)
1271 {
1272
1273         for (; caps->matches; caps++)
1274                 if (cpus_have_elf_hwcap(caps) && !caps->matches(caps, SCOPE_LOCAL_CPU)) {
1275                         pr_crit("CPU%d: missing HWCAP: %s\n",
1276                                         smp_processor_id(), caps->desc);
1277                         cpu_die_early();
1278                 }
1279 }
1280
1281 static void
1282 verify_local_cpu_features(const struct arm64_cpu_capabilities *caps_list)
1283 {
1284         const struct arm64_cpu_capabilities *caps = caps_list;
1285         for (; caps->matches; caps++) {
1286                 if (!cpus_have_cap(caps->capability))
1287                         continue;
1288                 /*
1289                  * If the new CPU misses an advertised feature, we cannot proceed
1290                  * further, park the cpu.
1291                  */
1292                 if (!__this_cpu_has_cap(caps_list, caps->capability)) {
1293                         pr_crit("CPU%d: missing feature: %s\n",
1294                                         smp_processor_id(), caps->desc);
1295                         cpu_die_early();
1296                 }
1297                 if (caps->enable)
1298                         caps->enable((void *)caps);
1299         }
1300 }
1301
1302 static void verify_sve_features(void)
1303 {
1304         u64 safe_zcr = read_sanitised_ftr_reg(SYS_ZCR_EL1);
1305         u64 zcr = read_zcr_features();
1306
1307         unsigned int safe_len = safe_zcr & ZCR_ELx_LEN_MASK;
1308         unsigned int len = zcr & ZCR_ELx_LEN_MASK;
1309
1310         if (len < safe_len || sve_verify_vq_map()) {
1311                 pr_crit("CPU%d: SVE: required vector length(s) missing\n",
1312                         smp_processor_id());
1313                 cpu_die_early();
1314         }
1315
1316         /* Add checks on other ZCR bits here if necessary */
1317 }
1318
1319 /*
1320  * Run through the enabled system capabilities and enable() it on this CPU.
1321  * The capabilities were decided based on the available CPUs at the boot time.
1322  * Any new CPU should match the system wide status of the capability. If the
1323  * new CPU doesn't have a capability which the system now has enabled, we
1324  * cannot do anything to fix it up and could cause unexpected failures. So
1325  * we park the CPU.
1326  */
1327 static void verify_local_cpu_capabilities(void)
1328 {
1329         verify_local_cpu_errata_workarounds();
1330         verify_local_cpu_features(arm64_features);
1331         verify_local_elf_hwcaps(arm64_elf_hwcaps);
1332
1333         if (system_supports_32bit_el0())
1334                 verify_local_elf_hwcaps(compat_elf_hwcaps);
1335
1336         if (system_supports_sve())
1337                 verify_sve_features();
1338
1339         if (system_uses_ttbr0_pan())
1340                 pr_info("Emulating Privileged Access Never (PAN) using TTBR0_EL1 switching\n");
1341 }
1342
1343 void check_local_cpu_capabilities(void)
1344 {
1345         /*
1346          * All secondary CPUs should conform to the early CPU features
1347          * in use by the kernel based on boot CPU.
1348          */
1349         check_early_cpu_features();
1350
1351         /*
1352          * If we haven't finalised the system capabilities, this CPU gets
1353          * a chance to update the errata work arounds.
1354          * Otherwise, this CPU should verify that it has all the system
1355          * advertised capabilities.
1356          */
1357         if (!sys_caps_initialised)
1358                 update_cpu_errata_workarounds();
1359         else
1360                 verify_local_cpu_capabilities();
1361 }
1362
1363 static void __init setup_feature_capabilities(void)
1364 {
1365         update_cpu_capabilities(arm64_features, "detected feature:");
1366         enable_cpu_capabilities(arm64_features);
1367 }
1368
1369 DEFINE_STATIC_KEY_FALSE(arm64_const_caps_ready);
1370 EXPORT_SYMBOL(arm64_const_caps_ready);
1371
1372 static void __init mark_const_caps_ready(void)
1373 {
1374         static_branch_enable(&arm64_const_caps_ready);
1375 }
1376
1377 extern const struct arm64_cpu_capabilities arm64_errata[];
1378
1379 bool this_cpu_has_cap(unsigned int cap)
1380 {
1381         return (__this_cpu_has_cap(arm64_features, cap) ||
1382                 __this_cpu_has_cap(arm64_errata, cap));
1383 }
1384
1385 void __init setup_cpu_features(void)
1386 {
1387         u32 cwg;
1388         int cls;
1389
1390         /* Set the CPU feature capabilies */
1391         setup_feature_capabilities();
1392         enable_errata_workarounds();
1393         mark_const_caps_ready();
1394         setup_elf_hwcaps(arm64_elf_hwcaps);
1395
1396         if (system_supports_32bit_el0())
1397                 setup_elf_hwcaps(compat_elf_hwcaps);
1398
1399         sve_setup();
1400
1401         /* Advertise that we have computed the system capabilities */
1402         set_sys_caps_initialised();
1403
1404         /*
1405          * Check for sane CTR_EL0.CWG value.
1406          */
1407         cwg = cache_type_cwg();
1408         cls = cache_line_size();
1409         if (!cwg)
1410                 pr_warn("No Cache Writeback Granule information, assuming cache line size %d\n",
1411                         cls);
1412         if (L1_CACHE_BYTES < cls)
1413                 pr_warn("L1_CACHE_BYTES smaller than the Cache Writeback Granule (%d < %d)\n",
1414                         L1_CACHE_BYTES, cls);
1415 }
1416
1417 static bool __maybe_unused
1418 cpufeature_pan_not_uao(const struct arm64_cpu_capabilities *entry, int __unused)
1419 {
1420         return (cpus_have_const_cap(ARM64_HAS_PAN) && !cpus_have_const_cap(ARM64_HAS_UAO));
1421 }
1422
1423 /*
1424  * We emulate only the following system register space.
1425  * Op0 = 0x3, CRn = 0x0, Op1 = 0x0, CRm = [0, 4 - 7]
1426  * See Table C5-6 System instruction encodings for System register accesses,
1427  * ARMv8 ARM(ARM DDI 0487A.f) for more details.
1428  */
1429 static inline bool __attribute_const__ is_emulated(u32 id)
1430 {
1431         return (sys_reg_Op0(id) == 0x3 &&
1432                 sys_reg_CRn(id) == 0x0 &&
1433                 sys_reg_Op1(id) == 0x0 &&
1434                 (sys_reg_CRm(id) == 0 ||
1435                  ((sys_reg_CRm(id) >= 4) && (sys_reg_CRm(id) <= 7))));
1436 }
1437
1438 /*
1439  * With CRm == 0, reg should be one of :
1440  * MIDR_EL1, MPIDR_EL1 or REVIDR_EL1.
1441  */
1442 static inline int emulate_id_reg(u32 id, u64 *valp)
1443 {
1444         switch (id) {
1445         case SYS_MIDR_EL1:
1446                 *valp = read_cpuid_id();
1447                 break;
1448         case SYS_MPIDR_EL1:
1449                 *valp = SYS_MPIDR_SAFE_VAL;
1450                 break;
1451         case SYS_REVIDR_EL1:
1452                 /* IMPLEMENTATION DEFINED values are emulated with 0 */
1453                 *valp = 0;
1454                 break;
1455         default:
1456                 return -EINVAL;
1457         }
1458
1459         return 0;
1460 }
1461
1462 static int emulate_sys_reg(u32 id, u64 *valp)
1463 {
1464         struct arm64_ftr_reg *regp;
1465
1466         if (!is_emulated(id))
1467                 return -EINVAL;
1468
1469         if (sys_reg_CRm(id) == 0)
1470                 return emulate_id_reg(id, valp);
1471
1472         regp = get_arm64_ftr_reg(id);
1473         if (regp)
1474                 *valp = arm64_ftr_reg_user_value(regp);
1475         else
1476                 /*
1477                  * The untracked registers are either IMPLEMENTATION DEFINED
1478                  * (e.g, ID_AFR0_EL1) or reserved RAZ.
1479                  */
1480                 *valp = 0;
1481         return 0;
1482 }
1483
1484 static int emulate_mrs(struct pt_regs *regs, u32 insn)
1485 {
1486         int rc;
1487         u32 sys_reg, dst;
1488         u64 val;
1489
1490         /*
1491          * sys_reg values are defined as used in mrs/msr instruction.
1492          * shift the imm value to get the encoding.
1493          */
1494         sys_reg = (u32)aarch64_insn_decode_immediate(AARCH64_INSN_IMM_16, insn) << 5;
1495         rc = emulate_sys_reg(sys_reg, &val);
1496         if (!rc) {
1497                 dst = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RT, insn);
1498                 pt_regs_write_reg(regs, dst, val);
1499                 arm64_skip_faulting_instruction(regs, AARCH64_INSN_SIZE);
1500         }
1501
1502         return rc;
1503 }
1504
1505 static struct undef_hook mrs_hook = {
1506         .instr_mask = 0xfff00000,
1507         .instr_val  = 0xd5300000,
1508         .pstate_mask = COMPAT_PSR_MODE_MASK,
1509         .pstate_val = PSR_MODE_EL0t,
1510         .fn = emulate_mrs,
1511 };
1512
1513 static int __init enable_mrs_emulation(void)
1514 {
1515         register_undef_hook(&mrs_hook);
1516         return 0;
1517 }
1518
1519 core_initcall(enable_mrs_emulation);
1520
1521 int cpu_clear_disr(void *__unused)
1522 {
1523         /* Firmware may have left a deferred SError in this register. */
1524         write_sysreg_s(0, SYS_DISR_EL1);
1525
1526         return 0;
1527 }