2 * Based on arch/arm/include/asm/ptrace.h
4 * Copyright (C) 1996-2003 Russell King
5 * Copyright (C) 2012 ARM Ltd.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __ASM_PTRACE_H
20 #define __ASM_PTRACE_H
22 #include <linux/types.h>
24 #include <asm/hwcap.h>
26 #define PTRACE_GETREGS 12
27 #define PTRACE_SETREGS 13
28 #define PTRACE_GETFPSIMDREGS 14
29 #define PTRACE_SETFPSIMDREGS 15
30 /* PTRACE_ATTACH is 16 */
31 /* PTRACE_DETACH is 17 */
32 #define PTRACE_GET_THREAD_AREA 22
33 #define PTRACE_SET_SYSCALL 23
34 #define PTRACE_GETHBPREGS 29
35 #define PTRACE_SETHBPREGS 30
37 /* AArch32-specific ptrace requests */
38 #define COMPAT_PTRACE_GETVFPREGS 27
39 #define COMPAT_PTRACE_SETVFPREGS 28
44 #define PSR_MODE_EL0t 0x00000000
45 #define PSR_MODE_EL1t 0x00000004
46 #define PSR_MODE_EL1h 0x00000005
47 #define PSR_MODE_EL2t 0x00000008
48 #define PSR_MODE_EL2h 0x00000009
49 #define PSR_MODE_EL3t 0x0000000c
50 #define PSR_MODE_EL3h 0x0000000d
51 #define PSR_MODE_MASK 0x0000000f
53 /* AArch32 CPSR bits */
54 #define PSR_MODE32_BIT 0x00000010
55 #define COMPAT_PSR_MODE_USR 0x00000010
56 #define COMPAT_PSR_T_BIT 0x00000020
57 #define COMPAT_PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
59 /* AArch64 SPSR bits */
60 #define PSR_F_BIT 0x00000040
61 #define PSR_I_BIT 0x00000080
62 #define PSR_A_BIT 0x00000100
63 #define PSR_D_BIT 0x00000200
64 #define PSR_Q_BIT 0x08000000
65 #define PSR_V_BIT 0x10000000
66 #define PSR_C_BIT 0x20000000
67 #define PSR_Z_BIT 0x40000000
68 #define PSR_N_BIT 0x80000000
73 #define PSR_f 0xff000000 /* Flags */
74 #define PSR_s 0x00ff0000 /* Status */
75 #define PSR_x 0x0000ff00 /* Extension */
76 #define PSR_c 0x000000ff /* Control */
79 * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
80 * process is located in memory.
82 #define PT_TEXT_ADDR 0x10000
83 #define PT_DATA_ADDR 0x10004
84 #define PT_TEXT_END_ADDR 0x10008
89 * User structures for general purpose, floating point and debug registers.
98 struct user_fpsimd_state {
99 __uint128_t vregs[32];
104 struct user_hwdebug_state {
114 /* sizeof(struct user) for AArch32 */
115 #define COMPAT_USER_SZ 296
116 /* AArch32 uses x13 as the stack pointer... */
117 #define compat_sp regs[13]
118 /* ... and x14 as the link register. */
119 #define compat_lr regs[14]
122 * This struct defines the way the registers are stored on the stack during an
123 * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
124 * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
128 struct user_pt_regs user_regs;
140 #define arch_has_single_step() (1)
143 #define compat_thumb_mode(regs) \
144 (((regs)->pstate & COMPAT_PSR_T_BIT))
146 #define compat_thumb_mode(regs) (0)
149 #define user_mode(regs) \
150 (((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
152 #define compat_user_mode(regs) \
153 (((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
154 (PSR_MODE32_BIT | PSR_MODE_EL0t))
156 #define processor_mode(regs) \
157 ((regs)->pstate & PSR_MODE_MASK)
159 #define interrupts_enabled(regs) \
160 (!((regs)->pstate & PSR_I_BIT))
162 #define fast_interrupts_enabled(regs) \
163 (!((regs)->pstate & PSR_F_BIT))
165 #define user_stack_pointer(regs) \
169 * Are the current registers suitable for user mode? (used to maintain
170 * security in signal handlers)
172 static inline int valid_user_regs(struct user_pt_regs *regs)
174 if (user_mode(regs) && (regs->pstate & PSR_I_BIT) == 0) {
175 regs->pstate &= ~(PSR_F_BIT | PSR_A_BIT);
177 /* The T bit is reserved for AArch64 */
178 if (!(regs->pstate & PSR_MODE32_BIT))
179 regs->pstate &= ~COMPAT_PSR_T_BIT;
185 * Force PSR to something logical...
187 regs->pstate &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | \
188 COMPAT_PSR_T_BIT | PSR_MODE32_BIT;
190 if (!(regs->pstate & PSR_MODE32_BIT)) {
191 regs->pstate &= ~COMPAT_PSR_T_BIT;
192 regs->pstate |= PSR_MODE_EL0t;
198 #define instruction_pointer(regs) (regs)->pc
201 extern unsigned long profile_pc(struct pt_regs *regs);
203 #define profile_pc(regs) instruction_pointer(regs)
206 extern int aarch32_break_trap(struct pt_regs *regs);
208 #endif /* __KERNEL__ */
210 #endif /* __ASSEMBLY__ */