2 * Copyright (C) 2012,2013 - ARM Ltd
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * Derived from arch/arm/include/asm/kvm_host.h:
6 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
7 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __ARM64_KVM_HOST_H__
23 #define __ARM64_KVM_HOST_H__
25 #include <linux/types.h>
26 #include <linux/kvm_types.h>
27 #include <asm/arch_gicv3.h>
28 #include <asm/cpufeature.h>
29 #include <asm/daifflags.h>
30 #include <asm/fpsimd.h>
32 #include <asm/kvm_asm.h>
33 #include <asm/kvm_mmio.h>
34 #include <asm/thread_info.h>
36 #define __KVM_HAVE_ARCH_INTC_INITIALIZED
38 #define KVM_USER_MEM_SLOTS 512
39 #define KVM_HALT_POLL_NS_DEFAULT 500000
41 #include <kvm/arm_vgic.h>
42 #include <kvm/arm_arch_timer.h>
43 #include <kvm/arm_pmu.h>
45 #define KVM_MAX_VCPUS VGIC_V3_MAX_CPUS
47 #define KVM_VCPU_MAX_FEATURES 4
49 #define KVM_REQ_SLEEP \
50 KVM_ARCH_REQ_FLAGS(0, KVM_REQUEST_WAIT | KVM_REQUEST_NO_WAKEUP)
51 #define KVM_REQ_IRQ_PENDING KVM_ARCH_REQ(1)
52 #define KVM_REQ_VCPU_RESET KVM_ARCH_REQ(2)
54 DECLARE_STATIC_KEY_FALSE(userspace_irqchip_in_use);
56 int __attribute_const__ kvm_target_cpu(void);
57 int kvm_reset_vcpu(struct kvm_vcpu *vcpu);
58 int kvm_arch_vm_ioctl_check_extension(struct kvm *kvm, long ext);
59 void __extended_idmap_trampoline(phys_addr_t boot_pgd, phys_addr_t idmap_start);
62 /* The VMID generation used for the virt. memory system */
66 /* stage2 entry level table */
69 /* VTTBR value associated with above pgd and vmid */
71 /* VTCR_EL2 value for this VM */
74 /* The last vcpu id that ran on each physical CPU */
75 int __percpu *last_vcpu_ran;
77 /* The maximum number of vCPUs depends on the used GIC model */
80 /* Interrupt controller */
81 struct vgic_dist vgic;
83 /* Mandated version of PSCI */
87 #define KVM_NR_MEM_OBJS 40
90 * We don't want allocation failures within the mmu code, so we preallocate
91 * enough memory for a single page fault in a cache.
93 struct kvm_mmu_memory_cache {
95 void *objects[KVM_NR_MEM_OBJS];
98 struct kvm_vcpu_fault_info {
99 u32 esr_el2; /* Hyp Syndrom Register */
100 u64 far_el2; /* Hyp Fault Address Register */
101 u64 hpfar_el2; /* Hyp IPA Fault Address Register */
102 u64 disr_el1; /* Deferred [SError] Status Register */
106 * 0 is reserved as an invalid value.
107 * Order should be kept in sync with the save/restore code.
111 MPIDR_EL1, /* MultiProcessor Affinity Register */
112 CSSELR_EL1, /* Cache Size Selection Register */
113 SCTLR_EL1, /* System Control Register */
114 ACTLR_EL1, /* Auxiliary Control Register */
115 CPACR_EL1, /* Coprocessor Access Control */
116 TTBR0_EL1, /* Translation Table Base Register 0 */
117 TTBR1_EL1, /* Translation Table Base Register 1 */
118 TCR_EL1, /* Translation Control Register */
119 ESR_EL1, /* Exception Syndrome Register */
120 AFSR0_EL1, /* Auxiliary Fault Status Register 0 */
121 AFSR1_EL1, /* Auxiliary Fault Status Register 1 */
122 FAR_EL1, /* Fault Address Register */
123 MAIR_EL1, /* Memory Attribute Indirection Register */
124 VBAR_EL1, /* Vector Base Address Register */
125 CONTEXTIDR_EL1, /* Context ID Register */
126 TPIDR_EL0, /* Thread ID, User R/W */
127 TPIDRRO_EL0, /* Thread ID, User R/O */
128 TPIDR_EL1, /* Thread ID, Privileged */
129 AMAIR_EL1, /* Aux Memory Attribute Indirection Register */
130 CNTKCTL_EL1, /* Timer Control Register (EL1) */
131 PAR_EL1, /* Physical Address Register */
132 MDSCR_EL1, /* Monitor Debug System Control Register */
133 MDCCINT_EL1, /* Monitor Debug Comms Channel Interrupt Enable Reg */
134 DISR_EL1, /* Deferred Interrupt Status Register */
136 /* Performance Monitors Registers */
137 PMCR_EL0, /* Control Register */
138 PMSELR_EL0, /* Event Counter Selection Register */
139 PMEVCNTR0_EL0, /* Event Counter Register (0-30) */
140 PMEVCNTR30_EL0 = PMEVCNTR0_EL0 + 30,
141 PMCCNTR_EL0, /* Cycle Counter Register */
142 PMEVTYPER0_EL0, /* Event Type Register (0-30) */
143 PMEVTYPER30_EL0 = PMEVTYPER0_EL0 + 30,
144 PMCCFILTR_EL0, /* Cycle Count Filter Register */
145 PMCNTENSET_EL0, /* Count Enable Set Register */
146 PMINTENSET_EL1, /* Interrupt Enable Set Register */
147 PMOVSSET_EL0, /* Overflow Flag Status Set Register */
148 PMSWINC_EL0, /* Software Increment Register */
149 PMUSERENR_EL0, /* User Enable Register */
151 /* 32bit specific registers. Keep them at the end of the range */
152 DACR32_EL2, /* Domain Access Control Register */
153 IFSR32_EL2, /* Instruction Fault Status Register */
154 FPEXC32_EL2, /* Floating-Point Exception Control Register */
155 DBGVCR32_EL2, /* Debug Vector Catch Register */
157 NR_SYS_REGS /* Nothing after this line! */
161 #define c0_MPIDR (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
162 #define c0_CSSELR (CSSELR_EL1 * 2)/* Cache Size Selection Register */
163 #define c1_SCTLR (SCTLR_EL1 * 2) /* System Control Register */
164 #define c1_ACTLR (ACTLR_EL1 * 2) /* Auxiliary Control Register */
165 #define c1_CPACR (CPACR_EL1 * 2) /* Coprocessor Access Control */
166 #define c2_TTBR0 (TTBR0_EL1 * 2) /* Translation Table Base Register 0 */
167 #define c2_TTBR0_high (c2_TTBR0 + 1) /* TTBR0 top 32 bits */
168 #define c2_TTBR1 (TTBR1_EL1 * 2) /* Translation Table Base Register 1 */
169 #define c2_TTBR1_high (c2_TTBR1 + 1) /* TTBR1 top 32 bits */
170 #define c2_TTBCR (TCR_EL1 * 2) /* Translation Table Base Control R. */
171 #define c3_DACR (DACR32_EL2 * 2)/* Domain Access Control Register */
172 #define c5_DFSR (ESR_EL1 * 2) /* Data Fault Status Register */
173 #define c5_IFSR (IFSR32_EL2 * 2)/* Instruction Fault Status Register */
174 #define c5_ADFSR (AFSR0_EL1 * 2) /* Auxiliary Data Fault Status R */
175 #define c5_AIFSR (AFSR1_EL1 * 2) /* Auxiliary Instr Fault Status R */
176 #define c6_DFAR (FAR_EL1 * 2) /* Data Fault Address Register */
177 #define c6_IFAR (c6_DFAR + 1) /* Instruction Fault Address Register */
178 #define c7_PAR (PAR_EL1 * 2) /* Physical Address Register */
179 #define c7_PAR_high (c7_PAR + 1) /* PAR top 32 bits */
180 #define c10_PRRR (MAIR_EL1 * 2) /* Primary Region Remap Register */
181 #define c10_NMRR (c10_PRRR + 1) /* Normal Memory Remap Register */
182 #define c12_VBAR (VBAR_EL1 * 2) /* Vector Base Address Register */
183 #define c13_CID (CONTEXTIDR_EL1 * 2) /* Context ID Register */
184 #define c13_TID_URW (TPIDR_EL0 * 2) /* Thread ID, User R/W */
185 #define c13_TID_URO (TPIDRRO_EL0 * 2)/* Thread ID, User R/O */
186 #define c13_TID_PRIV (TPIDR_EL1 * 2) /* Thread ID, Privileged */
187 #define c10_AMAIR0 (AMAIR_EL1 * 2) /* Aux Memory Attr Indirection Reg */
188 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
189 #define c14_CNTKCTL (CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
191 #define cp14_DBGDSCRext (MDSCR_EL1 * 2)
192 #define cp14_DBGBCR0 (DBGBCR0_EL1 * 2)
193 #define cp14_DBGBVR0 (DBGBVR0_EL1 * 2)
194 #define cp14_DBGBXVR0 (cp14_DBGBVR0 + 1)
195 #define cp14_DBGWCR0 (DBGWCR0_EL1 * 2)
196 #define cp14_DBGWVR0 (DBGWVR0_EL1 * 2)
197 #define cp14_DBGDCCINT (MDCCINT_EL1 * 2)
199 #define NR_COPRO_REGS (NR_SYS_REGS * 2)
201 struct kvm_cpu_context {
202 struct kvm_regs gp_regs;
204 u64 sys_regs[NR_SYS_REGS];
205 u32 copro[NR_COPRO_REGS];
208 struct kvm_vcpu *__hyp_running_vcpu;
211 typedef struct kvm_cpu_context kvm_cpu_context_t;
213 struct vcpu_reset_state {
220 struct kvm_vcpu_arch {
221 struct kvm_cpu_context ctxt;
223 /* HYP configuration */
227 /* Exception Information */
228 struct kvm_vcpu_fault_info fault;
230 /* State of various workarounds, see kvm_asm.h for bit assignment */
231 u64 workaround_flags;
233 /* Miscellaneous vcpu state flags */
237 * We maintain more than a single set of debug registers to support
238 * debugging the guest from the host and to maintain separate host and
239 * guest state during world switches. vcpu_debug_state are the debug
240 * registers of the vcpu as the guest sees them. host_debug_state are
241 * the host registers which are saved and restored during
242 * world switches. external_debug_state contains the debug
243 * values we want to debug the guest. This is set via the
244 * KVM_SET_GUEST_DEBUG ioctl.
246 * debug_ptr points to the set of debug registers that should be loaded
247 * onto the hardware when running the guest.
249 struct kvm_guest_debug_arch *debug_ptr;
250 struct kvm_guest_debug_arch vcpu_debug_state;
251 struct kvm_guest_debug_arch external_debug_state;
253 /* Pointer to host CPU context */
254 kvm_cpu_context_t *host_cpu_context;
256 struct thread_info *host_thread_info; /* hyp VA */
257 struct user_fpsimd_state *host_fpsimd_state; /* hyp VA */
260 /* {Break,watch}point registers */
261 struct kvm_guest_debug_arch regs;
262 /* Statistical profiling extension */
267 struct vgic_cpu vgic_cpu;
268 struct arch_timer_cpu timer_cpu;
272 * Anything that is not used directly from assembly code goes
277 * Guest registers we preserve during guest debugging.
279 * These shadow registers are updated by the kvm_handle_sys_reg
280 * trap handler if the guest accesses or updates them while we
281 * are using guest debug.
285 } guest_debug_preserved;
287 /* vcpu power-off state */
290 /* Don't run the guest (internal implementation need) */
293 /* IO related fields */
294 struct kvm_decode mmio_decode;
296 /* Cache some mmu pages needed inside spinlock regions */
297 struct kvm_mmu_memory_cache mmu_page_cache;
299 /* Target CPU and feature flags */
301 DECLARE_BITMAP(features, KVM_VCPU_MAX_FEATURES);
303 /* Detect first run of a vcpu */
306 /* Virtual SError ESR to restore when HCR_EL2.VSE is set */
309 /* Additional reset state */
310 struct vcpu_reset_state reset_state;
312 /* True when deferrable sysregs are loaded on the physical CPU,
313 * see kvm_vcpu_load_sysregs and kvm_vcpu_put_sysregs. */
314 bool sysregs_loaded_on_cpu;
317 /* vcpu_arch flags field values: */
318 #define KVM_ARM64_DEBUG_DIRTY (1 << 0)
319 #define KVM_ARM64_FP_ENABLED (1 << 1) /* guest FP regs loaded */
320 #define KVM_ARM64_FP_HOST (1 << 2) /* host FP regs loaded */
321 #define KVM_ARM64_HOST_SVE_IN_USE (1 << 3) /* backup for host TIF_SVE */
322 #define KVM_ARM64_HOST_SVE_ENABLED (1 << 4) /* SVE enabled for EL0 */
324 #define vcpu_gp_regs(v) (&(v)->arch.ctxt.gp_regs)
327 * Only use __vcpu_sys_reg if you know you want the memory backed version of a
328 * register, and not the one most recently accessed by a running VCPU. For
329 * example, for userspace access or for system registers that are never context
330 * switched, but only emulated.
332 #define __vcpu_sys_reg(v,r) ((v)->arch.ctxt.sys_regs[(r)])
334 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg);
335 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg);
338 * CP14 and CP15 live in the same array, as they are backed by the
339 * same system registers.
341 #define vcpu_cp14(v,r) ((v)->arch.ctxt.copro[(r)])
342 #define vcpu_cp15(v,r) ((v)->arch.ctxt.copro[(r)])
345 ulong remote_tlb_flush;
348 struct kvm_vcpu_stat {
349 u64 halt_successful_poll;
350 u64 halt_attempted_poll;
351 u64 halt_poll_invalid;
357 u64 mmio_exit_kernel;
361 int kvm_vcpu_preferred_target(struct kvm_vcpu_init *init);
362 unsigned long kvm_arm_num_regs(struct kvm_vcpu *vcpu);
363 int kvm_arm_copy_reg_indices(struct kvm_vcpu *vcpu, u64 __user *indices);
364 int kvm_arm_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
365 int kvm_arm_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg);
366 int __kvm_arm_vcpu_get_events(struct kvm_vcpu *vcpu,
367 struct kvm_vcpu_events *events);
369 int __kvm_arm_vcpu_set_events(struct kvm_vcpu *vcpu,
370 struct kvm_vcpu_events *events);
372 #define KVM_ARCH_WANT_MMU_NOTIFIER
373 int kvm_unmap_hva_range(struct kvm *kvm,
374 unsigned long start, unsigned long end);
375 int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte);
376 int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end);
377 int kvm_test_age_hva(struct kvm *kvm, unsigned long hva);
379 struct kvm_vcpu *kvm_arm_get_running_vcpu(void);
380 struct kvm_vcpu * __percpu *kvm_get_running_vcpus(void);
381 void kvm_arm_halt_guest(struct kvm *kvm);
382 void kvm_arm_resume_guest(struct kvm *kvm);
384 u64 __kvm_call_hyp(void *hypfn, ...);
385 #define kvm_call_hyp(f, ...) __kvm_call_hyp(kvm_ksym_ref(f), ##__VA_ARGS__)
387 void force_vm_exit(const cpumask_t *mask);
388 void kvm_mmu_wp_memory_region(struct kvm *kvm, int slot);
390 int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
391 int exception_index);
392 void handle_exit_early(struct kvm_vcpu *vcpu, struct kvm_run *run,
393 int exception_index);
395 int kvm_perf_init(void);
396 int kvm_perf_teardown(void);
398 void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 syndrome);
400 struct kvm_vcpu *kvm_mpidr_to_vcpu(struct kvm *kvm, unsigned long mpidr);
402 DECLARE_PER_CPU(kvm_cpu_context_t, kvm_host_cpu_state);
404 void __kvm_enable_ssbs(void);
406 static inline void __cpu_init_hyp_mode(phys_addr_t pgd_ptr,
407 unsigned long hyp_stack_ptr,
408 unsigned long vector_ptr)
411 * Calculate the raw per-cpu offset without a translation from the
412 * kernel's mapping to the linear mapping, and store it in tpidr_el2
413 * so that we can use adr_l to access per-cpu variables in EL2.
415 u64 tpidr_el2 = ((u64)this_cpu_ptr(&kvm_host_cpu_state) -
416 (u64)kvm_ksym_ref(kvm_host_cpu_state));
419 * Call initialization code, and switch to the full blown HYP code.
420 * If the cpucaps haven't been finalized yet, something has gone very
421 * wrong, and hyp will crash and burn when it uses any
422 * cpus_have_const_cap() wrapper.
424 BUG_ON(!static_branch_likely(&arm64_const_caps_ready));
425 __kvm_call_hyp((void *)pgd_ptr, hyp_stack_ptr, vector_ptr, tpidr_el2);
428 * Disabling SSBD on a non-VHE system requires us to enable SSBS
431 if (!has_vhe() && this_cpu_has_cap(ARM64_SSBS) &&
432 arm64_get_ssbd_state() == ARM64_SSBD_FORCE_DISABLE) {
433 kvm_call_hyp(__kvm_enable_ssbs);
437 static inline bool kvm_arch_requires_vhe(void)
440 * The Arm architecture specifies that implementation of SVE
441 * requires VHE also to be implemented. The KVM code for arm64
442 * relies on this when SVE is present:
444 if (system_supports_sve())
447 /* Some implementations have defects that confine them to VHE */
448 if (cpus_have_cap(ARM64_WORKAROUND_1165522))
454 static inline void kvm_arch_hardware_unsetup(void) {}
455 static inline void kvm_arch_sync_events(struct kvm *kvm) {}
456 static inline void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu) {}
457 static inline void kvm_arch_sched_in(struct kvm_vcpu *vcpu, int cpu) {}
458 static inline void kvm_arch_vcpu_block_finish(struct kvm_vcpu *vcpu) {}
460 void kvm_arm_init_debug(void);
461 void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
462 void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
463 void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
464 int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
465 struct kvm_device_attr *attr);
466 int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
467 struct kvm_device_attr *attr);
468 int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu,
469 struct kvm_device_attr *attr);
471 static inline void __cpu_init_stage2(void) {}
473 /* Guest/host FPSIMD coordination helpers */
474 int kvm_arch_vcpu_run_map_fp(struct kvm_vcpu *vcpu);
475 void kvm_arch_vcpu_load_fp(struct kvm_vcpu *vcpu);
476 void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu);
477 void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu);
479 #ifdef CONFIG_KVM /* Avoid conflicts with core headers if CONFIG_KVM=n */
480 static inline int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu)
482 return kvm_arch_vcpu_run_map_fp(vcpu);
486 static inline void kvm_arm_vhe_guest_enter(void)
491 * Having IRQs masked via PMR when entering the guest means the GIC
492 * will not signal the CPU of interrupts of lower priority, and the
493 * only way to get out will be via guest exceptions.
494 * Naturally, we want to avoid this.
496 if (system_uses_irq_prio_masking()) {
497 gic_write_pmr(GIC_PRIO_IRQON);
502 static inline void kvm_arm_vhe_guest_exit(void)
505 * local_daif_restore() takes care to properly restore PSTATE.DAIF
506 * and the GIC PMR if the host is using IRQ priorities.
508 local_daif_restore(DAIF_PROCCTX_NOIRQ);
511 * When we exit from the guest we change a number of CPU configuration
512 * parameters, such as traps. Make sure these changes take effect
513 * before running the host or additional guests.
518 static inline bool kvm_arm_harden_branch_predictor(void)
520 return cpus_have_const_cap(ARM64_HARDEN_BRANCH_PREDICTOR);
523 #define KVM_SSBD_UNKNOWN -1
524 #define KVM_SSBD_FORCE_DISABLE 0
525 #define KVM_SSBD_KERNEL 1
526 #define KVM_SSBD_FORCE_ENABLE 2
527 #define KVM_SSBD_MITIGATED 3
529 static inline int kvm_arm_have_ssbd(void)
531 switch (arm64_get_ssbd_state()) {
532 case ARM64_SSBD_FORCE_DISABLE:
533 return KVM_SSBD_FORCE_DISABLE;
534 case ARM64_SSBD_KERNEL:
535 return KVM_SSBD_KERNEL;
536 case ARM64_SSBD_FORCE_ENABLE:
537 return KVM_SSBD_FORCE_ENABLE;
538 case ARM64_SSBD_MITIGATED:
539 return KVM_SSBD_MITIGATED;
540 case ARM64_SSBD_UNKNOWN:
542 return KVM_SSBD_UNKNOWN;
546 void kvm_vcpu_load_sysregs(struct kvm_vcpu *vcpu);
547 void kvm_vcpu_put_sysregs(struct kvm_vcpu *vcpu);
549 void kvm_set_ipa_limit(void);
551 #define __KVM_HAVE_ARCH_VM_ALLOC
552 struct kvm *kvm_arch_alloc_vm(void);
553 void kvm_arch_free_vm(struct kvm *kvm);
555 int kvm_arm_setup_stage2(struct kvm *kvm, unsigned long type);
557 #endif /* __ARM64_KVM_HOST_H__ */