arch/arm64/include/asm/insn.h

   1 /*
   2  * Copyright (C) 2013 Huawei Ltd.
   3  * Author: Jiang Liu <liuj97@gmail.com>
   4  *
   5  * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef __ASM_INSN_H
  20 #define __ASM_INSN_H
  21 #include <linux/types.h>
  22
  23 /* A64 instructions are always 32 bits. */
  24 #define AARCH64_INSN_SIZE               4
  25
  26 #ifndef __ASSEMBLY__
  27 /*
  28  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
  29  * Section C3.1 "A64 instruction index by encoding":
  30  * AArch64 main encoding table
  31  *  Bit position
  32  *   28 27 26 25        Encoding Group
  33  *   0  0  -  -         Unallocated
  34  *   1  0  0  -         Data processing, immediate
  35  *   1  0  1  -         Branch, exception generation and system instructions
  36  *   -  1  -  0         Loads and stores
  37  *   -  1  0  1         Data processing - register
  38  *   0  1  1  1         Data processing - SIMD and floating point
  39  *   1  1  1  1         Data processing - SIMD and floating point
  40  * "-" means "don't care"
  41  */
  42 enum aarch64_insn_encoding_class {
  43         AARCH64_INSN_CLS_UNKNOWN,       /* UNALLOCATED */
  44         AARCH64_INSN_CLS_DP_IMM,        /* Data processing - immediate */
  45         AARCH64_INSN_CLS_DP_REG,        /* Data processing - register */
  46         AARCH64_INSN_CLS_DP_FPSIMD,     /* Data processing - SIMD and FP */
  47         AARCH64_INSN_CLS_LDST,          /* Loads and stores */
  48         AARCH64_INSN_CLS_BR_SYS,        /* Branch, exception generation and
  49                                          * system instructions */
  50 };
  51
  52 enum aarch64_insn_hint_op {
  53         AARCH64_INSN_HINT_NOP   = 0x0 << 5,
  54         AARCH64_INSN_HINT_YIELD = 0x1 << 5,
  55         AARCH64_INSN_HINT_WFE   = 0x2 << 5,
  56         AARCH64_INSN_HINT_WFI   = 0x3 << 5,
  57         AARCH64_INSN_HINT_SEV   = 0x4 << 5,
  58         AARCH64_INSN_HINT_SEVL  = 0x5 << 5,
  59 };
  60
  61 enum aarch64_insn_imm_type {
  62         AARCH64_INSN_IMM_ADR,
  63         AARCH64_INSN_IMM_26,
  64         AARCH64_INSN_IMM_19,
  65         AARCH64_INSN_IMM_16,
  66         AARCH64_INSN_IMM_14,
  67         AARCH64_INSN_IMM_12,
  68         AARCH64_INSN_IMM_9,
  69         AARCH64_INSN_IMM_7,
  70         AARCH64_INSN_IMM_6,
  71         AARCH64_INSN_IMM_S,
  72         AARCH64_INSN_IMM_R,
  73         AARCH64_INSN_IMM_MAX
  74 };
  75
  76 enum aarch64_insn_register_type {
  77         AARCH64_INSN_REGTYPE_RT,
  78         AARCH64_INSN_REGTYPE_RN,
  79         AARCH64_INSN_REGTYPE_RT2,
  80         AARCH64_INSN_REGTYPE_RM,
  81         AARCH64_INSN_REGTYPE_RD,
  82         AARCH64_INSN_REGTYPE_RA,
  83 };
  84
  85 enum aarch64_insn_register {
  86         AARCH64_INSN_REG_0  = 0,
  87         AARCH64_INSN_REG_1  = 1,
  88         AARCH64_INSN_REG_2  = 2,
  89         AARCH64_INSN_REG_3  = 3,
  90         AARCH64_INSN_REG_4  = 4,
  91         AARCH64_INSN_REG_5  = 5,
  92         AARCH64_INSN_REG_6  = 6,
  93         AARCH64_INSN_REG_7  = 7,
  94         AARCH64_INSN_REG_8  = 8,
  95         AARCH64_INSN_REG_9  = 9,
  96         AARCH64_INSN_REG_10 = 10,
  97         AARCH64_INSN_REG_11 = 11,
  98         AARCH64_INSN_REG_12 = 12,
  99         AARCH64_INSN_REG_13 = 13,
 100         AARCH64_INSN_REG_14 = 14,
 101         AARCH64_INSN_REG_15 = 15,
 102         AARCH64_INSN_REG_16 = 16,
 103         AARCH64_INSN_REG_17 = 17,
 104         AARCH64_INSN_REG_18 = 18,
 105         AARCH64_INSN_REG_19 = 19,
 106         AARCH64_INSN_REG_20 = 20,
 107         AARCH64_INSN_REG_21 = 21,
 108         AARCH64_INSN_REG_22 = 22,
 109         AARCH64_INSN_REG_23 = 23,
 110         AARCH64_INSN_REG_24 = 24,
 111         AARCH64_INSN_REG_25 = 25,
 112         AARCH64_INSN_REG_26 = 26,
 113         AARCH64_INSN_REG_27 = 27,
 114         AARCH64_INSN_REG_28 = 28,
 115         AARCH64_INSN_REG_29 = 29,
 116         AARCH64_INSN_REG_FP = 29, /* Frame pointer */
 117         AARCH64_INSN_REG_30 = 30,
 118         AARCH64_INSN_REG_LR = 30, /* Link register */
 119         AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
 120         AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
 121 };
 122
 123 enum aarch64_insn_special_register {
 124         AARCH64_INSN_SPCLREG_SPSR_EL1   = 0xC200,
 125         AARCH64_INSN_SPCLREG_ELR_EL1    = 0xC201,
 126         AARCH64_INSN_SPCLREG_SP_EL0     = 0xC208,
 127         AARCH64_INSN_SPCLREG_SPSEL      = 0xC210,
 128         AARCH64_INSN_SPCLREG_CURRENTEL  = 0xC212,
 129         AARCH64_INSN_SPCLREG_DAIF       = 0xDA11,
 130         AARCH64_INSN_SPCLREG_NZCV       = 0xDA10,
 131         AARCH64_INSN_SPCLREG_FPCR       = 0xDA20,
 132         AARCH64_INSN_SPCLREG_DSPSR_EL0  = 0xDA28,
 133         AARCH64_INSN_SPCLREG_DLR_EL0    = 0xDA29,
 134         AARCH64_INSN_SPCLREG_SPSR_EL2   = 0xE200,
 135         AARCH64_INSN_SPCLREG_ELR_EL2    = 0xE201,
 136         AARCH64_INSN_SPCLREG_SP_EL1     = 0xE208,
 137         AARCH64_INSN_SPCLREG_SPSR_INQ   = 0xE218,
 138         AARCH64_INSN_SPCLREG_SPSR_ABT   = 0xE219,
 139         AARCH64_INSN_SPCLREG_SPSR_UND   = 0xE21A,
 140         AARCH64_INSN_SPCLREG_SPSR_FIQ   = 0xE21B,
 141         AARCH64_INSN_SPCLREG_SPSR_EL3   = 0xF200,
 142         AARCH64_INSN_SPCLREG_ELR_EL3    = 0xF201,
 143         AARCH64_INSN_SPCLREG_SP_EL2     = 0xF210
 144 };
 145
 146 enum aarch64_insn_variant {
 147         AARCH64_INSN_VARIANT_32BIT,
 148         AARCH64_INSN_VARIANT_64BIT
 149 };
 150
 151 enum aarch64_insn_condition {
 152         AARCH64_INSN_COND_EQ = 0x0, /* == */
 153         AARCH64_INSN_COND_NE = 0x1, /* != */
 154         AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
 155         AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
 156         AARCH64_INSN_COND_MI = 0x4, /* < 0 */
 157         AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
 158         AARCH64_INSN_COND_VS = 0x6, /* overflow */
 159         AARCH64_INSN_COND_VC = 0x7, /* no overflow */
 160         AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
 161         AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
 162         AARCH64_INSN_COND_GE = 0xa, /* signed >= */
 163         AARCH64_INSN_COND_LT = 0xb, /* signed < */
 164         AARCH64_INSN_COND_GT = 0xc, /* signed > */
 165         AARCH64_INSN_COND_LE = 0xd, /* signed <= */
 166         AARCH64_INSN_COND_AL = 0xe, /* always */
 167 };
 168
 169 enum aarch64_insn_branch_type {
 170         AARCH64_INSN_BRANCH_NOLINK,
 171         AARCH64_INSN_BRANCH_LINK,
 172         AARCH64_INSN_BRANCH_RETURN,
 173         AARCH64_INSN_BRANCH_COMP_ZERO,
 174         AARCH64_INSN_BRANCH_COMP_NONZERO,
 175 };
 176
 177 enum aarch64_insn_size_type {
 178         AARCH64_INSN_SIZE_8,
 179         AARCH64_INSN_SIZE_16,
 180         AARCH64_INSN_SIZE_32,
 181         AARCH64_INSN_SIZE_64,
 182 };
 183
 184 enum aarch64_insn_ldst_type {
 185         AARCH64_INSN_LDST_LOAD_REG_OFFSET,
 186         AARCH64_INSN_LDST_STORE_REG_OFFSET,
 187         AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
 188         AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
 189         AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
 190         AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
 191 };
 192
 193 enum aarch64_insn_adsb_type {
 194         AARCH64_INSN_ADSB_ADD,
 195         AARCH64_INSN_ADSB_SUB,
 196         AARCH64_INSN_ADSB_ADD_SETFLAGS,
 197         AARCH64_INSN_ADSB_SUB_SETFLAGS
 198 };
 199
 200 enum aarch64_insn_movewide_type {
 201         AARCH64_INSN_MOVEWIDE_ZERO,
 202         AARCH64_INSN_MOVEWIDE_KEEP,
 203         AARCH64_INSN_MOVEWIDE_INVERSE
 204 };
 205
 206 enum aarch64_insn_bitfield_type {
 207         AARCH64_INSN_BITFIELD_MOVE,
 208         AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
 209         AARCH64_INSN_BITFIELD_MOVE_SIGNED
 210 };
 211
 212 enum aarch64_insn_data1_type {
 213         AARCH64_INSN_DATA1_REVERSE_16,
 214         AARCH64_INSN_DATA1_REVERSE_32,
 215         AARCH64_INSN_DATA1_REVERSE_64,
 216 };
 217
 218 enum aarch64_insn_data2_type {
 219         AARCH64_INSN_DATA2_UDIV,
 220         AARCH64_INSN_DATA2_SDIV,
 221         AARCH64_INSN_DATA2_LSLV,
 222         AARCH64_INSN_DATA2_LSRV,
 223         AARCH64_INSN_DATA2_ASRV,
 224         AARCH64_INSN_DATA2_RORV,
 225 };
 226
 227 enum aarch64_insn_data3_type {
 228         AARCH64_INSN_DATA3_MADD,
 229         AARCH64_INSN_DATA3_MSUB,
 230 };
 231
 232 enum aarch64_insn_logic_type {
 233         AARCH64_INSN_LOGIC_AND,
 234         AARCH64_INSN_LOGIC_BIC,
 235         AARCH64_INSN_LOGIC_ORR,
 236         AARCH64_INSN_LOGIC_ORN,
 237         AARCH64_INSN_LOGIC_EOR,
 238         AARCH64_INSN_LOGIC_EON,
 239         AARCH64_INSN_LOGIC_AND_SETFLAGS,
 240         AARCH64_INSN_LOGIC_BIC_SETFLAGS
 241 };
 242
 243 #define __AARCH64_INSN_FUNCS(abbr, mask, val)   \
 244 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \
 245 { return (code & (mask)) == (val); } \
 246 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \
 247 { return (val); }
 248
 249 __AARCH64_INSN_FUNCS(adr_adrp,  0x1F000000, 0x10000000)
 250 __AARCH64_INSN_FUNCS(prfm_lit,  0xFF000000, 0xD8000000)
 251 __AARCH64_INSN_FUNCS(str_reg,   0x3FE0EC00, 0x38206800)
 252 __AARCH64_INSN_FUNCS(ldr_reg,   0x3FE0EC00, 0x38606800)
 253 __AARCH64_INSN_FUNCS(ldr_lit,   0xBF000000, 0x18000000)
 254 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
 255 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
 256 __AARCH64_INSN_FUNCS(load_ex,   0x3F400000, 0x08400000)
 257 __AARCH64_INSN_FUNCS(store_ex,  0x3F400000, 0x08000000)
 258 __AARCH64_INSN_FUNCS(stp_post,  0x7FC00000, 0x28800000)
 259 __AARCH64_INSN_FUNCS(ldp_post,  0x7FC00000, 0x28C00000)
 260 __AARCH64_INSN_FUNCS(stp_pre,   0x7FC00000, 0x29800000)
 261 __AARCH64_INSN_FUNCS(ldp_pre,   0x7FC00000, 0x29C00000)
 262 __AARCH64_INSN_FUNCS(add_imm,   0x7F000000, 0x11000000)
 263 __AARCH64_INSN_FUNCS(adds_imm,  0x7F000000, 0x31000000)
 264 __AARCH64_INSN_FUNCS(sub_imm,   0x7F000000, 0x51000000)
 265 __AARCH64_INSN_FUNCS(subs_imm,  0x7F000000, 0x71000000)
 266 __AARCH64_INSN_FUNCS(movn,      0x7F800000, 0x12800000)
 267 __AARCH64_INSN_FUNCS(sbfm,      0x7F800000, 0x13000000)
 268 __AARCH64_INSN_FUNCS(bfm,       0x7F800000, 0x33000000)
 269 __AARCH64_INSN_FUNCS(movz,      0x7F800000, 0x52800000)
 270 __AARCH64_INSN_FUNCS(ubfm,      0x7F800000, 0x53000000)
 271 __AARCH64_INSN_FUNCS(movk,      0x7F800000, 0x72800000)
 272 __AARCH64_INSN_FUNCS(add,       0x7F200000, 0x0B000000)
 273 __AARCH64_INSN_FUNCS(adds,      0x7F200000, 0x2B000000)
 274 __AARCH64_INSN_FUNCS(sub,       0x7F200000, 0x4B000000)
 275 __AARCH64_INSN_FUNCS(subs,      0x7F200000, 0x6B000000)
 276 __AARCH64_INSN_FUNCS(madd,      0x7FE08000, 0x1B000000)
 277 __AARCH64_INSN_FUNCS(msub,      0x7FE08000, 0x1B008000)
 278 __AARCH64_INSN_FUNCS(udiv,      0x7FE0FC00, 0x1AC00800)
 279 __AARCH64_INSN_FUNCS(sdiv,      0x7FE0FC00, 0x1AC00C00)
 280 __AARCH64_INSN_FUNCS(lslv,      0x7FE0FC00, 0x1AC02000)
 281 __AARCH64_INSN_FUNCS(lsrv,      0x7FE0FC00, 0x1AC02400)
 282 __AARCH64_INSN_FUNCS(asrv,      0x7FE0FC00, 0x1AC02800)
 283 __AARCH64_INSN_FUNCS(rorv,      0x7FE0FC00, 0x1AC02C00)
 284 __AARCH64_INSN_FUNCS(rev16,     0x7FFFFC00, 0x5AC00400)
 285 __AARCH64_INSN_FUNCS(rev32,     0x7FFFFC00, 0x5AC00800)
 286 __AARCH64_INSN_FUNCS(rev64,     0x7FFFFC00, 0x5AC00C00)
 287 __AARCH64_INSN_FUNCS(and,       0x7F200000, 0x0A000000)
 288 __AARCH64_INSN_FUNCS(bic,       0x7F200000, 0x0A200000)
 289 __AARCH64_INSN_FUNCS(orr,       0x7F200000, 0x2A000000)
 290 __AARCH64_INSN_FUNCS(orn,       0x7F200000, 0x2A200000)
 291 __AARCH64_INSN_FUNCS(eor,       0x7F200000, 0x4A000000)
 292 __AARCH64_INSN_FUNCS(eon,       0x7F200000, 0x4A200000)
 293 __AARCH64_INSN_FUNCS(ands,      0x7F200000, 0x6A000000)
 294 __AARCH64_INSN_FUNCS(bics,      0x7F200000, 0x6A200000)
 295 __AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
 296 __AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
 297 __AARCH64_INSN_FUNCS(cbz,       0x7F000000, 0x34000000)
 298 __AARCH64_INSN_FUNCS(cbnz,      0x7F000000, 0x35000000)
 299 __AARCH64_INSN_FUNCS(tbz,       0x7F000000, 0x36000000)
 300 __AARCH64_INSN_FUNCS(tbnz,      0x7F000000, 0x37000000)
 301 __AARCH64_INSN_FUNCS(bcond,     0xFF000010, 0x54000000)
 302 __AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
 303 __AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
 304 __AARCH64_INSN_FUNCS(smc,       0xFFE0001F, 0xD4000003)
 305 __AARCH64_INSN_FUNCS(brk,       0xFFE0001F, 0xD4200000)
 306 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
 307 __AARCH64_INSN_FUNCS(hint,      0xFFFFF01F, 0xD503201F)
 308 __AARCH64_INSN_FUNCS(br,        0xFFFFFC1F, 0xD61F0000)
 309 __AARCH64_INSN_FUNCS(blr,       0xFFFFFC1F, 0xD63F0000)
 310 __AARCH64_INSN_FUNCS(ret,       0xFFFFFC1F, 0xD65F0000)
 311 __AARCH64_INSN_FUNCS(eret,      0xFFFFFFFF, 0xD69F03E0)
 312 __AARCH64_INSN_FUNCS(mrs,       0xFFF00000, 0xD5300000)
 313 __AARCH64_INSN_FUNCS(msr_imm,   0xFFF8F01F, 0xD500401F)
 314 __AARCH64_INSN_FUNCS(msr_reg,   0xFFF00000, 0xD5100000)
 315
 316 #undef  __AARCH64_INSN_FUNCS
 317
 318 bool aarch64_insn_is_nop(u32 insn);
 319 bool aarch64_insn_is_branch_imm(u32 insn);
 320
 321 int aarch64_insn_read(void *addr, u32 *insnp);
 322 int aarch64_insn_write(void *addr, u32 insn);
 323 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
 324 bool aarch64_insn_uses_literal(u32 insn);
 325 bool aarch64_insn_is_branch(u32 insn);
 326 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
 327 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
 328                                   u32 insn, u64 imm);
 329 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
 330                                 enum aarch64_insn_branch_type type);
 331 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
 332                                      enum aarch64_insn_register reg,
 333                                      enum aarch64_insn_variant variant,
 334                                      enum aarch64_insn_branch_type type);
 335 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
 336                                      enum aarch64_insn_condition cond);
 337 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op);
 338 u32 aarch64_insn_gen_nop(void);
 339 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
 340                                 enum aarch64_insn_branch_type type);
 341 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
 342                                     enum aarch64_insn_register base,
 343                                     enum aarch64_insn_register offset,
 344                                     enum aarch64_insn_size_type size,
 345                                     enum aarch64_insn_ldst_type type);
 346 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
 347                                      enum aarch64_insn_register reg2,
 348                                      enum aarch64_insn_register base,
 349                                      int offset,
 350                                      enum aarch64_insn_variant variant,
 351                                      enum aarch64_insn_ldst_type type);
 352 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
 353                                  enum aarch64_insn_register src,
 354                                  int imm, enum aarch64_insn_variant variant,
 355                                  enum aarch64_insn_adsb_type type);
 356 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
 357                               enum aarch64_insn_register src,
 358                               int immr, int imms,
 359                               enum aarch64_insn_variant variant,
 360                               enum aarch64_insn_bitfield_type type);
 361 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
 362                               int imm, int shift,
 363                               enum aarch64_insn_variant variant,
 364                               enum aarch64_insn_movewide_type type);
 365 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
 366                                          enum aarch64_insn_register src,
 367                                          enum aarch64_insn_register reg,
 368                                          int shift,
 369                                          enum aarch64_insn_variant variant,
 370                                          enum aarch64_insn_adsb_type type);
 371 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
 372                            enum aarch64_insn_register src,
 373                            enum aarch64_insn_variant variant,
 374                            enum aarch64_insn_data1_type type);
 375 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
 376                            enum aarch64_insn_register src,
 377                            enum aarch64_insn_register reg,
 378                            enum aarch64_insn_variant variant,
 379                            enum aarch64_insn_data2_type type);
 380 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
 381                            enum aarch64_insn_register src,
 382                            enum aarch64_insn_register reg1,
 383                            enum aarch64_insn_register reg2,
 384                            enum aarch64_insn_variant variant,
 385                            enum aarch64_insn_data3_type type);
 386 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
 387                                          enum aarch64_insn_register src,
 388                                          enum aarch64_insn_register reg,
 389                                          int shift,
 390                                          enum aarch64_insn_variant variant,
 391                                          enum aarch64_insn_logic_type type);
 392 s32 aarch64_get_branch_offset(u32 insn);
 393 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
 394
 395 bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn);
 396
 397 int aarch64_insn_patch_text_nosync(void *addr, u32 insn);
 398 int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt);
 399 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt);
 400
 401 bool aarch32_insn_is_wide(u32 insn);
 402
 403 #define A32_RN_OFFSET   16
 404 #define A32_RT_OFFSET   12
 405 #define A32_RT2_OFFSET   0
 406
 407 u32 aarch64_insn_extract_system_reg(u32 insn);
 408 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
 409 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
 410 u32 aarch32_insn_mcr_extract_crm(u32 insn);
 411
 412 typedef bool (pstate_check_t)(unsigned long);
 413 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
 414 #endif /* __ASSEMBLY__ */
 415
 416 #endif  /* __ASM_INSN_H */