Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
[sfrench/cifs-2.6.git] / arch / arm64 / boot / dts / ti / k3-am65-main.dtsi
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Device Tree Source for AM6 SoC Family Main Domain peripherals
4  *
5  * Copyright (C) 2016-2018 Texas Instruments Incorporated - http://www.ti.com/
6  */
7 #include <dt-bindings/phy/phy-am654-serdes.h>
8
9 &cbass_main {
10         msmc_ram: sram@70000000 {
11                 compatible = "mmio-sram";
12                 reg = <0x0 0x70000000 0x0 0x200000>;
13                 #address-cells = <1>;
14                 #size-cells = <1>;
15                 ranges = <0x0 0x0 0x70000000 0x200000>;
16
17                 atf-sram@0 {
18                         reg = <0x0 0x20000>;
19                 };
20
21                 sysfw-sram@f0000 {
22                         reg = <0xf0000 0x10000>;
23                 };
24
25                 l3cache-sram@100000 {
26                         reg = <0x100000 0x100000>;
27                 };
28         };
29
30         gic500: interrupt-controller@1800000 {
31                 compatible = "arm,gic-v3";
32                 #address-cells = <2>;
33                 #size-cells = <2>;
34                 ranges;
35                 #interrupt-cells = <3>;
36                 interrupt-controller;
37                 reg = <0x00 0x01800000 0x00 0x10000>,   /* GICD */
38                       <0x00 0x01880000 0x00 0x90000>;   /* GICR */
39                 /*
40                  * vcpumntirq:
41                  * virtual CPU interface maintenance interrupt
42                  */
43                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
44
45                 gic_its: gic-its@18200000 {
46                         compatible = "arm,gic-v3-its";
47                         reg = <0x00 0x01820000 0x00 0x10000>;
48                         socionext,synquacer-pre-its = <0x1000000 0x400000>;
49                         msi-controller;
50                         #msi-cells = <1>;
51                 };
52         };
53
54         secure_proxy_main: mailbox@32c00000 {
55                 compatible = "ti,am654-secure-proxy";
56                 #mbox-cells = <1>;
57                 reg-names = "target_data", "rt", "scfg";
58                 reg = <0x00 0x32c00000 0x00 0x100000>,
59                       <0x00 0x32400000 0x00 0x100000>,
60                       <0x00 0x32800000 0x00 0x100000>;
61                 interrupt-names = "rx_011";
62                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
63         };
64
65         serdes0: serdes@900000 {
66                 compatible = "ti,phy-am654-serdes";
67                 reg = <0x0 0x900000 0x0 0x2000>;
68                 reg-names = "serdes";
69                 #phy-cells = <2>;
70                 power-domains = <&k3_pds 153>;
71                 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>;
72                 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk";
73                 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>;
74                 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>;
75                 ti,serdes-clk = <&serdes0_clk>;
76                 #clock-cells = <1>;
77                 mux-controls = <&serdes_mux 0>;
78         };
79
80         serdes1: serdes@910000 {
81                 compatible = "ti,phy-am654-serdes";
82                 reg = <0x0 0x910000 0x0 0x2000>;
83                 reg-names = "serdes";
84                 #phy-cells = <2>;
85                 power-domains = <&k3_pds 154>;
86                 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>;
87                 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk";
88                 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>;
89                 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>;
90                 ti,serdes-clk = <&serdes1_clk>;
91                 #clock-cells = <1>;
92                 mux-controls = <&serdes_mux 1>;
93         };
94
95         main_uart0: serial@2800000 {
96                 compatible = "ti,am654-uart";
97                 reg = <0x00 0x02800000 0x00 0x100>;
98                 reg-shift = <2>;
99                 reg-io-width = <4>;
100                 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
101                 clock-frequency = <48000000>;
102                 current-speed = <115200>;
103                 power-domains = <&k3_pds 146>;
104         };
105
106         main_uart1: serial@2810000 {
107                 compatible = "ti,am654-uart";
108                 reg = <0x00 0x02810000 0x00 0x100>;
109                 reg-shift = <2>;
110                 reg-io-width = <4>;
111                 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
112                 clock-frequency = <48000000>;
113                 power-domains = <&k3_pds 147>;
114         };
115
116         main_uart2: serial@2820000 {
117                 compatible = "ti,am654-uart";
118                 reg = <0x00 0x02820000 0x00 0x100>;
119                 reg-shift = <2>;
120                 reg-io-width = <4>;
121                 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
122                 clock-frequency = <48000000>;
123                 power-domains = <&k3_pds 148>;
124         };
125
126         main_pmx0: pinmux@11c000 {
127                 compatible = "pinctrl-single";
128                 reg = <0x0 0x11c000 0x0 0x2e4>;
129                 #pinctrl-cells = <1>;
130                 pinctrl-single,register-width = <32>;
131                 pinctrl-single,function-mask = <0xffffffff>;
132         };
133
134         main_pmx1: pinmux@11c2e8 {
135                 compatible = "pinctrl-single";
136                 reg = <0x0 0x11c2e8 0x0 0x24>;
137                 #pinctrl-cells = <1>;
138                 pinctrl-single,register-width = <32>;
139                 pinctrl-single,function-mask = <0xffffffff>;
140         };
141
142         main_i2c0: i2c@2000000 {
143                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
144                 reg = <0x0 0x2000000 0x0 0x100>;
145                 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
146                 #address-cells = <1>;
147                 #size-cells = <0>;
148                 clock-names = "fck";
149                 clocks = <&k3_clks 110 1>;
150                 power-domains = <&k3_pds 110>;
151         };
152
153         main_i2c1: i2c@2010000 {
154                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
155                 reg = <0x0 0x2010000 0x0 0x100>;
156                 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
157                 #address-cells = <1>;
158                 #size-cells = <0>;
159                 clock-names = "fck";
160                 clocks = <&k3_clks 111 1>;
161                 power-domains = <&k3_pds 111>;
162         };
163
164         main_i2c2: i2c@2020000 {
165                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
166                 reg = <0x0 0x2020000 0x0 0x100>;
167                 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
168                 #address-cells = <1>;
169                 #size-cells = <0>;
170                 clock-names = "fck";
171                 clocks = <&k3_clks 112 1>;
172                 power-domains = <&k3_pds 112>;
173         };
174
175         main_i2c3: i2c@2030000 {
176                 compatible = "ti,am654-i2c", "ti,omap4-i2c";
177                 reg = <0x0 0x2030000 0x0 0x100>;
178                 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
179                 #address-cells = <1>;
180                 #size-cells = <0>;
181                 clock-names = "fck";
182                 clocks = <&k3_clks 113 1>;
183                 power-domains = <&k3_pds 113>;
184         };
185
186         ecap0: pwm@3100000 {
187                 compatible = "ti,am654-ecap", "ti,am3352-ecap";
188                 #pwm-cells = <3>;
189                 reg = <0x0 0x03100000 0x0 0x60>;
190                 power-domains = <&k3_pds 39>;
191                 clocks = <&k3_clks 39 0>;
192                 clock-names = "fck";
193         };
194
195         main_spi0: spi@2100000 {
196                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
197                 reg = <0x0 0x2100000 0x0 0x400>;
198                 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
199                 clocks = <&k3_clks 137 1>;
200                 power-domains = <&k3_pds 137>;
201                 #address-cells = <1>;
202                 #size-cells = <0>;
203         };
204
205         main_spi1: spi@2110000 {
206                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
207                 reg = <0x0 0x2110000 0x0 0x400>;
208                 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
209                 clocks = <&k3_clks 138 1>;
210                 power-domains = <&k3_pds 138>;
211                 #address-cells = <1>;
212                 #size-cells = <0>;
213                 assigned-clocks = <&k3_clks 137 1>;
214                 assigned-clock-rates = <48000000>;
215         };
216
217         main_spi2: spi@2120000 {
218                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
219                 reg = <0x0 0x2120000 0x0 0x400>;
220                 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
221                 clocks = <&k3_clks 139 1>;
222                 power-domains = <&k3_pds 139>;
223                 #address-cells = <1>;
224                 #size-cells = <0>;
225         };
226
227         main_spi3: spi@2130000 {
228                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
229                 reg = <0x0 0x2130000 0x0 0x400>;
230                 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
231                 clocks = <&k3_clks 140 1>;
232                 power-domains = <&k3_pds 140>;
233                 #address-cells = <1>;
234                 #size-cells = <0>;
235         };
236
237         main_spi4: spi@2140000 {
238                 compatible = "ti,am654-mcspi","ti,omap4-mcspi";
239                 reg = <0x0 0x2140000 0x0 0x400>;
240                 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
241                 clocks = <&k3_clks 141 1>;
242                 power-domains = <&k3_pds 141>;
243                 #address-cells = <1>;
244                 #size-cells = <0>;
245         };
246
247         sdhci0: sdhci@4f80000 {
248                 compatible = "ti,am654-sdhci-5.1";
249                 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
250                 power-domains = <&k3_pds 47>;
251                 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
252                 clock-names = "clk_ahb", "clk_xin";
253                 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
254                 mmc-ddr-1_8v;
255                 mmc-hs200-1_8v;
256                 ti,otap-del-sel = <0x2>;
257                 ti,trm-icp = <0x8>;
258                 dma-coherent;
259         };
260
261         scm_conf: scm_conf@100000 {
262                 compatible = "syscon", "simple-mfd";
263                 reg = <0 0x00100000 0 0x1c000>;
264                 #address-cells = <1>;
265                 #size-cells = <1>;
266                 ranges = <0x0 0x0 0x00100000 0x1c000>;
267
268                 pcie0_mode: pcie-mode@4060 {
269                         compatible = "syscon";
270                         reg = <0x00004060 0x4>;
271                 };
272
273                 pcie1_mode: pcie-mode@4070 {
274                         compatible = "syscon";
275                         reg = <0x00004070 0x4>;
276                 };
277
278                 pcie_devid: pcie-devid@210 {
279                         compatible = "syscon";
280                         reg = <0x00000210 0x4>;
281                 };
282
283                 serdes0_clk: serdes_clk@4080 {
284                         compatible = "syscon";
285                         reg = <0x00004080 0x4>;
286                 };
287
288                 serdes1_clk: serdes_clk@4090 {
289                         compatible = "syscon";
290                         reg = <0x00004090 0x4>;
291                 };
292
293                 serdes_mux: mux-controller {
294                         compatible = "mmio-mux";
295                         #mux-control-cells = <1>;
296                         mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
297                                         <0x4090 0x3>; /* SERDES1 lane select */
298                 };
299         };
300
301         dwc3_0: dwc3@4000000 {
302                 compatible = "ti,am654-dwc3";
303                 reg = <0x0 0x4000000 0x0 0x4000>;
304                 #address-cells = <1>;
305                 #size-cells = <1>;
306                 ranges = <0x0 0x0 0x4000000 0x20000>;
307                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
308                 dma-coherent;
309                 power-domains = <&k3_pds 151>;
310                 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>;
311                 assigned-clock-parents = <&k3_clks 151 4>,      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
312                                          <&k3_clks 151 9>;      /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */
313
314                 usb0: usb@10000 {
315                         compatible = "snps,dwc3";
316                         reg = <0x10000 0x10000>;
317                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
318                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
319                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
320                         interrupt-names = "peripheral",
321                                           "host",
322                                           "otg";
323                         maximum-speed = "high-speed";
324                         dr_mode = "otg";
325                         phys = <&usb0_phy>;
326                         phy-names = "usb2-phy";
327                         snps,dis_u3_susphy_quirk;
328                 };
329         };
330
331         usb0_phy: phy@4100000 {
332                 compatible = "ti,am654-usb2", "ti,omap-usb2";
333                 reg = <0x0 0x4100000 0x0 0x54>;
334                 syscon-phy-power = <&scm_conf 0x4000>;
335                 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>;
336                 clock-names = "wkupclk", "refclk";
337                 #phy-cells = <0>;
338         };
339
340         dwc3_1: dwc3@4020000 {
341                 compatible = "ti,am654-dwc3";
342                 reg = <0x0 0x4020000 0x0 0x4000>;
343                 #address-cells = <1>;
344                 #size-cells = <1>;
345                 ranges = <0x0 0x0 0x4020000 0x20000>;
346                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
347                 dma-coherent;
348                 power-domains = <&k3_pds 152>;
349                 assigned-clocks = <&k3_clks 152 2>;
350                 assigned-clock-parents = <&k3_clks 152 4>;      /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
351
352                 usb1: usb@10000 {
353                         compatible = "snps,dwc3";
354                         reg = <0x10000 0x10000>;
355                         interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
356                                      <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
357                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
358                         interrupt-names = "peripheral",
359                                           "host",
360                                           "otg";
361                         maximum-speed = "high-speed";
362                         dr_mode = "otg";
363                         phys = <&usb1_phy>;
364                         phy-names = "usb2-phy";
365                 };
366         };
367
368         usb1_phy: phy@4110000 {
369                 compatible = "ti,am654-usb2", "ti,omap-usb2";
370                 reg = <0x0 0x4110000 0x0 0x54>;
371                 syscon-phy-power = <&scm_conf 0x4020>;
372                 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>;
373                 clock-names = "wkupclk", "refclk";
374                 #phy-cells = <0>;
375         };
376
377         intr_main_gpio: interrupt-controller0 {
378                 compatible = "ti,sci-intr";
379                 ti,intr-trigger-type = <1>;
380                 interrupt-controller;
381                 interrupt-parent = <&gic500>;
382                 #interrupt-cells = <2>;
383                 ti,sci = <&dmsc>;
384                 ti,sci-dst-id = <56>;
385                 ti,sci-rm-range-girq = <0x1>;
386         };
387
388         cbass_main_navss: interconnect0 {
389                 compatible = "simple-bus";
390                 #address-cells = <2>;
391                 #size-cells = <2>;
392                 ranges;
393
394                 intr_main_navss: interrupt-controller1 {
395                         compatible = "ti,sci-intr";
396                         ti,intr-trigger-type = <4>;
397                         interrupt-controller;
398                         interrupt-parent = <&gic500>;
399                         #interrupt-cells = <2>;
400                         ti,sci = <&dmsc>;
401                         ti,sci-dst-id = <56>;
402                         ti,sci-rm-range-girq = <0x0>, <0x2>;
403                 };
404
405                 inta_main_udmass: interrupt-controller@33d00000 {
406                         compatible = "ti,sci-inta";
407                         reg = <0x0 0x33d00000 0x0 0x100000>;
408                         interrupt-controller;
409                         interrupt-parent = <&intr_main_navss>;
410                         msi-controller;
411                         ti,sci = <&dmsc>;
412                         ti,sci-dev-id = <179>;
413                         ti,sci-rm-range-vint = <0x0>;
414                         ti,sci-rm-range-global-event = <0x1>;
415                 };
416         };
417
418         main_gpio0:  main_gpio0@600000 {
419                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
420                 reg = <0x0 0x600000 0x0 0x100>;
421                 gpio-controller;
422                 #gpio-cells = <2>;
423                 interrupt-parent = <&intr_main_gpio>;
424                 interrupts = <57 256>, <57 257>, <57 258>, <57 259>, <57 260>,
425                                 <57 261>;
426                 interrupt-controller;
427                 #interrupt-cells = <2>;
428                 ti,ngpio = <96>;
429                 ti,davinci-gpio-unbanked = <0>;
430                 clocks = <&k3_clks 57 0>;
431                 clock-names = "gpio";
432         };
433
434         main_gpio1:  main_gpio1@601000 {
435                 compatible = "ti,am654-gpio", "ti,keystone-gpio";
436                 reg = <0x0 0x601000 0x0 0x100>;
437                 gpio-controller;
438                 #gpio-cells = <2>;
439                 interrupt-parent = <&intr_main_gpio>;
440                 interrupts = <58 256>, <58 257>, <58 258>, <58 259>, <58 260>,
441                                 <58 261>;
442                 interrupt-controller;
443                 #interrupt-cells = <2>;
444                 ti,ngpio = <90>;
445                 ti,davinci-gpio-unbanked = <0>;
446                 clocks = <&k3_clks 58 0>;
447                 clock-names = "gpio";
448         };
449
450         pcie0_rc: pcie@5500000 {
451                 compatible = "ti,am654-pcie-rc";
452                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>;
453                 reg-names = "app", "dbics", "config", "atu";
454                 power-domains = <&k3_pds 120>;
455                 #address-cells = <3>;
456                 #size-cells = <2>;
457                 ranges = <0x81000000 0 0          0x0 0x10020000 0 0x00010000
458                           0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>;
459                 ti,syscon-pcie-id = <&pcie_devid>;
460                 ti,syscon-pcie-mode = <&pcie0_mode>;
461                 bus-range = <0x0 0xff>;
462                 num-viewport = <16>;
463                 max-link-speed = <3>;
464                 dma-coherent;
465                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
466                 msi-map = <0x0 &gic_its 0x0 0x10000>;
467         };
468
469         pcie0_ep: pcie-ep@5500000 {
470                 compatible = "ti,am654-pcie-ep";
471                 reg =  <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>;
472                 reg-names = "app", "dbics", "addr_space", "atu";
473                 power-domains = <&k3_pds 120>;
474                 ti,syscon-pcie-mode = <&pcie0_mode>;
475                 num-ib-windows = <16>;
476                 num-ob-windows = <16>;
477                 max-link-speed = <3>;
478                 dma-coherent;
479                 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
480         };
481
482         pcie1_rc: pcie@5600000 {
483                 compatible = "ti,am654-pcie-rc";
484                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>;
485                 reg-names = "app", "dbics", "config", "atu";
486                 power-domains = <&k3_pds 121>;
487                 #address-cells = <3>;
488                 #size-cells = <2>;
489                 ranges = <0x81000000 0 0          0x0   0x18020000 0 0x00010000
490                           0x82000000 0 0x18030000 0x0   0x18030000 0 0x07FD0000>;
491                 ti,syscon-pcie-id = <&pcie_devid>;
492                 ti,syscon-pcie-mode = <&pcie1_mode>;
493                 bus-range = <0x0 0xff>;
494                 num-viewport = <16>;
495                 max-link-speed = <3>;
496                 dma-coherent;
497                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
498                 msi-map = <0x0 &gic_its 0x10000 0x10000>;
499         };
500
501         pcie1_ep: pcie-ep@5600000 {
502                 compatible = "ti,am654-pcie-ep";
503                 reg =  <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>;
504                 reg-names = "app", "dbics", "addr_space", "atu";
505                 power-domains = <&k3_pds 121>;
506                 ti,syscon-pcie-mode = <&pcie1_mode>;
507                 num-ib-windows = <16>;
508                 num-ob-windows = <16>;
509                 max-link-speed = <3>;
510                 dma-coherent;
511                 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>;
512         };
513 };