arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD11 SoC
   4 //
   5 // Copyright (C) 2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10
  11 /memreserve/ 0x80000000 0x02000000;
  12
  13 / {
  14         compatible = "socionext,uniphier-ld11";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32                 };
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         reg = <0 0x000>;
  38                         clocks = <&sys_clk 33>;
  39                         enable-method = "psci";
  40                         operating-points-v2 = <&cluster0_opp>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53", "arm,armv8";
  46                         reg = <0 0x001>;
  47                         clocks = <&sys_clk 33>;
  48                         enable-method = "psci";
  49                         operating-points-v2 = <&cluster0_opp>;
  50                 };
  51         };
  52
  53         cluster0_opp: opp-table {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56
  57                 opp-245000000 {
  58                         opp-hz = /bits/ 64 <245000000>;
  59                         clock-latency-ns = <300>;
  60                 };
  61                 opp-250000000 {
  62                         opp-hz = /bits/ 64 <250000000>;
  63                         clock-latency-ns = <300>;
  64                 };
  65                 opp-490000000 {
  66                         opp-hz = /bits/ 64 <490000000>;
  67                         clock-latency-ns = <300>;
  68                 };
  69                 opp-500000000 {
  70                         opp-hz = /bits/ 64 <500000000>;
  71                         clock-latency-ns = <300>;
  72                 };
  73                 opp-653334000 {
  74                         opp-hz = /bits/ 64 <653334000>;
  75                         clock-latency-ns = <300>;
  76                 };
  77                 opp-666667000 {
  78                         opp-hz = /bits/ 64 <666667000>;
  79                         clock-latency-ns = <300>;
  80                 };
  81                 opp-980000000 {
  82                         opp-hz = /bits/ 64 <980000000>;
  83                         clock-latency-ns = <300>;
  84                 };
  85         };
  86
  87         psci {
  88                 compatible = "arm,psci-1.0";
  89                 method = "smc";
  90         };
  91
  92         clocks {
  93                 refclk: ref {
  94                         compatible = "fixed-clock";
  95                         #clock-cells = <0>;
  96                         clock-frequency = <25000000>;
  97                 };
  98         };
  99
 100         emmc_pwrseq: emmc-pwrseq {
 101                 compatible = "mmc-pwrseq-emmc";
 102                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv8-timer";
 107                 interrupts = <1 13 4>,
 108                              <1 14 4>,
 109                              <1 11 4>,
 110                              <1 10 4>;
 111         };
 112
 113         soc@0 {
 114                 compatible = "simple-bus";
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 ranges = <0 0 0 0xffffffff>;
 118
 119                 serial0: serial@54006800 {
 120                         compatible = "socionext,uniphier-uart";
 121                         status = "disabled";
 122                         reg = <0x54006800 0x40>;
 123                         interrupts = <0 33 4>;
 124                         pinctrl-names = "default";
 125                         pinctrl-0 = <&pinctrl_uart0>;
 126                         clocks = <&peri_clk 0>;
 127                         resets = <&peri_rst 0>;
 128                 };
 129
 130                 serial1: serial@54006900 {
 131                         compatible = "socionext,uniphier-uart";
 132                         status = "disabled";
 133                         reg = <0x54006900 0x40>;
 134                         interrupts = <0 35 4>;
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&pinctrl_uart1>;
 137                         clocks = <&peri_clk 1>;
 138                         resets = <&peri_rst 1>;
 139                 };
 140
 141                 serial2: serial@54006a00 {
 142                         compatible = "socionext,uniphier-uart";
 143                         status = "disabled";
 144                         reg = <0x54006a00 0x40>;
 145                         interrupts = <0 37 4>;
 146                         pinctrl-names = "default";
 147                         pinctrl-0 = <&pinctrl_uart2>;
 148                         clocks = <&peri_clk 2>;
 149                         resets = <&peri_rst 2>;
 150                 };
 151
 152                 serial3: serial@54006b00 {
 153                         compatible = "socionext,uniphier-uart";
 154                         status = "disabled";
 155                         reg = <0x54006b00 0x40>;
 156                         interrupts = <0 177 4>;
 157                         pinctrl-names = "default";
 158                         pinctrl-0 = <&pinctrl_uart3>;
 159                         clocks = <&peri_clk 3>;
 160                         resets = <&peri_rst 3>;
 161                 };
 162
 163                 gpio: gpio@55000000 {
 164                         compatible = "socionext,uniphier-gpio";
 165                         reg = <0x55000000 0x200>;
 166                         interrupt-parent = <&aidet>;
 167                         interrupt-controller;
 168                         #interrupt-cells = <2>;
 169                         gpio-controller;
 170                         #gpio-cells = <2>;
 171                         gpio-ranges = <&pinctrl 0 0 0>,
 172                                       <&pinctrl 43 0 0>,
 173                                       <&pinctrl 51 0 0>,
 174                                       <&pinctrl 96 0 0>,
 175                                       <&pinctrl 160 0 0>,
 176                                       <&pinctrl 184 0 0>;
 177                         gpio-ranges-group-names = "gpio_range0",
 178                                                   "gpio_range1",
 179                                                   "gpio_range2",
 180                                                   "gpio_range3",
 181                                                   "gpio_range4",
 182                                                   "gpio_range5";
 183                         ngpios = <200>;
 184                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 185                                                      <21 217 3>;
 186                 };
 187
 188                 audio@56000000 {
 189                         compatible = "socionext,uniphier-ld11-aio";
 190                         reg = <0x56000000 0x80000>;
 191                         interrupts = <0 144 4>;
 192                         pinctrl-names = "default";
 193                         pinctrl-0 = <&pinctrl_aout1>,
 194                                     <&pinctrl_aoutiec1>;
 195                         clock-names = "aio";
 196                         clocks = <&sys_clk 40>;
 197                         reset-names = "aio";
 198                         resets = <&sys_rst 40>;
 199                         #sound-dai-cells = <1>;
 200                         socionext,syscon = <&soc_glue>;
 201
 202                         i2s_port0: port@0 {
 203                                 i2s_hdmi: endpoint {
 204                                 };
 205                         };
 206
 207                         i2s_port1: port@1 {
 208                                 i2s_pcmin2: endpoint {
 209                                 };
 210                         };
 211
 212                         i2s_port2: port@2 {
 213                                 i2s_line: endpoint {
 214                                         dai-format = "i2s";
 215                                         remote-endpoint = <&evea_line>;
 216                                 };
 217                         };
 218
 219                         i2s_port3: port@3 {
 220                                 i2s_hpcmout1: endpoint {
 221                                 };
 222                         };
 223
 224                         i2s_port4: port@4 {
 225                                 i2s_hp: endpoint {
 226                                         dai-format = "i2s";
 227                                         remote-endpoint = <&evea_hp>;
 228                                 };
 229                         };
 230
 231                         spdif_port0: port@5 {
 232                                 spdif_hiecout1: endpoint {
 233                                 };
 234                         };
 235
 236                         src_port0: port@6 {
 237                                 i2s_epcmout2: endpoint {
 238                                 };
 239                         };
 240
 241                         src_port1: port@7 {
 242                                 i2s_epcmout3: endpoint {
 243                                 };
 244                         };
 245
 246                         comp_spdif_port0: port@8 {
 247                                 comp_spdif_hiecout1: endpoint {
 248                                 };
 249                         };
 250                 };
 251
 252                 codec@57900000 {
 253                         compatible = "socionext,uniphier-evea";
 254                         reg = <0x57900000 0x1000>;
 255                         clock-names = "evea", "exiv";
 256                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 257                         reset-names = "evea", "exiv", "adamv";
 258                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 259                         #sound-dai-cells = <1>;
 260
 261                         port@0 {
 262                                 evea_line: endpoint {
 263                                         remote-endpoint = <&i2s_line>;
 264                                 };
 265                         };
 266
 267                         port@1 {
 268                                 evea_hp: endpoint {
 269                                         remote-endpoint = <&i2s_hp>;
 270                                 };
 271                         };
 272                 };
 273
 274                 adamv@57920000 {
 275                         compatible = "socionext,uniphier-ld11-adamv",
 276                                      "simple-mfd", "syscon";
 277                         reg = <0x57920000 0x1000>;
 278
 279                         adamv_rst: reset {
 280                                 compatible = "socionext,uniphier-ld11-adamv-reset";
 281                                 #reset-cells = <1>;
 282                         };
 283                 };
 284
 285                 i2c0: i2c@58780000 {
 286                         compatible = "socionext,uniphier-fi2c";
 287                         status = "disabled";
 288                         reg = <0x58780000 0x80>;
 289                         #address-cells = <1>;
 290                         #size-cells = <0>;
 291                         interrupts = <0 41 4>;
 292                         pinctrl-names = "default";
 293                         pinctrl-0 = <&pinctrl_i2c0>;
 294                         clocks = <&peri_clk 4>;
 295                         resets = <&peri_rst 4>;
 296                         clock-frequency = <100000>;
 297                 };
 298
 299                 i2c1: i2c@58781000 {
 300                         compatible = "socionext,uniphier-fi2c";
 301                         status = "disabled";
 302                         reg = <0x58781000 0x80>;
 303                         #address-cells = <1>;
 304                         #size-cells = <0>;
 305                         interrupts = <0 42 4>;
 306                         pinctrl-names = "default";
 307                         pinctrl-0 = <&pinctrl_i2c1>;
 308                         clocks = <&peri_clk 5>;
 309                         resets = <&peri_rst 5>;
 310                         clock-frequency = <100000>;
 311                 };
 312
 313                 i2c2: i2c@58782000 {
 314                         compatible = "socionext,uniphier-fi2c";
 315                         reg = <0x58782000 0x80>;
 316                         #address-cells = <1>;
 317                         #size-cells = <0>;
 318                         interrupts = <0 43 4>;
 319                         clocks = <&peri_clk 6>;
 320                         resets = <&peri_rst 6>;
 321                         clock-frequency = <400000>;
 322                 };
 323
 324                 i2c3: i2c@58783000 {
 325                         compatible = "socionext,uniphier-fi2c";
 326                         status = "disabled";
 327                         reg = <0x58783000 0x80>;
 328                         #address-cells = <1>;
 329                         #size-cells = <0>;
 330                         interrupts = <0 44 4>;
 331                         pinctrl-names = "default";
 332                         pinctrl-0 = <&pinctrl_i2c3>;
 333                         clocks = <&peri_clk 7>;
 334                         resets = <&peri_rst 7>;
 335                         clock-frequency = <100000>;
 336                 };
 337
 338                 i2c4: i2c@58784000 {
 339                         compatible = "socionext,uniphier-fi2c";
 340                         status = "disabled";
 341                         reg = <0x58784000 0x80>;
 342                         #address-cells = <1>;
 343                         #size-cells = <0>;
 344                         interrupts = <0 45 4>;
 345                         pinctrl-names = "default";
 346                         pinctrl-0 = <&pinctrl_i2c4>;
 347                         clocks = <&peri_clk 8>;
 348                         resets = <&peri_rst 8>;
 349                         clock-frequency = <100000>;
 350                 };
 351
 352                 i2c5: i2c@58785000 {
 353                         compatible = "socionext,uniphier-fi2c";
 354                         reg = <0x58785000 0x80>;
 355                         #address-cells = <1>;
 356                         #size-cells = <0>;
 357                         interrupts = <0 25 4>;
 358                         clocks = <&peri_clk 9>;
 359                         resets = <&peri_rst 9>;
 360                         clock-frequency = <400000>;
 361                 };
 362
 363                 system_bus: system-bus@58c00000 {
 364                         compatible = "socionext,uniphier-system-bus";
 365                         status = "disabled";
 366                         reg = <0x58c00000 0x400>;
 367                         #address-cells = <2>;
 368                         #size-cells = <1>;
 369                         pinctrl-names = "default";
 370                         pinctrl-0 = <&pinctrl_system_bus>;
 371                 };
 372
 373                 smpctrl@59801000 {
 374                         compatible = "socionext,uniphier-smpctrl";
 375                         reg = <0x59801000 0x400>;
 376                 };
 377
 378                 sdctrl@59810000 {
 379                         compatible = "socionext,uniphier-ld11-sdctrl",
 380                                      "simple-mfd", "syscon";
 381                         reg = <0x59810000 0x400>;
 382
 383                         sd_rst: reset {
 384                                 compatible = "socionext,uniphier-ld11-sd-reset";
 385                                 #reset-cells = <1>;
 386                         };
 387                 };
 388
 389                 perictrl@59820000 {
 390                         compatible = "socionext,uniphier-ld11-perictrl",
 391                                      "simple-mfd", "syscon";
 392                         reg = <0x59820000 0x200>;
 393
 394                         peri_clk: clock {
 395                                 compatible = "socionext,uniphier-ld11-peri-clock";
 396                                 #clock-cells = <1>;
 397                         };
 398
 399                         peri_rst: reset {
 400                                 compatible = "socionext,uniphier-ld11-peri-reset";
 401                                 #reset-cells = <1>;
 402                         };
 403                 };
 404
 405                 emmc: sdhc@5a000000 {
 406                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 407                         reg = <0x5a000000 0x400>;
 408                         interrupts = <0 78 4>;
 409                         pinctrl-names = "default";
 410                         pinctrl-0 = <&pinctrl_emmc>;
 411                         clocks = <&sys_clk 4>;
 412                         resets = <&sys_rst 4>;
 413                         bus-width = <8>;
 414                         mmc-ddr-1_8v;
 415                         mmc-hs200-1_8v;
 416                         mmc-pwrseq = <&emmc_pwrseq>;
 417                         cdns,phy-input-delay-legacy = <9>;
 418                         cdns,phy-input-delay-mmc-highspeed = <2>;
 419                         cdns,phy-input-delay-mmc-ddr = <3>;
 420                         cdns,phy-dll-delay-sdclk = <21>;
 421                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 422                 };
 423
 424                 usb0: usb@5a800100 {
 425                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 426                         status = "disabled";
 427                         reg = <0x5a800100 0x100>;
 428                         interrupts = <0 243 4>;
 429                         pinctrl-names = "default";
 430                         pinctrl-0 = <&pinctrl_usb0>;
 431                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 432                                  <&mio_clk 12>;
 433                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 434                                  <&mio_rst 12>;
 435                         has-transaction-translator;
 436                 };
 437
 438                 usb1: usb@5a810100 {
 439                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 440                         status = "disabled";
 441                         reg = <0x5a810100 0x100>;
 442                         interrupts = <0 244 4>;
 443                         pinctrl-names = "default";
 444                         pinctrl-0 = <&pinctrl_usb1>;
 445                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 446                                  <&mio_clk 13>;
 447                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 448                                  <&mio_rst 13>;
 449                         has-transaction-translator;
 450                 };
 451
 452                 usb2: usb@5a820100 {
 453                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 454                         status = "disabled";
 455                         reg = <0x5a820100 0x100>;
 456                         interrupts = <0 245 4>;
 457                         pinctrl-names = "default";
 458                         pinctrl-0 = <&pinctrl_usb2>;
 459                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 460                                  <&mio_clk 14>;
 461                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 462                                  <&mio_rst 14>;
 463                         has-transaction-translator;
 464                 };
 465
 466                 mioctrl@5b3e0000 {
 467                         compatible = "socionext,uniphier-ld11-mioctrl",
 468                                      "simple-mfd", "syscon";
 469                         reg = <0x5b3e0000 0x800>;
 470
 471                         mio_clk: clock {
 472                                 compatible = "socionext,uniphier-ld11-mio-clock";
 473                                 #clock-cells = <1>;
 474                         };
 475
 476                         mio_rst: reset {
 477                                 compatible = "socionext,uniphier-ld11-mio-reset";
 478                                 #reset-cells = <1>;
 479                                 resets = <&sys_rst 7>;
 480                         };
 481                 };
 482
 483                 soc_glue: soc-glue@5f800000 {
 484                         compatible = "socionext,uniphier-ld11-soc-glue",
 485                                      "simple-mfd", "syscon";
 486                         reg = <0x5f800000 0x2000>;
 487
 488                         pinctrl: pinctrl {
 489                                 compatible = "socionext,uniphier-ld11-pinctrl";
 490                         };
 491                 };
 492
 493                 soc-glue@5f900000 {
 494                         compatible = "socionext,uniphier-ld11-soc-glue-debug",
 495                                      "simple-mfd";
 496                         #address-cells = <1>;
 497                         #size-cells = <1>;
 498                         ranges = <0 0x5f900000 0x2000>;
 499
 500                         efuse@100 {
 501                                 compatible = "socionext,uniphier-efuse";
 502                                 reg = <0x100 0x28>;
 503                         };
 504
 505                         efuse@200 {
 506                                 compatible = "socionext,uniphier-efuse";
 507                                 reg = <0x200 0x68>;
 508                         };
 509                 };
 510
 511                 aidet: aidet@5fc20000 {
 512                         compatible = "socionext,uniphier-ld11-aidet";
 513                         reg = <0x5fc20000 0x200>;
 514                         interrupt-controller;
 515                         #interrupt-cells = <2>;
 516                 };
 517
 518                 gic: interrupt-controller@5fe00000 {
 519                         compatible = "arm,gic-v3";
 520                         reg = <0x5fe00000 0x10000>,     /* GICD */
 521                               <0x5fe40000 0x80000>;     /* GICR */
 522                         interrupt-controller;
 523                         #interrupt-cells = <3>;
 524                         interrupts = <1 9 4>;
 525                 };
 526
 527                 sysctrl@61840000 {
 528                         compatible = "socionext,uniphier-ld11-sysctrl",
 529                                      "simple-mfd", "syscon";
 530                         reg = <0x61840000 0x10000>;
 531
 532                         sys_clk: clock {
 533                                 compatible = "socionext,uniphier-ld11-clock";
 534                                 #clock-cells = <1>;
 535                         };
 536
 537                         sys_rst: reset {
 538                                 compatible = "socionext,uniphier-ld11-reset";
 539                                 #reset-cells = <1>;
 540                         };
 541
 542                         watchdog {
 543                                 compatible = "socionext,uniphier-wdt";
 544                         };
 545                 };
 546
 547                 eth: ethernet@65000000 {
 548                         compatible = "socionext,uniphier-ld11-ave4";
 549                         status = "disabled";
 550                         reg = <0x65000000 0x8500>;
 551                         interrupts = <0 66 4>;
 552                         clock-names = "ether";
 553                         clocks = <&sys_clk 6>;
 554                         reset-names = "ether";
 555                         resets = <&sys_rst 6>;
 556                         phy-mode = "internal";
 557                         local-mac-address = [00 00 00 00 00 00];
 558                         socionext,syscon-phy-mode = <&soc_glue 0>;
 559
 560                         mdio: mdio {
 561                                 #address-cells = <1>;
 562                                 #size-cells = <0>;
 563                         };
 564                 };
 565
 566                 nand: nand@68000000 {
 567                         compatible = "socionext,uniphier-denali-nand-v5b";
 568                         status = "disabled";
 569                         reg-names = "nand_data", "denali_reg";
 570                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 571                         interrupts = <0 65 4>;
 572                         pinctrl-names = "default";
 573                         pinctrl-0 = <&pinctrl_nand>;
 574                         clocks = <&sys_clk 2>;
 575                         resets = <&sys_rst 2>;
 576                 };
 577         };
 578 };
 579
 580 #include "uniphier-pinctrl.dtsi"
 581
 582 &pinctrl_aoutiec1 {
 583         drive-strength = <4>;   /* default: 4mA */
 584
 585         ao1arc {
 586                 pins = "AO1ARC";
 587                 drive-strength = <8>;   /* 8mA */
 588         };
 589 };