arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi

   1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
   2 //
   3 // Device Tree Source for UniPhier LD11 SoC
   4 //
   5 // Copyright (C) 2016 Socionext Inc.
   6 //   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
   7
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/gpio/uniphier-gpio.h>
  10
  11 /memreserve/ 0x80000000 0x02000000;
  12
  13 / {
  14         compatible = "socionext,uniphier-ld11";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17         interrupt-parent = <&gic>;
  18
  19         cpus {
  20                 #address-cells = <2>;
  21                 #size-cells = <0>;
  22
  23                 cpu-map {
  24                         cluster0 {
  25                                 core0 {
  26                                         cpu = <&cpu0>;
  27                                 };
  28                                 core1 {
  29                                         cpu = <&cpu1>;
  30                                 };
  31                         };
  32                 };
  33
  34                 cpu0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         reg = <0 0x000>;
  38                         clocks = <&sys_clk 33>;
  39                         enable-method = "psci";
  40                         operating-points-v2 = <&cluster0_opp>;
  41                 };
  42
  43                 cpu1: cpu@1 {
  44                         device_type = "cpu";
  45                         compatible = "arm,cortex-a53", "arm,armv8";
  46                         reg = <0 0x001>;
  47                         clocks = <&sys_clk 33>;
  48                         enable-method = "psci";
  49                         operating-points-v2 = <&cluster0_opp>;
  50                 };
  51         };
  52
  53         cluster0_opp: opp-table {
  54                 compatible = "operating-points-v2";
  55                 opp-shared;
  56
  57                 opp-245000000 {
  58                         opp-hz = /bits/ 64 <245000000>;
  59                         clock-latency-ns = <300>;
  60                 };
  61                 opp-250000000 {
  62                         opp-hz = /bits/ 64 <250000000>;
  63                         clock-latency-ns = <300>;
  64                 };
  65                 opp-490000000 {
  66                         opp-hz = /bits/ 64 <490000000>;
  67                         clock-latency-ns = <300>;
  68                 };
  69                 opp-500000000 {
  70                         opp-hz = /bits/ 64 <500000000>;
  71                         clock-latency-ns = <300>;
  72                 };
  73                 opp-653334000 {
  74                         opp-hz = /bits/ 64 <653334000>;
  75                         clock-latency-ns = <300>;
  76                 };
  77                 opp-666667000 {
  78                         opp-hz = /bits/ 64 <666667000>;
  79                         clock-latency-ns = <300>;
  80                 };
  81                 opp-980000000 {
  82                         opp-hz = /bits/ 64 <980000000>;
  83                         clock-latency-ns = <300>;
  84                 };
  85         };
  86
  87         psci {
  88                 compatible = "arm,psci-1.0";
  89                 method = "smc";
  90         };
  91
  92         clocks {
  93                 refclk: ref {
  94                         compatible = "fixed-clock";
  95                         #clock-cells = <0>;
  96                         clock-frequency = <25000000>;
  97                 };
  98         };
  99
 100         emmc_pwrseq: emmc-pwrseq {
 101                 compatible = "mmc-pwrseq-emmc";
 102                 reset-gpios = <&gpio UNIPHIER_GPIO_PORT(3, 2) GPIO_ACTIVE_LOW>;
 103         };
 104
 105         timer {
 106                 compatible = "arm,armv8-timer";
 107                 interrupts = <1 13 4>,
 108                              <1 14 4>,
 109                              <1 11 4>,
 110                              <1 10 4>;
 111         };
 112
 113         soc@0 {
 114                 compatible = "simple-bus";
 115                 #address-cells = <1>;
 116                 #size-cells = <1>;
 117                 ranges = <0 0 0 0xffffffff>;
 118
 119                 spi0: spi@54006000 {
 120                         compatible = "socionext,uniphier-scssi";
 121                         status = "disabled";
 122                         reg = <0x54006000 0x100>;
 123                         interrupts = <0 39 4>;
 124                         pinctrl-names = "default";
 125                         pinctrl-0 = <&pinctrl_spi0>;
 126                         clocks = <&peri_clk 11>;
 127                         resets = <&peri_rst 11>;
 128                 };
 129
 130                 spi1: spi@54006100 {
 131                         compatible = "socionext,uniphier-scssi";
 132                         status = "disabled";
 133                         reg = <0x54006100 0x100>;
 134                         interrupts = <0 216 4>;
 135                         pinctrl-names = "default";
 136                         pinctrl-0 = <&pinctrl_spi1>;
 137                         clocks = <&peri_clk 11>;
 138                         resets = <&peri_rst 11>;
 139                 };
 140
 141                 serial0: serial@54006800 {
 142                         compatible = "socionext,uniphier-uart";
 143                         status = "disabled";
 144                         reg = <0x54006800 0x40>;
 145                         interrupts = <0 33 4>;
 146                         pinctrl-names = "default";
 147                         pinctrl-0 = <&pinctrl_uart0>;
 148                         clocks = <&peri_clk 0>;
 149                         resets = <&peri_rst 0>;
 150                 };
 151
 152                 serial1: serial@54006900 {
 153                         compatible = "socionext,uniphier-uart";
 154                         status = "disabled";
 155                         reg = <0x54006900 0x40>;
 156                         interrupts = <0 35 4>;
 157                         pinctrl-names = "default";
 158                         pinctrl-0 = <&pinctrl_uart1>;
 159                         clocks = <&peri_clk 1>;
 160                         resets = <&peri_rst 1>;
 161                 };
 162
 163                 serial2: serial@54006a00 {
 164                         compatible = "socionext,uniphier-uart";
 165                         status = "disabled";
 166                         reg = <0x54006a00 0x40>;
 167                         interrupts = <0 37 4>;
 168                         pinctrl-names = "default";
 169                         pinctrl-0 = <&pinctrl_uart2>;
 170                         clocks = <&peri_clk 2>;
 171                         resets = <&peri_rst 2>;
 172                 };
 173
 174                 serial3: serial@54006b00 {
 175                         compatible = "socionext,uniphier-uart";
 176                         status = "disabled";
 177                         reg = <0x54006b00 0x40>;
 178                         interrupts = <0 177 4>;
 179                         pinctrl-names = "default";
 180                         pinctrl-0 = <&pinctrl_uart3>;
 181                         clocks = <&peri_clk 3>;
 182                         resets = <&peri_rst 3>;
 183                 };
 184
 185                 gpio: gpio@55000000 {
 186                         compatible = "socionext,uniphier-gpio";
 187                         reg = <0x55000000 0x200>;
 188                         interrupt-parent = <&aidet>;
 189                         interrupt-controller;
 190                         #interrupt-cells = <2>;
 191                         gpio-controller;
 192                         #gpio-cells = <2>;
 193                         gpio-ranges = <&pinctrl 0 0 0>,
 194                                       <&pinctrl 43 0 0>,
 195                                       <&pinctrl 51 0 0>,
 196                                       <&pinctrl 96 0 0>,
 197                                       <&pinctrl 160 0 0>,
 198                                       <&pinctrl 184 0 0>;
 199                         gpio-ranges-group-names = "gpio_range0",
 200                                                   "gpio_range1",
 201                                                   "gpio_range2",
 202                                                   "gpio_range3",
 203                                                   "gpio_range4",
 204                                                   "gpio_range5";
 205                         ngpios = <200>;
 206                         socionext,interrupt-ranges = <0 48 16>, <16 154 5>,
 207                                                      <21 217 3>;
 208                 };
 209
 210                 audio@56000000 {
 211                         compatible = "socionext,uniphier-ld11-aio";
 212                         reg = <0x56000000 0x80000>;
 213                         interrupts = <0 144 4>;
 214                         pinctrl-names = "default";
 215                         pinctrl-0 = <&pinctrl_aout1>,
 216                                     <&pinctrl_aoutiec1>;
 217                         clock-names = "aio";
 218                         clocks = <&sys_clk 40>;
 219                         reset-names = "aio";
 220                         resets = <&sys_rst 40>;
 221                         #sound-dai-cells = <1>;
 222                         socionext,syscon = <&soc_glue>;
 223
 224                         i2s_port0: port@0 {
 225                                 i2s_hdmi: endpoint {
 226                                 };
 227                         };
 228
 229                         i2s_port1: port@1 {
 230                                 i2s_pcmin2: endpoint {
 231                                 };
 232                         };
 233
 234                         i2s_port2: port@2 {
 235                                 i2s_line: endpoint {
 236                                         dai-format = "i2s";
 237                                         remote-endpoint = <&evea_line>;
 238                                 };
 239                         };
 240
 241                         i2s_port3: port@3 {
 242                                 i2s_hpcmout1: endpoint {
 243                                 };
 244                         };
 245
 246                         i2s_port4: port@4 {
 247                                 i2s_hp: endpoint {
 248                                         dai-format = "i2s";
 249                                         remote-endpoint = <&evea_hp>;
 250                                 };
 251                         };
 252
 253                         spdif_port0: port@5 {
 254                                 spdif_hiecout1: endpoint {
 255                                 };
 256                         };
 257
 258                         src_port0: port@6 {
 259                                 i2s_epcmout2: endpoint {
 260                                 };
 261                         };
 262
 263                         src_port1: port@7 {
 264                                 i2s_epcmout3: endpoint {
 265                                 };
 266                         };
 267
 268                         comp_spdif_port0: port@8 {
 269                                 comp_spdif_hiecout1: endpoint {
 270                                 };
 271                         };
 272                 };
 273
 274                 codec@57900000 {
 275                         compatible = "socionext,uniphier-evea";
 276                         reg = <0x57900000 0x1000>;
 277                         clock-names = "evea", "exiv";
 278                         clocks = <&sys_clk 41>, <&sys_clk 42>;
 279                         reset-names = "evea", "exiv", "adamv";
 280                         resets = <&sys_rst 41>, <&sys_rst 42>, <&adamv_rst 0>;
 281                         #sound-dai-cells = <1>;
 282
 283                         port@0 {
 284                                 evea_line: endpoint {
 285                                         remote-endpoint = <&i2s_line>;
 286                                 };
 287                         };
 288
 289                         port@1 {
 290                                 evea_hp: endpoint {
 291                                         remote-endpoint = <&i2s_hp>;
 292                                 };
 293                         };
 294                 };
 295
 296                 adamv@57920000 {
 297                         compatible = "socionext,uniphier-ld11-adamv",
 298                                      "simple-mfd", "syscon";
 299                         reg = <0x57920000 0x1000>;
 300
 301                         adamv_rst: reset {
 302                                 compatible = "socionext,uniphier-ld11-adamv-reset";
 303                                 #reset-cells = <1>;
 304                         };
 305                 };
 306
 307                 i2c0: i2c@58780000 {
 308                         compatible = "socionext,uniphier-fi2c";
 309                         status = "disabled";
 310                         reg = <0x58780000 0x80>;
 311                         #address-cells = <1>;
 312                         #size-cells = <0>;
 313                         interrupts = <0 41 4>;
 314                         pinctrl-names = "default";
 315                         pinctrl-0 = <&pinctrl_i2c0>;
 316                         clocks = <&peri_clk 4>;
 317                         resets = <&peri_rst 4>;
 318                         clock-frequency = <100000>;
 319                 };
 320
 321                 i2c1: i2c@58781000 {
 322                         compatible = "socionext,uniphier-fi2c";
 323                         status = "disabled";
 324                         reg = <0x58781000 0x80>;
 325                         #address-cells = <1>;
 326                         #size-cells = <0>;
 327                         interrupts = <0 42 4>;
 328                         pinctrl-names = "default";
 329                         pinctrl-0 = <&pinctrl_i2c1>;
 330                         clocks = <&peri_clk 5>;
 331                         resets = <&peri_rst 5>;
 332                         clock-frequency = <100000>;
 333                 };
 334
 335                 i2c2: i2c@58782000 {
 336                         compatible = "socionext,uniphier-fi2c";
 337                         reg = <0x58782000 0x80>;
 338                         #address-cells = <1>;
 339                         #size-cells = <0>;
 340                         interrupts = <0 43 4>;
 341                         clocks = <&peri_clk 6>;
 342                         resets = <&peri_rst 6>;
 343                         clock-frequency = <400000>;
 344                 };
 345
 346                 i2c3: i2c@58783000 {
 347                         compatible = "socionext,uniphier-fi2c";
 348                         status = "disabled";
 349                         reg = <0x58783000 0x80>;
 350                         #address-cells = <1>;
 351                         #size-cells = <0>;
 352                         interrupts = <0 44 4>;
 353                         pinctrl-names = "default";
 354                         pinctrl-0 = <&pinctrl_i2c3>;
 355                         clocks = <&peri_clk 7>;
 356                         resets = <&peri_rst 7>;
 357                         clock-frequency = <100000>;
 358                 };
 359
 360                 i2c4: i2c@58784000 {
 361                         compatible = "socionext,uniphier-fi2c";
 362                         status = "disabled";
 363                         reg = <0x58784000 0x80>;
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         interrupts = <0 45 4>;
 367                         pinctrl-names = "default";
 368                         pinctrl-0 = <&pinctrl_i2c4>;
 369                         clocks = <&peri_clk 8>;
 370                         resets = <&peri_rst 8>;
 371                         clock-frequency = <100000>;
 372                 };
 373
 374                 i2c5: i2c@58785000 {
 375                         compatible = "socionext,uniphier-fi2c";
 376                         reg = <0x58785000 0x80>;
 377                         #address-cells = <1>;
 378                         #size-cells = <0>;
 379                         interrupts = <0 25 4>;
 380                         clocks = <&peri_clk 9>;
 381                         resets = <&peri_rst 9>;
 382                         clock-frequency = <400000>;
 383                 };
 384
 385                 system_bus: system-bus@58c00000 {
 386                         compatible = "socionext,uniphier-system-bus";
 387                         status = "disabled";
 388                         reg = <0x58c00000 0x400>;
 389                         #address-cells = <2>;
 390                         #size-cells = <1>;
 391                         pinctrl-names = "default";
 392                         pinctrl-0 = <&pinctrl_system_bus>;
 393                 };
 394
 395                 smpctrl@59801000 {
 396                         compatible = "socionext,uniphier-smpctrl";
 397                         reg = <0x59801000 0x400>;
 398                 };
 399
 400                 sdctrl@59810000 {
 401                         compatible = "socionext,uniphier-ld11-sdctrl",
 402                                      "simple-mfd", "syscon";
 403                         reg = <0x59810000 0x400>;
 404
 405                         sd_rst: reset {
 406                                 compatible = "socionext,uniphier-ld11-sd-reset";
 407                                 #reset-cells = <1>;
 408                         };
 409                 };
 410
 411                 perictrl@59820000 {
 412                         compatible = "socionext,uniphier-ld11-perictrl",
 413                                      "simple-mfd", "syscon";
 414                         reg = <0x59820000 0x200>;
 415
 416                         peri_clk: clock {
 417                                 compatible = "socionext,uniphier-ld11-peri-clock";
 418                                 #clock-cells = <1>;
 419                         };
 420
 421                         peri_rst: reset {
 422                                 compatible = "socionext,uniphier-ld11-peri-reset";
 423                                 #reset-cells = <1>;
 424                         };
 425                 };
 426
 427                 emmc: sdhc@5a000000 {
 428                         compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
 429                         reg = <0x5a000000 0x400>;
 430                         interrupts = <0 78 4>;
 431                         pinctrl-names = "default";
 432                         pinctrl-0 = <&pinctrl_emmc>;
 433                         clocks = <&sys_clk 4>;
 434                         resets = <&sys_rst 4>;
 435                         bus-width = <8>;
 436                         mmc-ddr-1_8v;
 437                         mmc-hs200-1_8v;
 438                         mmc-pwrseq = <&emmc_pwrseq>;
 439                         cdns,phy-input-delay-legacy = <9>;
 440                         cdns,phy-input-delay-mmc-highspeed = <2>;
 441                         cdns,phy-input-delay-mmc-ddr = <3>;
 442                         cdns,phy-dll-delay-sdclk = <21>;
 443                         cdns,phy-dll-delay-sdclk-hsmmc = <21>;
 444                 };
 445
 446                 usb0: usb@5a800100 {
 447                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 448                         status = "disabled";
 449                         reg = <0x5a800100 0x100>;
 450                         interrupts = <0 243 4>;
 451                         pinctrl-names = "default";
 452                         pinctrl-0 = <&pinctrl_usb0>;
 453                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
 454                                  <&mio_clk 12>;
 455                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
 456                                  <&mio_rst 12>;
 457                         phy-names = "usb";
 458                         phys = <&usb_phy0>;
 459                         has-transaction-translator;
 460                 };
 461
 462                 usb1: usb@5a810100 {
 463                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 464                         status = "disabled";
 465                         reg = <0x5a810100 0x100>;
 466                         interrupts = <0 244 4>;
 467                         pinctrl-names = "default";
 468                         pinctrl-0 = <&pinctrl_usb1>;
 469                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
 470                                  <&mio_clk 13>;
 471                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
 472                                  <&mio_rst 13>;
 473                         phy-names = "usb";
 474                         phys = <&usb_phy1>;
 475                         has-transaction-translator;
 476                 };
 477
 478                 usb2: usb@5a820100 {
 479                         compatible = "socionext,uniphier-ehci", "generic-ehci";
 480                         status = "disabled";
 481                         reg = <0x5a820100 0x100>;
 482                         interrupts = <0 245 4>;
 483                         pinctrl-names = "default";
 484                         pinctrl-0 = <&pinctrl_usb2>;
 485                         clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
 486                                  <&mio_clk 14>;
 487                         resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
 488                                  <&mio_rst 14>;
 489                         phy-names = "usb";
 490                         phys = <&usb_phy2>;
 491                         has-transaction-translator;
 492                 };
 493
 494                 mioctrl@5b3e0000 {
 495                         compatible = "socionext,uniphier-ld11-mioctrl",
 496                                      "simple-mfd", "syscon";
 497                         reg = <0x5b3e0000 0x800>;
 498
 499                         mio_clk: clock {
 500                                 compatible = "socionext,uniphier-ld11-mio-clock";
 501                                 #clock-cells = <1>;
 502                         };
 503
 504                         mio_rst: reset {
 505                                 compatible = "socionext,uniphier-ld11-mio-reset";
 506                                 #reset-cells = <1>;
 507                                 resets = <&sys_rst 7>;
 508                         };
 509                 };
 510
 511                 soc_glue: soc-glue@5f800000 {
 512                         compatible = "socionext,uniphier-ld11-soc-glue",
 513                                      "simple-mfd", "syscon";
 514                         reg = <0x5f800000 0x2000>;
 515
 516                         pinctrl: pinctrl {
 517                                 compatible = "socionext,uniphier-ld11-pinctrl";
 518                         };
 519
 520                         usb-phy {
 521                                 compatible = "socionext,uniphier-ld11-usb2-phy";
 522                                 #address-cells = <1>;
 523                                 #size-cells = <0>;
 524
 525                                 usb_phy0: phy@0 {
 526                                         reg = <0>;
 527                                         #phy-cells = <0>;
 528                                 };
 529
 530                                 usb_phy1: phy@1 {
 531                                         reg = <1>;
 532                                         #phy-cells = <0>;
 533                                 };
 534
 535                                 usb_phy2: phy@2 {
 536                                         reg = <2>;
 537                                         #phy-cells = <0>;
 538                                 };
 539                         };
 540                 };
 541
 542                 soc-glue@5f900000 {
 543                         compatible = "socionext,uniphier-ld11-soc-glue-debug",
 544                                      "simple-mfd";
 545                         #address-cells = <1>;
 546                         #size-cells = <1>;
 547                         ranges = <0 0x5f900000 0x2000>;
 548
 549                         efuse@100 {
 550                                 compatible = "socionext,uniphier-efuse";
 551                                 reg = <0x100 0x28>;
 552                         };
 553
 554                         efuse@200 {
 555                                 compatible = "socionext,uniphier-efuse";
 556                                 reg = <0x200 0x68>;
 557                         };
 558                 };
 559
 560                 aidet: aidet@5fc20000 {
 561                         compatible = "socionext,uniphier-ld11-aidet";
 562                         reg = <0x5fc20000 0x200>;
 563                         interrupt-controller;
 564                         #interrupt-cells = <2>;
 565                 };
 566
 567                 gic: interrupt-controller@5fe00000 {
 568                         compatible = "arm,gic-v3";
 569                         reg = <0x5fe00000 0x10000>,     /* GICD */
 570                               <0x5fe40000 0x80000>;     /* GICR */
 571                         interrupt-controller;
 572                         #interrupt-cells = <3>;
 573                         interrupts = <1 9 4>;
 574                 };
 575
 576                 sysctrl@61840000 {
 577                         compatible = "socionext,uniphier-ld11-sysctrl",
 578                                      "simple-mfd", "syscon";
 579                         reg = <0x61840000 0x10000>;
 580
 581                         sys_clk: clock {
 582                                 compatible = "socionext,uniphier-ld11-clock";
 583                                 #clock-cells = <1>;
 584                         };
 585
 586                         sys_rst: reset {
 587                                 compatible = "socionext,uniphier-ld11-reset";
 588                                 #reset-cells = <1>;
 589                         };
 590
 591                         watchdog {
 592                                 compatible = "socionext,uniphier-wdt";
 593                         };
 594                 };
 595
 596                 eth: ethernet@65000000 {
 597                         compatible = "socionext,uniphier-ld11-ave4";
 598                         status = "disabled";
 599                         reg = <0x65000000 0x8500>;
 600                         interrupts = <0 66 4>;
 601                         clock-names = "ether";
 602                         clocks = <&sys_clk 6>;
 603                         reset-names = "ether";
 604                         resets = <&sys_rst 6>;
 605                         phy-mode = "internal";
 606                         local-mac-address = [00 00 00 00 00 00];
 607                         socionext,syscon-phy-mode = <&soc_glue 0>;
 608
 609                         mdio: mdio {
 610                                 #address-cells = <1>;
 611                                 #size-cells = <0>;
 612                         };
 613                 };
 614
 615                 nand: nand@68000000 {
 616                         compatible = "socionext,uniphier-denali-nand-v5b";
 617                         status = "disabled";
 618                         reg-names = "nand_data", "denali_reg";
 619                         reg = <0x68000000 0x20>, <0x68100000 0x1000>;
 620                         interrupts = <0 65 4>;
 621                         pinctrl-names = "default";
 622                         pinctrl-0 = <&pinctrl_nand>;
 623                         clock-names = "nand", "nand_x", "ecc";
 624                         clocks = <&sys_clk 2>, <&sys_clk 3>, <&sys_clk 3>;
 625                         resets = <&sys_rst 2>;
 626                 };
 627         };
 628 };
 629
 630 #include "uniphier-pinctrl.dtsi"
 631
 632 &pinctrl_aoutiec1 {
 633         drive-strength = <4>;   /* default: 4mA */
 634
 635         ao1arc {
 636                 pins = "AO1ARC";
 637                 drive-strength = <8>;   /* 8mA */
 638         };
 639 };