arch/arm64/boot/dts/rockchip/rk3368.dtsi

   1 /*
   2  * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This library is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This library is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  */
  42
  43 #include <dt-bindings/clock/rk3368-cru.h>
  44 #include <dt-bindings/gpio/gpio.h>
  45 #include <dt-bindings/interrupt-controller/irq.h>
  46 #include <dt-bindings/interrupt-controller/arm-gic.h>
  47 #include <dt-bindings/pinctrl/rockchip.h>
  48 #include <dt-bindings/soc/rockchip,boot-mode.h>
  49 #include <dt-bindings/thermal/thermal.h>
  50
  51 / {
  52         compatible = "rockchip,rk3368";
  53         interrupt-parent = <&gic>;
  54         #address-cells = <2>;
  55         #size-cells = <2>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59                 i2c0 = &i2c0;
  60                 i2c1 = &i2c1;
  61                 i2c2 = &i2c2;
  62                 i2c3 = &i2c3;
  63                 i2c4 = &i2c4;
  64                 i2c5 = &i2c5;
  65                 serial0 = &uart0;
  66                 serial1 = &uart1;
  67                 serial2 = &uart2;
  68                 serial3 = &uart3;
  69                 serial4 = &uart4;
  70                 spi0 = &spi0;
  71                 spi1 = &spi1;
  72                 spi2 = &spi2;
  73         };
  74
  75         cpus {
  76                 #address-cells = <0x2>;
  77                 #size-cells = <0x0>;
  78
  79                 cpu-map {
  80                         cluster0 {
  81                                 core0 {
  82                                         cpu = <&cpu_b0>;
  83                                 };
  84                                 core1 {
  85                                         cpu = <&cpu_b1>;
  86                                 };
  87                                 core2 {
  88                                         cpu = <&cpu_b2>;
  89                                 };
  90                                 core3 {
  91                                         cpu = <&cpu_b3>;
  92                                 };
  93                         };
  94
  95                         cluster1 {
  96                                 core0 {
  97                                         cpu = <&cpu_l0>;
  98                                 };
  99                                 core1 {
 100                                         cpu = <&cpu_l1>;
 101                                 };
 102                                 core2 {
 103                                         cpu = <&cpu_l2>;
 104                                 };
 105                                 core3 {
 106                                         cpu = <&cpu_l3>;
 107                                 };
 108                         };
 109                 };
 110
 111                 cpu_l0: cpu@0 {
 112                         device_type = "cpu";
 113                         compatible = "arm,cortex-a53", "arm,armv8";
 114                         reg = <0x0 0x0>;
 115                         enable-method = "psci";
 116
 117                         #cooling-cells = <2>; /* min followed by max */
 118                 };
 119
 120                 cpu_l1: cpu@1 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a53", "arm,armv8";
 123                         reg = <0x0 0x1>;
 124                         enable-method = "psci";
 125                 };
 126
 127                 cpu_l2: cpu@2 {
 128                         device_type = "cpu";
 129                         compatible = "arm,cortex-a53", "arm,armv8";
 130                         reg = <0x0 0x2>;
 131                         enable-method = "psci";
 132                 };
 133
 134                 cpu_l3: cpu@3 {
 135                         device_type = "cpu";
 136                         compatible = "arm,cortex-a53", "arm,armv8";
 137                         reg = <0x0 0x3>;
 138                         enable-method = "psci";
 139                 };
 140
 141                 cpu_b0: cpu@100 {
 142                         device_type = "cpu";
 143                         compatible = "arm,cortex-a53", "arm,armv8";
 144                         reg = <0x0 0x100>;
 145                         enable-method = "psci";
 146
 147                         #cooling-cells = <2>; /* min followed by max */
 148                 };
 149
 150                 cpu_b1: cpu@101 {
 151                         device_type = "cpu";
 152                         compatible = "arm,cortex-a53", "arm,armv8";
 153                         reg = <0x0 0x101>;
 154                         enable-method = "psci";
 155                 };
 156
 157                 cpu_b2: cpu@102 {
 158                         device_type = "cpu";
 159                         compatible = "arm,cortex-a53", "arm,armv8";
 160                         reg = <0x0 0x102>;
 161                         enable-method = "psci";
 162                 };
 163
 164                 cpu_b3: cpu@103 {
 165                         device_type = "cpu";
 166                         compatible = "arm,cortex-a53", "arm,armv8";
 167                         reg = <0x0 0x103>;
 168                         enable-method = "psci";
 169                 };
 170         };
 171
 172         amba {
 173                 compatible = "simple-bus";
 174                 #address-cells = <2>;
 175                 #size-cells = <2>;
 176                 ranges;
 177
 178                 dmac_peri: dma-controller@ff250000 {
 179                         compatible = "arm,pl330", "arm,primecell";
 180                         reg = <0x0 0xff250000 0x0 0x4000>;
 181                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 182                                      <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 183                         #dma-cells = <1>;
 184                         arm,pl330-broken-no-flushp;
 185                         clocks = <&cru ACLK_DMAC_PERI>;
 186                         clock-names = "apb_pclk";
 187                 };
 188
 189                 dmac_bus: dma-controller@ff600000 {
 190                         compatible = "arm,pl330", "arm,primecell";
 191                         reg = <0x0 0xff600000 0x0 0x4000>;
 192                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 193                                      <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 194                         #dma-cells = <1>;
 195                         arm,pl330-broken-no-flushp;
 196                         clocks = <&cru ACLK_DMAC_BUS>;
 197                         clock-names = "apb_pclk";
 198                 };
 199         };
 200
 201         arm-pmu {
 202                 compatible = "arm,armv8-pmuv3";
 203                 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
 204                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
 205                              <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
 206                              <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
 207                              <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 208                              <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 209                              <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 210                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 211                 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>,
 212                                      <&cpu_l3>, <&cpu_b0>, <&cpu_b1>,
 213                                      <&cpu_b2>, <&cpu_b3>;
 214         };
 215
 216         psci {
 217                 compatible = "arm,psci-0.2";
 218                 method = "smc";
 219         };
 220
 221         timer {
 222                 compatible = "arm,armv8-timer";
 223                 interrupts = <GIC_PPI 13
 224                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 225                              <GIC_PPI 14
 226                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 227                              <GIC_PPI 11
 228                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
 229                              <GIC_PPI 10
 230                         (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 231         };
 232
 233         xin24m: oscillator {
 234                 compatible = "fixed-clock";
 235                 clock-frequency = <24000000>;
 236                 clock-output-names = "xin24m";
 237                 #clock-cells = <0>;
 238         };
 239
 240         sdmmc: dwmmc@ff0c0000 {
 241                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 242                 reg = <0x0 0xff0c0000 0x0 0x4000>;
 243                 max-frequency = <150000000>;
 244                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 245                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 246                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 247                 fifo-depth = <0x100>;
 248                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 249                 resets = <&cru SRST_MMC0>;
 250                 reset-names = "reset";
 251                 status = "disabled";
 252         };
 253
 254         sdio0: dwmmc@ff0d0000 {
 255                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 256                 reg = <0x0 0xff0d0000 0x0 0x4000>;
 257                 max-frequency = <150000000>;
 258                 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
 259                          <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
 260                 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
 261                 fifo-depth = <0x100>;
 262                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 263                 resets = <&cru SRST_SDIO0>;
 264                 reset-names = "reset";
 265                 status = "disabled";
 266         };
 267
 268         emmc: dwmmc@ff0f0000 {
 269                 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc";
 270                 reg = <0x0 0xff0f0000 0x0 0x4000>;
 271                 max-frequency = <150000000>;
 272                 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
 273                          <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
 274                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 275                 fifo-depth = <0x100>;
 276                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 277                 resets = <&cru SRST_EMMC>;
 278                 reset-names = "reset";
 279                 status = "disabled";
 280         };
 281
 282         saradc: saradc@ff100000 {
 283                 compatible = "rockchip,saradc";
 284                 reg = <0x0 0xff100000 0x0 0x100>;
 285                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 286                 #io-channel-cells = <1>;
 287                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 288                 clock-names = "saradc", "apb_pclk";
 289                 resets = <&cru SRST_SARADC>;
 290                 reset-names = "saradc-apb";
 291                 status = "disabled";
 292         };
 293
 294         spi0: spi@ff110000 {
 295                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 296                 reg = <0x0 0xff110000 0x0 0x1000>;
 297                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 298                 clock-names = "spiclk", "apb_pclk";
 299                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 300                 pinctrl-names = "default";
 301                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 302                 #address-cells = <1>;
 303                 #size-cells = <0>;
 304                 status = "disabled";
 305         };
 306
 307         spi1: spi@ff120000 {
 308                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 309                 reg = <0x0 0xff120000 0x0 0x1000>;
 310                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 311                 clock-names = "spiclk", "apb_pclk";
 312                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 313                 pinctrl-names = "default";
 314                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 315                 #address-cells = <1>;
 316                 #size-cells = <0>;
 317                 status = "disabled";
 318         };
 319
 320         spi2: spi@ff130000 {
 321                 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi";
 322                 reg = <0x0 0xff130000 0x0 0x1000>;
 323                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 324                 clock-names = "spiclk", "apb_pclk";
 325                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 326                 pinctrl-names = "default";
 327                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 328                 #address-cells = <1>;
 329                 #size-cells = <0>;
 330                 status = "disabled";
 331         };
 332
 333         i2c2: i2c@ff140000 {
 334                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 335                 reg = <0x0 0xff140000 0x0 0x1000>;
 336                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 337                 #address-cells = <1>;
 338                 #size-cells = <0>;
 339                 clock-names = "i2c";
 340                 clocks = <&cru PCLK_I2C2>;
 341                 pinctrl-names = "default";
 342                 pinctrl-0 = <&i2c2_xfer>;
 343                 status = "disabled";
 344         };
 345
 346         i2c3: i2c@ff150000 {
 347                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 348                 reg = <0x0 0xff150000 0x0 0x1000>;
 349                 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 350                 #address-cells = <1>;
 351                 #size-cells = <0>;
 352                 clock-names = "i2c";
 353                 clocks = <&cru PCLK_I2C3>;
 354                 pinctrl-names = "default";
 355                 pinctrl-0 = <&i2c3_xfer>;
 356                 status = "disabled";
 357         };
 358
 359         i2c4: i2c@ff160000 {
 360                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 361                 reg = <0x0 0xff160000 0x0 0x1000>;
 362                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 363                 #address-cells = <1>;
 364                 #size-cells = <0>;
 365                 clock-names = "i2c";
 366                 clocks = <&cru PCLK_I2C4>;
 367                 pinctrl-names = "default";
 368                 pinctrl-0 = <&i2c4_xfer>;
 369                 status = "disabled";
 370         };
 371
 372         i2c5: i2c@ff170000 {
 373                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 374                 reg = <0x0 0xff170000 0x0 0x1000>;
 375                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 376                 #address-cells = <1>;
 377                 #size-cells = <0>;
 378                 clock-names = "i2c";
 379                 clocks = <&cru PCLK_I2C5>;
 380                 pinctrl-names = "default";
 381                 pinctrl-0 = <&i2c5_xfer>;
 382                 status = "disabled";
 383         };
 384
 385         uart0: serial@ff180000 {
 386                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 387                 reg = <0x0 0xff180000 0x0 0x100>;
 388                 clock-frequency = <24000000>;
 389                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 390                 clock-names = "baudclk", "apb_pclk";
 391                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 392                 reg-shift = <2>;
 393                 reg-io-width = <4>;
 394                 status = "disabled";
 395         };
 396
 397         uart1: serial@ff190000 {
 398                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 399                 reg = <0x0 0xff190000 0x0 0x100>;
 400                 clock-frequency = <24000000>;
 401                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 402                 clock-names = "baudclk", "apb_pclk";
 403                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 404                 reg-shift = <2>;
 405                 reg-io-width = <4>;
 406                 status = "disabled";
 407         };
 408
 409         uart3: serial@ff1b0000 {
 410                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 411                 reg = <0x0 0xff1b0000 0x0 0x100>;
 412                 clock-frequency = <24000000>;
 413                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 414                 clock-names = "baudclk", "apb_pclk";
 415                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 416                 reg-shift = <2>;
 417                 reg-io-width = <4>;
 418                 status = "disabled";
 419         };
 420
 421         uart4: serial@ff1c0000 {
 422                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 423                 reg = <0x0 0xff1c0000 0x0 0x100>;
 424                 clock-frequency = <24000000>;
 425                 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
 426                 clock-names = "baudclk", "apb_pclk";
 427                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
 428                 reg-shift = <2>;
 429                 reg-io-width = <4>;
 430                 status = "disabled";
 431         };
 432
 433         thermal-zones {
 434                 cpu {
 435                         polling-delay-passive = <100>; /* milliseconds */
 436                         polling-delay = <5000>; /* milliseconds */
 437
 438                         thermal-sensors = <&tsadc 0>;
 439
 440                         trips {
 441                                 cpu_alert0: cpu_alert0 {
 442                                         temperature = <75000>; /* millicelsius */
 443                                         hysteresis = <2000>; /* millicelsius */
 444                                         type = "passive";
 445                                 };
 446                                 cpu_alert1: cpu_alert1 {
 447                                         temperature = <80000>; /* millicelsius */
 448                                         hysteresis = <2000>; /* millicelsius */
 449                                         type = "passive";
 450                                 };
 451                                 cpu_crit: cpu_crit {
 452                                         temperature = <95000>; /* millicelsius */
 453                                         hysteresis = <2000>; /* millicelsius */
 454                                         type = "critical";
 455                                 };
 456                         };
 457
 458                         cooling-maps {
 459                                 map0 {
 460                                         trip = <&cpu_alert0>;
 461                                         cooling-device =
 462                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 463                                 };
 464                                 map1 {
 465                                         trip = <&cpu_alert1>;
 466                                         cooling-device =
 467                                         <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 468                                 };
 469                         };
 470                 };
 471
 472                 gpu {
 473                         polling-delay-passive = <100>; /* milliseconds */
 474                         polling-delay = <5000>; /* milliseconds */
 475
 476                         thermal-sensors = <&tsadc 1>;
 477
 478                         trips {
 479                                 gpu_alert0: gpu_alert0 {
 480                                         temperature = <80000>; /* millicelsius */
 481                                         hysteresis = <2000>; /* millicelsius */
 482                                         type = "passive";
 483                                 };
 484                                 gpu_crit: gpu_crit {
 485                                         temperature = <115000>; /* millicelsius */
 486                                         hysteresis = <2000>; /* millicelsius */
 487                                         type = "critical";
 488                                 };
 489                         };
 490
 491                         cooling-maps {
 492                                 map0 {
 493                                         trip = <&gpu_alert0>;
 494                                         cooling-device =
 495                                         <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 496                                 };
 497                         };
 498                 };
 499         };
 500
 501         tsadc: tsadc@ff280000 {
 502                 compatible = "rockchip,rk3368-tsadc";
 503                 reg = <0x0 0xff280000 0x0 0x100>;
 504                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 505                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 506                 clock-names = "tsadc", "apb_pclk";
 507                 resets = <&cru SRST_TSADC>;
 508                 reset-names = "tsadc-apb";
 509                 pinctrl-names = "init", "default", "sleep";
 510                 pinctrl-0 = <&otp_gpio>;
 511                 pinctrl-1 = <&otp_out>;
 512                 pinctrl-2 = <&otp_gpio>;
 513                 #thermal-sensor-cells = <1>;
 514                 rockchip,hw-tshut-temp = <95000>;
 515                 status = "disabled";
 516         };
 517
 518         gmac: ethernet@ff290000 {
 519                 compatible = "rockchip,rk3368-gmac";
 520                 reg = <0x0 0xff290000 0x0 0x10000>;
 521                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 522                 interrupt-names = "macirq";
 523                 rockchip,grf = <&grf>;
 524                 clocks = <&cru SCLK_MAC>,
 525                         <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
 526                         <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
 527                         <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
 528                 clock-names = "stmmaceth",
 529                         "mac_clk_rx", "mac_clk_tx",
 530                         "clk_mac_ref", "clk_mac_refout",
 531                         "aclk_mac", "pclk_mac";
 532                 status = "disabled";
 533         };
 534
 535         usb_host0_ehci: usb@ff500000 {
 536                 compatible = "generic-ehci";
 537                 reg = <0x0 0xff500000 0x0 0x100>;
 538                 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 539                 clocks = <&cru HCLK_HOST0>;
 540                 clock-names = "usbhost";
 541                 status = "disabled";
 542         };
 543
 544         usb_otg: usb@ff580000 {
 545                 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb",
 546                                 "snps,dwc2";
 547                 reg = <0x0 0xff580000 0x0 0x40000>;
 548                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 549                 clocks = <&cru HCLK_OTG0>;
 550                 clock-names = "otg";
 551                 dr_mode = "otg";
 552                 g-np-tx-fifo-size = <16>;
 553                 g-rx-fifo-size = <275>;
 554                 g-tx-fifo-size = <256 128 128 64 64 32>;
 555                 status = "disabled";
 556         };
 557
 558         i2c0: i2c@ff650000 {
 559                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 560                 reg = <0x0 0xff650000 0x0 0x1000>;
 561                 clocks = <&cru PCLK_I2C0>;
 562                 clock-names = "i2c";
 563                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 564                 pinctrl-names = "default";
 565                 pinctrl-0 = <&i2c0_xfer>;
 566                 #address-cells = <1>;
 567                 #size-cells = <0>;
 568                 status = "disabled";
 569         };
 570
 571         i2c1: i2c@ff660000 {
 572                 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c";
 573                 reg = <0x0 0xff660000 0x0 0x1000>;
 574                 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 575                 #address-cells = <1>;
 576                 #size-cells = <0>;
 577                 clock-names = "i2c";
 578                 clocks = <&cru PCLK_I2C1>;
 579                 pinctrl-names = "default";
 580                 pinctrl-0 = <&i2c1_xfer>;
 581                 status = "disabled";
 582         };
 583
 584         pwm0: pwm@ff680000 {
 585                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 586                 reg = <0x0 0xff680000 0x0 0x10>;
 587                 #pwm-cells = <3>;
 588                 pinctrl-names = "default";
 589                 pinctrl-0 = <&pwm0_pin>;
 590                 clocks = <&cru PCLK_PWM1>;
 591                 clock-names = "pwm";
 592                 status = "disabled";
 593         };
 594
 595         pwm1: pwm@ff680010 {
 596                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 597                 reg = <0x0 0xff680010 0x0 0x10>;
 598                 #pwm-cells = <3>;
 599                 pinctrl-names = "default";
 600                 pinctrl-0 = <&pwm1_pin>;
 601                 clocks = <&cru PCLK_PWM1>;
 602                 clock-names = "pwm";
 603                 status = "disabled";
 604         };
 605
 606         pwm2: pwm@ff680020 {
 607                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 608                 reg = <0x0 0xff680020 0x0 0x10>;
 609                 #pwm-cells = <3>;
 610                 clocks = <&cru PCLK_PWM1>;
 611                 clock-names = "pwm";
 612                 status = "disabled";
 613         };
 614
 615         pwm3: pwm@ff680030 {
 616                 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm";
 617                 reg = <0x0 0xff680030 0x0 0x10>;
 618                 #pwm-cells = <3>;
 619                 pinctrl-names = "default";
 620                 pinctrl-0 = <&pwm3_pin>;
 621                 clocks = <&cru PCLK_PWM1>;
 622                 clock-names = "pwm";
 623                 status = "disabled";
 624         };
 625
 626         uart2: serial@ff690000 {
 627                 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart";
 628                 reg = <0x0 0xff690000 0x0 0x100>;
 629                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 630                 clock-names = "baudclk", "apb_pclk";
 631                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 632                 pinctrl-names = "default";
 633                 pinctrl-0 = <&uart2_xfer>;
 634                 reg-shift = <2>;
 635                 reg-io-width = <4>;
 636                 status = "disabled";
 637         };
 638
 639         mbox: mbox@ff6b0000 {
 640                 compatible = "rockchip,rk3368-mailbox";
 641                 reg = <0x0 0xff6b0000 0x0 0x1000>;
 642                 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
 643                              <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
 644                              <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
 645                              <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
 646                 clocks = <&cru PCLK_MAILBOX>;
 647                 clock-names = "pclk_mailbox";
 648                 #mbox-cells = <1>;
 649                 status = "disabled";
 650         };
 651
 652         pmugrf: syscon@ff738000 {
 653                 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd";
 654                 reg = <0x0 0xff738000 0x0 0x1000>;
 655
 656                 pmu_io_domains: io-domains {
 657                         compatible = "rockchip,rk3368-pmu-io-voltage-domain";
 658                         status = "disabled";
 659                 };
 660
 661                 reboot-mode {
 662                         compatible = "syscon-reboot-mode";
 663                         offset = <0x200>;
 664                         mode-normal = <BOOT_NORMAL>;
 665                         mode-recovery = <BOOT_RECOVERY>;
 666                         mode-bootloader = <BOOT_FASTBOOT>;
 667                         mode-loader = <BOOT_BL_DOWNLOAD>;
 668                 };
 669         };
 670
 671         cru: clock-controller@ff760000 {
 672                 compatible = "rockchip,rk3368-cru";
 673                 reg = <0x0 0xff760000 0x0 0x1000>;
 674                 rockchip,grf = <&grf>;
 675                 #clock-cells = <1>;
 676                 #reset-cells = <1>;
 677         };
 678
 679         grf: syscon@ff770000 {
 680                 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd";
 681                 reg = <0x0 0xff770000 0x0 0x1000>;
 682
 683                 io_domains: io-domains {
 684                         compatible = "rockchip,rk3368-io-voltage-domain";
 685                         status = "disabled";
 686                 };
 687         };
 688
 689         wdt: watchdog@ff800000 {
 690                 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt";
 691                 reg = <0x0 0xff800000 0x0 0x100>;
 692                 clocks = <&cru PCLK_WDT>;
 693                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 694                 status = "disabled";
 695         };
 696
 697         timer@ff810000 {
 698                 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer";
 699                 reg = <0x0 0xff810000 0x0 0x20>;
 700                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 701         };
 702
 703         spdif: spdif@ff880000 {
 704                 compatible = "rockchip,rk3368-spdif";
 705                 reg = <0x0 0xff880000 0x0 0x1000>;
 706                 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 707                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
 708                 clock-names = "mclk", "hclk";
 709                 dmas = <&dmac_bus 3>;
 710                 dma-names = "tx";
 711                 pinctrl-names = "default";
 712                 pinctrl-0 = <&spdif_tx>;
 713                 status = "disabled";
 714         };
 715
 716         i2s_2ch: i2s-2ch@ff890000 {
 717                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 718                 reg = <0x0 0xff890000 0x0 0x1000>;
 719                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 720                 clock-names = "i2s_clk", "i2s_hclk";
 721                 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>;
 722                 dmas = <&dmac_bus 6>, <&dmac_bus 7>;
 723                 dma-names = "tx", "rx";
 724                 status = "disabled";
 725         };
 726
 727         i2s_8ch: i2s-8ch@ff898000 {
 728                 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s";
 729                 reg = <0x0 0xff898000 0x0 0x1000>;
 730                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 731                 clock-names = "i2s_clk", "i2s_hclk";
 732                 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>;
 733                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
 734                 dma-names = "tx", "rx";
 735                 pinctrl-names = "default";
 736                 pinctrl-0 = <&i2s_8ch_bus>;
 737                 status = "disabled";
 738         };
 739
 740         iep_mmu: iommu@ff900800 {
 741                 compatible = "rockchip,iommu";
 742                 reg = <0x0 0xff900800 0x0 0x100>;
 743                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 744                 interrupt-names = "iep_mmu";
 745                 #iommu-cells = <0>;
 746                 status = "disabled";
 747         };
 748
 749         isp_mmu: iommu@ff914000 {
 750                 compatible = "rockchip,iommu";
 751                 reg = <0x0 0xff914000 0x0 0x100>,
 752                       <0x0 0xff915000 0x0 0x100>;
 753                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 754                 interrupt-names = "isp_mmu";
 755                 #iommu-cells = <0>;
 756                 rockchip,disable-mmu-reset;
 757                 status = "disabled";
 758         };
 759
 760         vop_mmu: iommu@ff930300 {
 761                 compatible = "rockchip,iommu";
 762                 reg = <0x0 0xff930300 0x0 0x100>;
 763                 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
 764                 interrupt-names = "vop_mmu";
 765                 #iommu-cells = <0>;
 766                 status = "disabled";
 767         };
 768
 769         hevc_mmu: iommu@ff9a0440 {
 770                 compatible = "rockchip,iommu";
 771                 reg = <0x0 0xff9a0440 0x0 0x40>,
 772                       <0x0 0xff9a0480 0x0 0x40>;
 773                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 774                 interrupt-names = "hevc_mmu";
 775                 #iommu-cells = <0>;
 776                 status = "disabled";
 777         };
 778
 779         vpu_mmu: iommu@ff9a0800 {
 780                 compatible = "rockchip,iommu";
 781                 reg = <0x0 0xff9a0800 0x0 0x100>;
 782                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 783                              <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 784                 interrupt-names = "vepu_mmu", "vdpu_mmu";
 785                 #iommu-cells = <0>;
 786                 status = "disabled";
 787         };
 788
 789         gic: interrupt-controller@ffb71000 {
 790                 compatible = "arm,gic-400";
 791                 interrupt-controller;
 792                 #interrupt-cells = <3>;
 793                 #address-cells = <0>;
 794
 795                 reg = <0x0 0xffb71000 0x0 0x1000>,
 796                       <0x0 0xffb72000 0x0 0x2000>,
 797                       <0x0 0xffb74000 0x0 0x2000>,
 798                       <0x0 0xffb76000 0x0 0x2000>;
 799                 interrupts = <GIC_PPI 9
 800                       (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
 801         };
 802
 803         pinctrl: pinctrl {
 804                 compatible = "rockchip,rk3368-pinctrl";
 805                 rockchip,grf = <&grf>;
 806                 rockchip,pmu = <&pmugrf>;
 807                 #address-cells = <0x2>;
 808                 #size-cells = <0x2>;
 809                 ranges;
 810
 811                 gpio0: gpio0@ff750000 {
 812                         compatible = "rockchip,gpio-bank";
 813                         reg = <0x0 0xff750000 0x0 0x100>;
 814                         clocks = <&cru PCLK_GPIO0>;
 815                         interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>;
 816
 817                         gpio-controller;
 818                         #gpio-cells = <0x2>;
 819
 820                         interrupt-controller;
 821                         #interrupt-cells = <0x2>;
 822                 };
 823
 824                 gpio1: gpio1@ff780000 {
 825                         compatible = "rockchip,gpio-bank";
 826                         reg = <0x0 0xff780000 0x0 0x100>;
 827                         clocks = <&cru PCLK_GPIO1>;
 828                         interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>;
 829
 830                         gpio-controller;
 831                         #gpio-cells = <0x2>;
 832
 833                         interrupt-controller;
 834                         #interrupt-cells = <0x2>;
 835                 };
 836
 837                 gpio2: gpio2@ff790000 {
 838                         compatible = "rockchip,gpio-bank";
 839                         reg = <0x0 0xff790000 0x0 0x100>;
 840                         clocks = <&cru PCLK_GPIO2>;
 841                         interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>;
 842
 843                         gpio-controller;
 844                         #gpio-cells = <0x2>;
 845
 846                         interrupt-controller;
 847                         #interrupt-cells = <0x2>;
 848                 };
 849
 850                 gpio3: gpio3@ff7a0000 {
 851                         compatible = "rockchip,gpio-bank";
 852                         reg = <0x0 0xff7a0000 0x0 0x100>;
 853                         clocks = <&cru PCLK_GPIO3>;
 854                         interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>;
 855
 856                         gpio-controller;
 857                         #gpio-cells = <0x2>;
 858
 859                         interrupt-controller;
 860                         #interrupt-cells = <0x2>;
 861                 };
 862
 863                 pcfg_pull_up: pcfg-pull-up {
 864                         bias-pull-up;
 865                 };
 866
 867                 pcfg_pull_down: pcfg-pull-down {
 868                         bias-pull-down;
 869                 };
 870
 871                 pcfg_pull_none: pcfg-pull-none {
 872                         bias-disable;
 873                 };
 874
 875                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
 876                         bias-disable;
 877                         drive-strength = <12>;
 878                 };
 879
 880                 emmc {
 881                         emmc_clk: emmc-clk {
 882                                 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
 883                         };
 884
 885                         emmc_cmd: emmc-cmd {
 886                                 rockchip,pins = <1 26 RK_FUNC_2 &pcfg_pull_up>;
 887                         };
 888
 889                         emmc_pwr: emmc-pwr {
 890                                 rockchip,pins = <1 27 RK_FUNC_2 &pcfg_pull_up>;
 891                         };
 892
 893                         emmc_bus1: emmc-bus1 {
 894                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>;
 895                         };
 896
 897                         emmc_bus4: emmc-bus4 {
 898                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 899                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 900                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 901                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>;
 902                         };
 903
 904                         emmc_bus8: emmc-bus8 {
 905                                 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_up>,
 906                                                 <1 19 RK_FUNC_2 &pcfg_pull_up>,
 907                                                 <1 20 RK_FUNC_2 &pcfg_pull_up>,
 908                                                 <1 21 RK_FUNC_2 &pcfg_pull_up>,
 909                                                 <1 22 RK_FUNC_2 &pcfg_pull_up>,
 910                                                 <1 23 RK_FUNC_2 &pcfg_pull_up>,
 911                                                 <1 24 RK_FUNC_2 &pcfg_pull_up>,
 912                                                 <1 25 RK_FUNC_2 &pcfg_pull_up>;
 913                         };
 914                 };
 915
 916                 gmac {
 917                         rgmii_pins: rgmii-pins {
 918                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 919                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 920                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 921                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 922                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 923                                                 <3 10 RK_FUNC_1 &pcfg_pull_none_12ma>,
 924                                                 <3 14 RK_FUNC_1 &pcfg_pull_none_12ma>,
 925                                                 <3 28 RK_FUNC_1 &pcfg_pull_none_12ma>,
 926                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 927                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 928                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 929                                                 <3 17 RK_FUNC_1 &pcfg_pull_none>,
 930                                                 <3 18 RK_FUNC_1 &pcfg_pull_none>,
 931                                                 <3 25 RK_FUNC_1 &pcfg_pull_none>,
 932                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>;
 933                         };
 934
 935                         rmii_pins: rmii-pins {
 936                                 rockchip,pins = <3 22 RK_FUNC_1 &pcfg_pull_none>,
 937                                                 <3 24 RK_FUNC_1 &pcfg_pull_none>,
 938                                                 <3 19 RK_FUNC_1 &pcfg_pull_none>,
 939                                                 <3 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
 940                                                 <3 9 RK_FUNC_1 &pcfg_pull_none_12ma>,
 941                                                 <3 13 RK_FUNC_1 &pcfg_pull_none_12ma>,
 942                                                 <3 15 RK_FUNC_1 &pcfg_pull_none>,
 943                                                 <3 16 RK_FUNC_1 &pcfg_pull_none>,
 944                                                 <3 20 RK_FUNC_1 &pcfg_pull_none>,
 945                                                 <3 21 RK_FUNC_1 &pcfg_pull_none>;
 946                         };
 947                 };
 948
 949                 i2c0 {
 950                         i2c0_xfer: i2c0-xfer {
 951                                 rockchip,pins = <0 6 RK_FUNC_1 &pcfg_pull_none>,
 952                                                 <0 7 RK_FUNC_1 &pcfg_pull_none>;
 953                         };
 954                 };
 955
 956                 i2c1 {
 957                         i2c1_xfer: i2c1-xfer {
 958                                 rockchip,pins = <2 21 RK_FUNC_1 &pcfg_pull_none>,
 959                                                 <2 22 RK_FUNC_1 &pcfg_pull_none>;
 960                         };
 961                 };
 962
 963                 i2c2 {
 964                         i2c2_xfer: i2c2-xfer {
 965                                 rockchip,pins = <0 9 RK_FUNC_2 &pcfg_pull_none>,
 966                                                 <3 31 RK_FUNC_2 &pcfg_pull_none>;
 967                         };
 968                 };
 969
 970                 i2c3 {
 971                         i2c3_xfer: i2c3-xfer {
 972                                 rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none>,
 973                                                 <1 17 RK_FUNC_1 &pcfg_pull_none>;
 974                         };
 975                 };
 976
 977                 i2c4 {
 978                         i2c4_xfer: i2c4-xfer {
 979                                 rockchip,pins = <3 24 RK_FUNC_2 &pcfg_pull_none>,
 980                                                 <3 25 RK_FUNC_2 &pcfg_pull_none>;
 981                         };
 982                 };
 983
 984                 i2c5 {
 985                         i2c5_xfer: i2c5-xfer {
 986                                 rockchip,pins = <3 26 RK_FUNC_2 &pcfg_pull_none>,
 987                                                 <3 27 RK_FUNC_2 &pcfg_pull_none>;
 988                         };
 989                 };
 990
 991                 i2s {
 992                         i2s_8ch_bus: i2s-8ch-bus {
 993                                 rockchip,pins = <2 12 RK_FUNC_1 &pcfg_pull_none>,
 994                                                 <2 13 RK_FUNC_1 &pcfg_pull_none>,
 995                                                 <2 14 RK_FUNC_1 &pcfg_pull_none>,
 996                                                 <2 15 RK_FUNC_1 &pcfg_pull_none>,
 997                                                 <2 16 RK_FUNC_1 &pcfg_pull_none>,
 998                                                 <2 17 RK_FUNC_1 &pcfg_pull_none>,
 999                                                 <2 18 RK_FUNC_1 &pcfg_pull_none>,
1000                                                 <2 19 RK_FUNC_1 &pcfg_pull_none>,
1001                                                 <2 20 RK_FUNC_1 &pcfg_pull_none>;
1002                         };
1003                 };
1004
1005                 pwm0 {
1006                         pwm0_pin: pwm0-pin {
1007                                 rockchip,pins = <3 8 RK_FUNC_2 &pcfg_pull_none>;
1008                         };
1009                 };
1010
1011                 pwm1 {
1012                         pwm1_pin: pwm1-pin {
1013                                 rockchip,pins = <0 8 RK_FUNC_2 &pcfg_pull_none>;
1014                         };
1015                 };
1016
1017                 pwm3 {
1018                         pwm3_pin: pwm3-pin {
1019                                 rockchip,pins = <3 29 RK_FUNC_3 &pcfg_pull_none>;
1020                         };
1021                 };
1022
1023                 sdio0 {
1024                         sdio0_bus1: sdio0-bus1 {
1025                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>;
1026                         };
1027
1028                         sdio0_bus4: sdio0-bus4 {
1029                                 rockchip,pins = <2 28 RK_FUNC_1 &pcfg_pull_up>,
1030                                                 <2 29 RK_FUNC_1 &pcfg_pull_up>,
1031                                                 <2 30 RK_FUNC_1 &pcfg_pull_up>,
1032                                                 <2 31 RK_FUNC_1 &pcfg_pull_up>;
1033                         };
1034
1035                         sdio0_cmd: sdio0-cmd {
1036                                 rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_up>;
1037                         };
1038
1039                         sdio0_clk: sdio0-clk {
1040                                 rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none>;
1041                         };
1042
1043                         sdio0_cd: sdio0-cd {
1044                                 rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_up>;
1045                         };
1046
1047                         sdio0_wp: sdio0-wp {
1048                                 rockchip,pins = <3 3 RK_FUNC_1 &pcfg_pull_up>;
1049                         };
1050
1051                         sdio0_pwr: sdio0-pwr {
1052                                 rockchip,pins = <3 4 RK_FUNC_1 &pcfg_pull_up>;
1053                         };
1054
1055                         sdio0_bkpwr: sdio0-bkpwr {
1056                                 rockchip,pins = <3 5 RK_FUNC_1 &pcfg_pull_up>;
1057                         };
1058
1059                         sdio0_int: sdio0-int {
1060                                 rockchip,pins = <3 6 RK_FUNC_1 &pcfg_pull_up>;
1061                         };
1062                 };
1063
1064                 sdmmc {
1065                         sdmmc_clk: sdmmc-clk {
1066                                 rockchip,pins = <2 9 RK_FUNC_1 &pcfg_pull_none>;
1067                         };
1068
1069                         sdmmc_cmd: sdmmc-cmd {
1070                                 rockchip,pins = <2 10 RK_FUNC_1 &pcfg_pull_up>;
1071                         };
1072
1073                         sdmmc_cd: sdmmc-cd {
1074                                 rockchip,pins = <2 11 RK_FUNC_1 &pcfg_pull_up>;
1075                         };
1076
1077                         sdmmc_bus1: sdmmc-bus1 {
1078                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>;
1079                         };
1080
1081                         sdmmc_bus4: sdmmc-bus4 {
1082                                 rockchip,pins = <2 5 RK_FUNC_1 &pcfg_pull_up>,
1083                                                 <2 6 RK_FUNC_1 &pcfg_pull_up>,
1084                                                 <2 7 RK_FUNC_1 &pcfg_pull_up>,
1085                                                 <2 8 RK_FUNC_1 &pcfg_pull_up>;
1086                         };
1087                 };
1088
1089                 spdif {
1090                         spdif_tx: spdif-tx {
1091                                 rockchip,pins = <2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;
1092                         };
1093                 };
1094
1095                 spi0 {
1096                         spi0_clk: spi0-clk {
1097                                 rockchip,pins = <1 29 RK_FUNC_2 &pcfg_pull_up>;
1098                         };
1099                         spi0_cs0: spi0-cs0 {
1100                                 rockchip,pins = <1 24 RK_FUNC_3 &pcfg_pull_up>;
1101                         };
1102                         spi0_cs1: spi0-cs1 {
1103                                 rockchip,pins = <1 25 RK_FUNC_3 &pcfg_pull_up>;
1104                         };
1105                         spi0_tx: spi0-tx {
1106                                 rockchip,pins = <1 23 RK_FUNC_3 &pcfg_pull_up>;
1107                         };
1108                         spi0_rx: spi0-rx {
1109                                 rockchip,pins = <1 22 RK_FUNC_3 &pcfg_pull_up>;
1110                         };
1111                 };
1112
1113                 spi1 {
1114                         spi1_clk: spi1-clk {
1115                                 rockchip,pins = <1 14 RK_FUNC_2 &pcfg_pull_up>;
1116                         };
1117                         spi1_cs0: spi1-cs0 {
1118                                 rockchip,pins = <1 15 RK_FUNC_2 &pcfg_pull_up>;
1119                         };
1120                         spi1_cs1: spi1-cs1 {
1121                                 rockchip,pins = <3 28 RK_FUNC_2 &pcfg_pull_up>;
1122                         };
1123                         spi1_rx: spi1-rx {
1124                                 rockchip,pins = <1 16 RK_FUNC_2 &pcfg_pull_up>;
1125                         };
1126                         spi1_tx: spi1-tx {
1127                                 rockchip,pins = <1 17 RK_FUNC_2 &pcfg_pull_up>;
1128                         };
1129                 };
1130
1131                 spi2 {
1132                         spi2_clk: spi2-clk {
1133                                 rockchip,pins = <0 12 RK_FUNC_2 &pcfg_pull_up>;
1134                         };
1135                         spi2_cs0: spi2-cs0 {
1136                                 rockchip,pins = <0 13 RK_FUNC_2 &pcfg_pull_up>;
1137                         };
1138                         spi2_rx: spi2-rx {
1139                                 rockchip,pins = <0 10 RK_FUNC_2 &pcfg_pull_up>;
1140                         };
1141                         spi2_tx: spi2-tx {
1142                                 rockchip,pins = <0 11 RK_FUNC_2 &pcfg_pull_up>;
1143                         };
1144                 };
1145
1146                 tsadc {
1147                         otp_gpio: otp-gpio {
1148                                 rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;
1149                         };
1150
1151                         otp_out: otp-out {
1152                                 rockchip,pins = <0 3 RK_FUNC_1 &pcfg_pull_none>;
1153                         };
1154                 };
1155
1156                 uart0 {
1157                         uart0_xfer: uart0-xfer {
1158                                 rockchip,pins = <2 24 RK_FUNC_1 &pcfg_pull_up>,
1159                                                 <2 25 RK_FUNC_1 &pcfg_pull_none>;
1160                         };
1161
1162                         uart0_cts: uart0-cts {
1163                                 rockchip,pins = <2 26 RK_FUNC_1 &pcfg_pull_none>;
1164                         };
1165
1166                         uart0_rts: uart0-rts {
1167                                 rockchip,pins = <2 27 RK_FUNC_1 &pcfg_pull_none>;
1168                         };
1169                 };
1170
1171                 uart1 {
1172                         uart1_xfer: uart1-xfer {
1173                                 rockchip,pins = <0 20 RK_FUNC_3 &pcfg_pull_up>,
1174                                                 <0 21 RK_FUNC_3 &pcfg_pull_none>;
1175                         };
1176
1177                         uart1_cts: uart1-cts {
1178                                 rockchip,pins = <0 22 RK_FUNC_3 &pcfg_pull_none>;
1179                         };
1180
1181                         uart1_rts: uart1-rts {
1182                                 rockchip,pins = <0 23 RK_FUNC_3 &pcfg_pull_none>;
1183                         };
1184                 };
1185
1186                 uart2 {
1187                         uart2_xfer: uart2-xfer {
1188                                 rockchip,pins = <2 6 RK_FUNC_2 &pcfg_pull_up>,
1189                                                 <2 5 RK_FUNC_2 &pcfg_pull_none>;
1190                         };
1191                         /* no rts / cts for uart2 */
1192                 };
1193
1194                 uart3 {
1195                         uart3_xfer: uart3-xfer {
1196                                 rockchip,pins = <3 29 RK_FUNC_2 &pcfg_pull_up>,
1197                                                 <3 30 RK_FUNC_3 &pcfg_pull_none>;
1198                         };
1199
1200                         uart3_cts: uart3-cts {
1201                                 rockchip,pins = <3 16 RK_FUNC_2 &pcfg_pull_none>;
1202                         };
1203
1204                         uart3_rts: uart3-rts {
1205                                 rockchip,pins = <3 17 RK_FUNC_2 &pcfg_pull_none>;
1206                         };
1207                 };
1208
1209                 uart4 {
1210                         uart4_xfer: uart4-xfer {
1211                                 rockchip,pins = <0 27 RK_FUNC_3 &pcfg_pull_up>,
1212                                                 <0 26 RK_FUNC_3 &pcfg_pull_none>;
1213                         };
1214
1215                         uart4_cts: uart4-cts {
1216                                 rockchip,pins = <0 24 RK_FUNC_3 &pcfg_pull_none>;
1217                         };
1218
1219                         uart4_rts: uart4-rts {
1220                                 rockchip,pins = <0 25 RK_FUNC_3 &pcfg_pull_none>;
1221                         };
1222                 };
1223         };
1224 };