1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
6 #include <dt-bindings/clock/rk3328-cru.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/pinctrl/rockchip.h>
11 #include <dt-bindings/power/rk3328-power.h>
12 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #include <dt-bindings/thermal/thermal.h>
16 compatible = "rockchip,rk3328";
18 interrupt-parent = <&gic>;
31 ethernet1 = &gmac2phy;
40 compatible = "arm,cortex-a53";
42 clocks = <&cru ARMCLK>;
44 dynamic-power-coefficient = <120>;
45 enable-method = "psci";
46 next-level-cache = <&l2>;
47 operating-points-v2 = <&cpu0_opp_table>;
52 compatible = "arm,cortex-a53";
54 clocks = <&cru ARMCLK>;
56 dynamic-power-coefficient = <120>;
57 enable-method = "psci";
58 next-level-cache = <&l2>;
59 operating-points-v2 = <&cpu0_opp_table>;
64 compatible = "arm,cortex-a53";
66 clocks = <&cru ARMCLK>;
68 dynamic-power-coefficient = <120>;
69 enable-method = "psci";
70 next-level-cache = <&l2>;
71 operating-points-v2 = <&cpu0_opp_table>;
76 compatible = "arm,cortex-a53";
78 clocks = <&cru ARMCLK>;
80 dynamic-power-coefficient = <120>;
81 enable-method = "psci";
82 next-level-cache = <&l2>;
83 operating-points-v2 = <&cpu0_opp_table>;
91 cpu0_opp_table: opp_table0 {
92 compatible = "operating-points-v2";
96 opp-hz = /bits/ 64 <408000000>;
97 opp-microvolt = <950000>;
98 clock-latency-ns = <40000>;
102 opp-hz = /bits/ 64 <600000000>;
103 opp-microvolt = <950000>;
104 clock-latency-ns = <40000>;
107 opp-hz = /bits/ 64 <816000000>;
108 opp-microvolt = <1000000>;
109 clock-latency-ns = <40000>;
112 opp-hz = /bits/ 64 <1008000000>;
113 opp-microvolt = <1100000>;
114 clock-latency-ns = <40000>;
117 opp-hz = /bits/ 64 <1200000000>;
118 opp-microvolt = <1225000>;
119 clock-latency-ns = <40000>;
122 opp-hz = /bits/ 64 <1296000000>;
123 opp-microvolt = <1300000>;
124 clock-latency-ns = <40000>;
129 compatible = "simple-bus";
130 #address-cells = <2>;
134 dmac: dmac@ff1f0000 {
135 compatible = "arm,pl330", "arm,primecell";
136 reg = <0x0 0xff1f0000 0x0 0x4000>;
137 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&cru ACLK_DMAC>;
140 clock-names = "apb_pclk";
146 compatible = "arm,cortex-a53-pmu";
147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 display_subsystem: display-subsystem {
155 compatible = "rockchip,display-subsystem";
160 compatible = "arm,psci-1.0", "arm,psci-0.2";
165 compatible = "arm,armv8-timer";
166 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
167 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
168 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
169 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
173 compatible = "fixed-clock";
175 clock-frequency = <24000000>;
176 clock-output-names = "xin24m";
180 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
181 reg = <0x0 0xff000000 0x0 0x1000>;
182 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
183 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
184 clock-names = "i2s_clk", "i2s_hclk";
185 dmas = <&dmac 11>, <&dmac 12>;
186 dma-names = "tx", "rx";
187 #sound-dai-cells = <0>;
192 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
193 reg = <0x0 0xff010000 0x0 0x1000>;
194 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
195 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
196 clock-names = "i2s_clk", "i2s_hclk";
197 dmas = <&dmac 14>, <&dmac 15>;
198 dma-names = "tx", "rx";
199 #sound-dai-cells = <0>;
204 compatible = "rockchip,rk3328-i2s", "rockchip,rk3066-i2s";
205 reg = <0x0 0xff020000 0x0 0x1000>;
206 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
208 clock-names = "i2s_clk", "i2s_hclk";
209 dmas = <&dmac 0>, <&dmac 1>;
210 dma-names = "tx", "rx";
211 #sound-dai-cells = <0>;
215 spdif: spdif@ff030000 {
216 compatible = "rockchip,rk3328-spdif";
217 reg = <0x0 0xff030000 0x0 0x1000>;
218 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
220 clock-names = "mclk", "hclk";
223 pinctrl-names = "default";
224 pinctrl-0 = <&spdifm2_tx>;
225 #sound-dai-cells = <0>;
230 compatible = "rockchip,pdm";
231 reg = <0x0 0xff040000 0x0 0x1000>;
232 clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
233 clock-names = "pdm_clk", "pdm_hclk";
236 pinctrl-names = "default", "sleep";
237 pinctrl-0 = <&pdmm0_clk
242 pinctrl-1 = <&pdmm0_clk_sleep
250 grf: syscon@ff100000 {
251 compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
252 reg = <0x0 0xff100000 0x0 0x1000>;
253 #address-cells = <1>;
256 io_domains: io-domains {
257 compatible = "rockchip,rk3328-io-voltage-domain";
262 compatible = "rockchip,rk3328-grf-gpio";
267 power: power-controller {
268 compatible = "rockchip,rk3328-power-controller";
269 #power-domain-cells = <1>;
270 #address-cells = <1>;
273 pd_hevc@RK3328_PD_HEVC {
274 reg = <RK3328_PD_HEVC>;
276 pd_video@RK3328_PD_VIDEO {
277 reg = <RK3328_PD_VIDEO>;
279 pd_vpu@RK3328_PD_VPU {
280 reg = <RK3328_PD_VPU>;
281 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
286 compatible = "syscon-reboot-mode";
288 mode-normal = <BOOT_NORMAL>;
289 mode-recovery = <BOOT_RECOVERY>;
290 mode-bootloader = <BOOT_FASTBOOT>;
291 mode-loader = <BOOT_BL_DOWNLOAD>;
295 uart0: serial@ff110000 {
296 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
297 reg = <0x0 0xff110000 0x0 0x100>;
298 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
300 clock-names = "baudclk", "apb_pclk";
301 dmas = <&dmac 2>, <&dmac 3>;
302 dma-names = "tx", "rx";
303 pinctrl-names = "default";
304 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
310 uart1: serial@ff120000 {
311 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
312 reg = <0x0 0xff120000 0x0 0x100>;
313 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
315 clock-names = "baudclk", "apb_pclk";
316 dmas = <&dmac 4>, <&dmac 5>;
317 dma-names = "tx", "rx";
318 pinctrl-names = "default";
319 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
325 uart2: serial@ff130000 {
326 compatible = "rockchip,rk3328-uart", "snps,dw-apb-uart";
327 reg = <0x0 0xff130000 0x0 0x100>;
328 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
330 clock-names = "baudclk", "apb_pclk";
331 dmas = <&dmac 6>, <&dmac 7>;
332 dma-names = "tx", "rx";
333 pinctrl-names = "default";
334 pinctrl-0 = <&uart2m1_xfer>;
341 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
342 reg = <0x0 0xff150000 0x0 0x1000>;
343 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
344 #address-cells = <1>;
346 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
347 clock-names = "i2c", "pclk";
348 pinctrl-names = "default";
349 pinctrl-0 = <&i2c0_xfer>;
354 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
355 reg = <0x0 0xff160000 0x0 0x1000>;
356 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
357 #address-cells = <1>;
359 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
360 clock-names = "i2c", "pclk";
361 pinctrl-names = "default";
362 pinctrl-0 = <&i2c1_xfer>;
367 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
368 reg = <0x0 0xff170000 0x0 0x1000>;
369 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
370 #address-cells = <1>;
372 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
373 clock-names = "i2c", "pclk";
374 pinctrl-names = "default";
375 pinctrl-0 = <&i2c2_xfer>;
380 compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
381 reg = <0x0 0xff180000 0x0 0x1000>;
382 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
385 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
386 clock-names = "i2c", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c3_xfer>;
393 compatible = "rockchip,rk3328-spi", "rockchip,rk3066-spi";
394 reg = <0x0 0xff190000 0x0 0x1000>;
395 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
396 #address-cells = <1>;
398 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
399 clock-names = "spiclk", "apb_pclk";
400 dmas = <&dmac 8>, <&dmac 9>;
401 dma-names = "tx", "rx";
402 pinctrl-names = "default";
403 pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
407 wdt: watchdog@ff1a0000 {
408 compatible = "snps,dw-wdt";
409 reg = <0x0 0xff1a0000 0x0 0x100>;
410 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&cru PCLK_WDT>;
415 compatible = "rockchip,rk3328-pwm";
416 reg = <0x0 0xff1b0000 0x0 0x10>;
417 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
418 clock-names = "pwm", "pclk";
419 pinctrl-names = "default";
420 pinctrl-0 = <&pwm0_pin>;
426 compatible = "rockchip,rk3328-pwm";
427 reg = <0x0 0xff1b0010 0x0 0x10>;
428 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
429 clock-names = "pwm", "pclk";
430 pinctrl-names = "default";
431 pinctrl-0 = <&pwm1_pin>;
437 compatible = "rockchip,rk3328-pwm";
438 reg = <0x0 0xff1b0020 0x0 0x10>;
439 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
440 clock-names = "pwm", "pclk";
441 pinctrl-names = "default";
442 pinctrl-0 = <&pwm2_pin>;
448 compatible = "rockchip,rk3328-pwm";
449 reg = <0x0 0xff1b0030 0x0 0x10>;
450 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
451 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
452 clock-names = "pwm", "pclk";
453 pinctrl-names = "default";
454 pinctrl-0 = <&pwmir_pin>;
460 soc_thermal: soc-thermal {
461 polling-delay-passive = <20>;
462 polling-delay = <1000>;
463 sustainable-power = <1000>;
465 thermal-sensors = <&tsadc 0>;
468 threshold: trip-point0 {
469 temperature = <70000>;
473 target: trip-point1 {
474 temperature = <85000>;
479 temperature = <95000>;
488 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
489 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
490 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
491 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
492 contribution = <4096>;
499 tsadc: tsadc@ff250000 {
500 compatible = "rockchip,rk3328-tsadc";
501 reg = <0x0 0xff250000 0x0 0x100>;
502 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
503 assigned-clocks = <&cru SCLK_TSADC>;
504 assigned-clock-rates = <50000>;
505 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
506 clock-names = "tsadc", "apb_pclk";
507 pinctrl-names = "init", "default", "sleep";
508 pinctrl-0 = <&otp_gpio>;
509 pinctrl-1 = <&otp_out>;
510 pinctrl-2 = <&otp_gpio>;
511 resets = <&cru SRST_TSADC>;
512 reset-names = "tsadc-apb";
513 rockchip,grf = <&grf>;
514 rockchip,hw-tshut-temp = <100000>;
515 #thermal-sensor-cells = <1>;
519 efuse: efuse@ff260000 {
520 compatible = "rockchip,rk3328-efuse";
521 reg = <0x0 0xff260000 0x0 0x50>;
522 #address-cells = <1>;
524 clocks = <&cru SCLK_EFUSE>;
525 clock-names = "pclk_efuse";
526 rockchip,efuse-size = <0x20>;
532 cpu_leakage: cpu-leakage@17 {
535 logic_leakage: logic-leakage@19 {
538 efuse_cpu_version: cpu-version@1a {
544 saradc: adc@ff280000 {
545 compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
546 reg = <0x0 0xff280000 0x0 0x100>;
547 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
548 #io-channel-cells = <1>;
549 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
550 clock-names = "saradc", "apb_pclk";
551 resets = <&cru SRST_SARADC_P>;
552 reset-names = "saradc-apb";
557 compatible = "rockchip,rk3328-mali", "arm,mali-450";
558 reg = <0x0 0xff300000 0x0 0x40000>;
559 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
566 interrupt-names = "gp",
573 clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
574 clock-names = "bus", "core";
575 resets = <&cru SRST_GPU_A>;
578 h265e_mmu: iommu@ff330200 {
579 compatible = "rockchip,iommu";
580 reg = <0x0 0xff330200 0 0x100>;
581 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
582 interrupt-names = "h265e_mmu";
583 clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
584 clock-names = "aclk", "iface";
589 vepu_mmu: iommu@ff340800 {
590 compatible = "rockchip,iommu";
591 reg = <0x0 0xff340800 0x0 0x40>;
592 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-names = "vepu_mmu";
594 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
595 clock-names = "aclk", "iface";
600 vpu: video-codec@ff350000 {
601 compatible = "rockchip,rk3328-vpu";
602 reg = <0x0 0xff350000 0x0 0x800>;
603 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
604 interrupt-names = "vdpu";
605 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
606 clock-names = "aclk", "hclk";
608 power-domains = <&power RK3328_PD_VPU>;
611 vpu_mmu: iommu@ff350800 {
612 compatible = "rockchip,iommu";
613 reg = <0x0 0xff350800 0x0 0x40>;
614 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
615 interrupt-names = "vpu_mmu";
616 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
617 clock-names = "aclk", "iface";
619 power-domains = <&power RK3328_PD_VPU>;
622 rkvdec_mmu: iommu@ff360480 {
623 compatible = "rockchip,iommu";
624 reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
625 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
626 interrupt-names = "rkvdec_mmu";
627 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
628 clock-names = "aclk", "iface";
634 compatible = "rockchip,rk3328-vop";
635 reg = <0x0 0xff370000 0x0 0x3efc>;
636 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
638 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
639 resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru SRST_VOP_D>;
640 reset-names = "axi", "ahb", "dclk";
645 #address-cells = <1>;
648 vop_out_hdmi: endpoint@0 {
650 remote-endpoint = <&hdmi_in_vop>;
655 vop_mmu: iommu@ff373f00 {
656 compatible = "rockchip,iommu";
657 reg = <0x0 0xff373f00 0x0 0x100>;
658 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
659 interrupt-names = "vop_mmu";
660 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
661 clock-names = "aclk", "iface";
666 hdmi: hdmi@ff3c0000 {
667 compatible = "rockchip,rk3328-dw-hdmi";
668 reg = <0x0 0xff3c0000 0x0 0x20000>;
670 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&cru PCLK_HDMI>,
673 <&cru SCLK_HDMI_SFC>,
675 clock-names = "iahb",
680 pinctrl-names = "default";
681 pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
682 rockchip,grf = <&grf>;
683 #sound-dai-cells = <0>;
688 hdmi_in_vop: endpoint {
689 remote-endpoint = <&vop_out_hdmi>;
695 codec: codec@ff410000 {
696 compatible = "rockchip,rk3328-codec";
697 reg = <0x0 0xff410000 0x0 0x1000>;
698 clocks = <&cru PCLK_ACODECPHY>, <&cru SCLK_I2S1>;
699 clock-names = "pclk", "mclk";
700 rockchip,grf = <&grf>;
701 #sound-dai-cells = <0>;
705 hdmiphy: phy@ff430000 {
706 compatible = "rockchip,rk3328-hdmi-phy";
707 reg = <0x0 0xff430000 0x0 0x10000>;
708 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
709 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
710 clock-names = "sysclk", "refoclk", "refpclk";
711 clock-output-names = "hdmi_phy";
713 nvmem-cells = <&efuse_cpu_version>;
714 nvmem-cell-names = "cpu-version";
719 cru: clock-controller@ff440000 {
720 compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
721 reg = <0x0 0xff440000 0x0 0x1000>;
722 rockchip,grf = <&grf>;
727 * CPLL should run at 1200, but that is to high for
728 * the initial dividers of most of its children.
729 * We need set cpll child clk div first,
730 * and then set the cpll frequency.
732 <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
733 <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
734 <&cru SCLK_UART1>, <&cru SCLK_UART2>,
735 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
736 <&cru ACLK_VIO_PRE>, <&cru ACLK_RGA_PRE>,
737 <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
738 <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
739 <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
740 <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
741 <&cru SCLK_SDIO>, <&cru SCLK_TSP>,
742 <&cru SCLK_WIFI>, <&cru ARMCLK>,
743 <&cru PLL_GPLL>, <&cru PLL_CPLL>,
744 <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
745 <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
746 <&cru HCLK_PERI>, <&cru PCLK_PERI>,
748 assigned-clock-parents =
749 <&cru HDMIPHY>, <&cru PLL_APLL>,
750 <&cru PLL_GPLL>, <&xin24m>,
751 <&xin24m>, <&xin24m>;
752 assigned-clock-rates =
755 <24000000>, <24000000>,
756 <15000000>, <15000000>,
757 <100000000>, <100000000>,
758 <100000000>, <100000000>,
759 <50000000>, <100000000>,
760 <100000000>, <100000000>,
761 <50000000>, <50000000>,
762 <50000000>, <50000000>,
763 <24000000>, <600000000>,
764 <491520000>, <1200000000>,
765 <150000000>, <75000000>,
766 <75000000>, <150000000>,
767 <75000000>, <75000000>,
771 usb2phy_grf: syscon@ff450000 {
772 compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
774 reg = <0x0 0xff450000 0x0 0x10000>;
775 #address-cells = <1>;
778 u2phy: usb2-phy@100 {
779 compatible = "rockchip,rk3328-usb2phy";
782 clock-names = "phyclk";
783 clock-output-names = "usb480m_phy";
785 assigned-clocks = <&cru USB480M>;
786 assigned-clock-parents = <&u2phy>;
789 u2phy_otg: otg-port {
791 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
792 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
793 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
794 interrupt-names = "otg-bvalid", "otg-id",
799 u2phy_host: host-port {
801 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
802 interrupt-names = "linestate";
808 sdmmc: dwmmc@ff500000 {
809 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
810 reg = <0x0 0xff500000 0x0 0x4000>;
811 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
812 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
813 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
814 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
815 fifo-depth = <0x100>;
816 max-frequency = <150000000>;
820 sdio: dwmmc@ff510000 {
821 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
822 reg = <0x0 0xff510000 0x0 0x4000>;
823 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
825 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
826 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
827 fifo-depth = <0x100>;
828 max-frequency = <150000000>;
832 emmc: dwmmc@ff520000 {
833 compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc";
834 reg = <0x0 0xff520000 0x0 0x4000>;
835 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
836 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
837 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
838 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
839 fifo-depth = <0x100>;
840 max-frequency = <150000000>;
844 gmac2io: ethernet@ff540000 {
845 compatible = "rockchip,rk3328-gmac";
846 reg = <0x0 0xff540000 0x0 0x10000>;
847 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
848 interrupt-names = "macirq";
849 clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
850 <&cru SCLK_MAC2IO_TX>, <&cru SCLK_MAC2IO_REF>,
851 <&cru SCLK_MAC2IO_REFOUT>, <&cru ACLK_MAC2IO>,
853 clock-names = "stmmaceth", "mac_clk_rx",
854 "mac_clk_tx", "clk_mac_ref",
855 "clk_mac_refout", "aclk_mac",
857 resets = <&cru SRST_GMAC2IO_A>;
858 reset-names = "stmmaceth";
859 rockchip,grf = <&grf>;
863 gmac2phy: ethernet@ff550000 {
864 compatible = "rockchip,rk3328-gmac";
865 reg = <0x0 0xff550000 0x0 0x10000>;
866 rockchip,grf = <&grf>;
867 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
868 interrupt-names = "macirq";
869 clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
870 <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
871 <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
872 <&cru SCLK_MAC2PHY_OUT>;
873 clock-names = "stmmaceth", "mac_clk_rx",
874 "mac_clk_tx", "clk_mac_ref",
875 "aclk_mac", "pclk_mac",
877 resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
878 reset-names = "stmmaceth", "mac-phy";
884 compatible = "snps,dwmac-mdio";
885 #address-cells = <1>;
889 compatible = "ethernet-phy-id1234.d400", "ethernet-phy-ieee802.3-c22";
891 clocks = <&cru SCLK_MAC2PHY_OUT>;
892 resets = <&cru SRST_MACPHY>;
893 pinctrl-names = "default";
894 pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
900 usb20_otg: usb@ff580000 {
901 compatible = "rockchip,rk3328-usb", "rockchip,rk3066-usb",
903 reg = <0x0 0xff580000 0x0 0x40000>;
904 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
905 clocks = <&cru HCLK_OTG>;
908 g-np-tx-fifo-size = <16>;
909 g-rx-fifo-size = <280>;
910 g-tx-fifo-size = <256 128 128 64 32 16>;
913 phy-names = "usb2-phy";
917 usb_host0_ehci: usb@ff5c0000 {
918 compatible = "generic-ehci";
919 reg = <0x0 0xff5c0000 0x0 0x10000>;
920 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&cru HCLK_HOST0>, <&u2phy>;
922 clock-names = "usbhost", "utmi";
923 phys = <&u2phy_host>;
928 usb_host0_ohci: usb@ff5d0000 {
929 compatible = "generic-ohci";
930 reg = <0x0 0xff5d0000 0x0 0x10000>;
931 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
932 clocks = <&cru HCLK_HOST0>, <&u2phy>;
933 clock-names = "usbhost", "utmi";
934 phys = <&u2phy_host>;
939 gic: interrupt-controller@ff811000 {
940 compatible = "arm,gic-400";
941 #interrupt-cells = <3>;
942 #address-cells = <0>;
943 interrupt-controller;
944 reg = <0x0 0xff811000 0 0x1000>,
945 <0x0 0xff812000 0 0x2000>,
946 <0x0 0xff814000 0 0x2000>,
947 <0x0 0xff816000 0 0x2000>;
948 interrupts = <GIC_PPI 9
949 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
953 compatible = "rockchip,rk3328-pinctrl";
954 rockchip,grf = <&grf>;
955 #address-cells = <2>;
959 gpio0: gpio0@ff210000 {
960 compatible = "rockchip,gpio-bank";
961 reg = <0x0 0xff210000 0x0 0x100>;
962 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&cru PCLK_GPIO0>;
968 interrupt-controller;
969 #interrupt-cells = <2>;
972 gpio1: gpio1@ff220000 {
973 compatible = "rockchip,gpio-bank";
974 reg = <0x0 0xff220000 0x0 0x100>;
975 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&cru PCLK_GPIO1>;
981 interrupt-controller;
982 #interrupt-cells = <2>;
985 gpio2: gpio2@ff230000 {
986 compatible = "rockchip,gpio-bank";
987 reg = <0x0 0xff230000 0x0 0x100>;
988 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
989 clocks = <&cru PCLK_GPIO2>;
994 interrupt-controller;
995 #interrupt-cells = <2>;
998 gpio3: gpio3@ff240000 {
999 compatible = "rockchip,gpio-bank";
1000 reg = <0x0 0xff240000 0x0 0x100>;
1001 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1002 clocks = <&cru PCLK_GPIO3>;
1007 interrupt-controller;
1008 #interrupt-cells = <2>;
1011 pcfg_pull_up: pcfg-pull-up {
1015 pcfg_pull_down: pcfg-pull-down {
1019 pcfg_pull_none: pcfg-pull-none {
1023 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
1025 drive-strength = <2>;
1028 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
1030 drive-strength = <2>;
1033 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
1035 drive-strength = <4>;
1038 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1040 drive-strength = <4>;
1043 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
1045 drive-strength = <4>;
1048 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
1050 drive-strength = <8>;
1053 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
1055 drive-strength = <8>;
1058 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1060 drive-strength = <12>;
1063 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
1065 drive-strength = <12>;
1068 pcfg_output_high: pcfg-output-high {
1072 pcfg_output_low: pcfg-output-low {
1076 pcfg_input_high: pcfg-input-high {
1081 pcfg_input: pcfg-input {
1086 i2c0_xfer: i2c0-xfer {
1087 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
1088 <2 RK_PD1 1 &pcfg_pull_none>;
1093 i2c1_xfer: i2c1-xfer {
1094 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
1095 <2 RK_PA5 2 &pcfg_pull_none>;
1100 i2c2_xfer: i2c2-xfer {
1101 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
1102 <2 RK_PB6 1 &pcfg_pull_none>;
1107 i2c3_xfer: i2c3-xfer {
1108 rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
1109 <0 RK_PA6 2 &pcfg_pull_none>;
1111 i2c3_gpio: i2c3-gpio {
1113 <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
1114 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
1119 hdmii2c_xfer: hdmii2c-xfer {
1120 rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
1121 <0 RK_PA6 1 &pcfg_pull_none>;
1126 pdmm0_clk: pdmm0-clk {
1127 rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
1130 pdmm0_fsync: pdmm0-fsync {
1131 rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
1134 pdmm0_sdi0: pdmm0-sdi0 {
1135 rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
1138 pdmm0_sdi1: pdmm0-sdi1 {
1139 rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
1142 pdmm0_sdi2: pdmm0-sdi2 {
1143 rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
1146 pdmm0_sdi3: pdmm0-sdi3 {
1147 rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
1150 pdmm0_clk_sleep: pdmm0-clk-sleep {
1152 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>;
1155 pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
1157 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>;
1160 pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
1162 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>;
1165 pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
1167 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>;
1170 pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
1172 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>;
1175 pdmm0_fsync_sleep: pdmm0-fsync-sleep {
1177 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1182 otp_gpio: otp-gpio {
1183 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1187 rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
1192 uart0_xfer: uart0-xfer {
1193 rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
1194 <1 RK_PB0 1 &pcfg_pull_none>;
1197 uart0_cts: uart0-cts {
1198 rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
1201 uart0_rts: uart0-rts {
1202 rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
1205 uart0_rts_gpio: uart0-rts-gpio {
1206 rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
1211 uart1_xfer: uart1-xfer {
1212 rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
1213 <3 RK_PA6 4 &pcfg_pull_none>;
1216 uart1_cts: uart1-cts {
1217 rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
1220 uart1_rts: uart1-rts {
1221 rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
1224 uart1_rts_gpio: uart1-rts-gpio {
1225 rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
1230 uart2m0_xfer: uart2m0-xfer {
1231 rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
1232 <1 RK_PA1 2 &pcfg_pull_none>;
1237 uart2m1_xfer: uart2m1-xfer {
1238 rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
1239 <2 RK_PA1 1 &pcfg_pull_none>;
1244 spi0m0_clk: spi0m0-clk {
1245 rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
1248 spi0m0_cs0: spi0m0-cs0 {
1249 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
1252 spi0m0_tx: spi0m0-tx {
1253 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
1256 spi0m0_rx: spi0m0-rx {
1257 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
1260 spi0m0_cs1: spi0m0-cs1 {
1261 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
1266 spi0m1_clk: spi0m1-clk {
1267 rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
1270 spi0m1_cs0: spi0m1-cs0 {
1271 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
1274 spi0m1_tx: spi0m1-tx {
1275 rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
1278 spi0m1_rx: spi0m1-rx {
1279 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
1282 spi0m1_cs1: spi0m1-cs1 {
1283 rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
1288 spi0m2_clk: spi0m2-clk {
1289 rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
1292 spi0m2_cs0: spi0m2-cs0 {
1293 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
1296 spi0m2_tx: spi0m2-tx {
1297 rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
1300 spi0m2_rx: spi0m2-rx {
1301 rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
1306 i2s1_mclk: i2s1-mclk {
1307 rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
1310 i2s1_sclk: i2s1-sclk {
1311 rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
1314 i2s1_lrckrx: i2s1-lrckrx {
1315 rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
1318 i2s1_lrcktx: i2s1-lrcktx {
1319 rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
1322 i2s1_sdi: i2s1-sdi {
1323 rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
1326 i2s1_sdo: i2s1-sdo {
1327 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
1330 i2s1_sdio1: i2s1-sdio1 {
1331 rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
1334 i2s1_sdio2: i2s1-sdio2 {
1335 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
1338 i2s1_sdio3: i2s1-sdio3 {
1339 rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
1342 i2s1_sleep: i2s1-sleep {
1344 <2 RK_PB7 RK_FUNC_GPIO &pcfg_input_high>,
1345 <2 RK_PC0 RK_FUNC_GPIO &pcfg_input_high>,
1346 <2 RK_PC1 RK_FUNC_GPIO &pcfg_input_high>,
1347 <2 RK_PC2 RK_FUNC_GPIO &pcfg_input_high>,
1348 <2 RK_PC3 RK_FUNC_GPIO &pcfg_input_high>,
1349 <2 RK_PC4 RK_FUNC_GPIO &pcfg_input_high>,
1350 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1351 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1352 <2 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>;
1357 i2s2m0_mclk: i2s2m0-mclk {
1358 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1361 i2s2m0_sclk: i2s2m0-sclk {
1362 rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
1365 i2s2m0_lrckrx: i2s2m0-lrckrx {
1366 rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
1369 i2s2m0_lrcktx: i2s2m0-lrcktx {
1370 rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
1373 i2s2m0_sdi: i2s2m0-sdi {
1374 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
1377 i2s2m0_sdo: i2s2m0-sdo {
1378 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
1381 i2s2m0_sleep: i2s2m0-sleep {
1383 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1384 <1 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>,
1385 <1 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>,
1386 <1 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>,
1387 <1 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>,
1388 <1 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>;
1393 i2s2m1_mclk: i2s2m1-mclk {
1394 rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
1397 i2s2m1_sclk: i2s2m1-sclk {
1398 rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
1401 i2s2m1_lrckrx: i2sm1-lrckrx {
1402 rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
1405 i2s2m1_lrcktx: i2s2m1-lrcktx {
1406 rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
1409 i2s2m1_sdi: i2s2m1-sdi {
1410 rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
1413 i2s2m1_sdo: i2s2m1-sdo {
1414 rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
1417 i2s2m1_sleep: i2s2m1-sleep {
1419 <1 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>,
1420 <3 RK_PA0 RK_FUNC_GPIO &pcfg_input_high>,
1421 <3 RK_PB0 RK_FUNC_GPIO &pcfg_input_high>,
1422 <3 RK_PA2 RK_FUNC_GPIO &pcfg_input_high>,
1423 <3 RK_PA1 RK_FUNC_GPIO &pcfg_input_high>;
1428 spdifm0_tx: spdifm0-tx {
1429 rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
1434 spdifm1_tx: spdifm1-tx {
1435 rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
1440 spdifm2_tx: spdifm2-tx {
1441 rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
1446 sdmmc0m0_pwren: sdmmc0m0-pwren {
1447 rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
1450 sdmmc0m0_gpio: sdmmc0m0-gpio {
1451 rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1456 sdmmc0m1_pwren: sdmmc0m1-pwren {
1457 rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
1460 sdmmc0m1_gpio: sdmmc0m1-gpio {
1461 rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1466 sdmmc0_clk: sdmmc0-clk {
1467 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none_8ma>;
1470 sdmmc0_cmd: sdmmc0-cmd {
1471 rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_8ma>;
1474 sdmmc0_dectn: sdmmc0-dectn {
1475 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
1478 sdmmc0_wrprt: sdmmc0-wrprt {
1479 rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
1482 sdmmc0_bus1: sdmmc0-bus1 {
1483 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>;
1486 sdmmc0_bus4: sdmmc0-bus4 {
1487 rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_8ma>,
1488 <1 RK_PA1 1 &pcfg_pull_up_8ma>,
1489 <1 RK_PA2 1 &pcfg_pull_up_8ma>,
1490 <1 RK_PA3 1 &pcfg_pull_up_8ma>;
1493 sdmmc0_gpio: sdmmc0-gpio {
1495 <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1496 <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1497 <1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1498 <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1499 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1500 <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1501 <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1502 <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1507 sdmmc0ext_clk: sdmmc0ext-clk {
1508 rockchip,pins = <3 RK_PA2 3 &pcfg_pull_none_4ma>;
1511 sdmmc0ext_cmd: sdmmc0ext-cmd {
1512 rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
1515 sdmmc0ext_wrprt: sdmmc0ext-wrprt {
1516 rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
1519 sdmmc0ext_dectn: sdmmc0ext-dectn {
1520 rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
1523 sdmmc0ext_bus1: sdmmc0ext-bus1 {
1524 rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
1527 sdmmc0ext_bus4: sdmmc0ext-bus4 {
1529 <3 RK_PA4 3 &pcfg_pull_up_4ma>,
1530 <3 RK_PA5 3 &pcfg_pull_up_4ma>,
1531 <3 RK_PA6 3 &pcfg_pull_up_4ma>,
1532 <3 RK_PA7 3 &pcfg_pull_up_4ma>;
1535 sdmmc0ext_gpio: sdmmc0ext-gpio {
1537 <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1538 <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1539 <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1540 <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1541 <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1542 <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1543 <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1544 <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1549 sdmmc1_clk: sdmmc1-clk {
1550 rockchip,pins = <1 RK_PB4 1 &pcfg_pull_none_8ma>;
1553 sdmmc1_cmd: sdmmc1-cmd {
1554 rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
1557 sdmmc1_pwren: sdmmc1-pwren {
1558 rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
1561 sdmmc1_wrprt: sdmmc1-wrprt {
1562 rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
1565 sdmmc1_dectn: sdmmc1-dectn {
1566 rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
1569 sdmmc1_bus1: sdmmc1-bus1 {
1570 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
1573 sdmmc1_bus4: sdmmc1-bus4 {
1574 rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
1575 <1 RK_PB7 1 &pcfg_pull_up_8ma>,
1576 <1 RK_PC0 1 &pcfg_pull_up_8ma>,
1577 <1 RK_PC1 1 &pcfg_pull_up_8ma>;
1580 sdmmc1_gpio: sdmmc1-gpio {
1582 <1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1583 <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1584 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1585 <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1586 <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1587 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1588 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1589 <1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
1590 <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
1595 emmc_clk: emmc-clk {
1596 rockchip,pins = <3 RK_PC5 2 &pcfg_pull_none_12ma>;
1599 emmc_cmd: emmc-cmd {
1600 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
1603 emmc_pwren: emmc-pwren {
1604 rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
1607 emmc_rstnout: emmc-rstnout {
1608 rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
1611 emmc_bus1: emmc-bus1 {
1612 rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
1615 emmc_bus4: emmc-bus4 {
1617 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1618 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1619 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1620 <2 RK_PD6 2 &pcfg_pull_up_12ma>;
1623 emmc_bus8: emmc-bus8 {
1625 <0 RK_PA7 2 &pcfg_pull_up_12ma>,
1626 <2 RK_PD4 2 &pcfg_pull_up_12ma>,
1627 <2 RK_PD5 2 &pcfg_pull_up_12ma>,
1628 <2 RK_PD6 2 &pcfg_pull_up_12ma>,
1629 <2 RK_PD7 2 &pcfg_pull_up_12ma>,
1630 <3 RK_PC0 2 &pcfg_pull_up_12ma>,
1631 <3 RK_PC1 2 &pcfg_pull_up_12ma>,
1632 <3 RK_PC2 2 &pcfg_pull_up_12ma>;
1637 pwm0_pin: pwm0-pin {
1638 rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
1643 pwm1_pin: pwm1-pin {
1644 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
1649 pwm2_pin: pwm2-pin {
1650 rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
1655 pwmir_pin: pwmir-pin {
1656 rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
1661 rgmiim1_pins: rgmiim1-pins {
1664 <1 RK_PB4 2 &pcfg_pull_none_8ma>,
1666 <1 RK_PB5 2 &pcfg_pull_none_4ma>,
1668 <1 RK_PC3 2 &pcfg_pull_none_4ma>,
1670 <1 RK_PD1 2 &pcfg_pull_none_8ma>,
1672 <1 RK_PC5 2 &pcfg_pull_none_4ma>,
1674 <1 RK_PC6 2 &pcfg_pull_none_4ma>,
1676 <1 RK_PC7 2 &pcfg_pull_none_4ma>,
1678 <1 RK_PB2 2 &pcfg_pull_none_4ma>,
1680 <1 RK_PB3 2 &pcfg_pull_none_4ma>,
1682 <1 RK_PB0 2 &pcfg_pull_none_8ma>,
1684 <1 RK_PB1 2 &pcfg_pull_none_8ma>,
1686 <1 RK_PB6 2 &pcfg_pull_none_4ma>,
1688 <1 RK_PB7 2 &pcfg_pull_none_4ma>,
1690 <1 RK_PC0 2 &pcfg_pull_none_8ma>,
1692 <1 RK_PC1 2 &pcfg_pull_none_8ma>,
1695 <0 RK_PB0 1 &pcfg_pull_none_8ma>,
1697 <0 RK_PB4 1 &pcfg_pull_none_8ma>,
1699 <0 RK_PD0 1 &pcfg_pull_none_4ma>,
1701 <0 RK_PC0 1 &pcfg_pull_none_8ma>,
1703 <0 RK_PC1 1 &pcfg_pull_none_8ma>,
1705 <0 RK_PC7 1 &pcfg_pull_none_8ma>,
1707 <0 RK_PC6 1 &pcfg_pull_none_8ma>;
1710 rmiim1_pins: rmiim1-pins {
1713 <1 RK_PC3 2 &pcfg_pull_none_2ma>,
1715 <1 RK_PD1 2 &pcfg_pull_none_12ma>,
1717 <1 RK_PC5 2 &pcfg_pull_none_2ma>,
1719 <1 RK_PD0 2 &pcfg_pull_none_2ma>,
1721 <1 RK_PC6 2 &pcfg_pull_none_2ma>,
1723 <1 RK_PC7 2 &pcfg_pull_none_2ma>,
1725 <1 RK_PB2 2 &pcfg_pull_none_2ma>,
1727 <1 RK_PB3 2 &pcfg_pull_none_2ma>,
1729 <1 RK_PB0 2 &pcfg_pull_none_12ma>,
1731 <1 RK_PB1 2 &pcfg_pull_none_12ma>,
1734 <0 RK_PB3 1 &pcfg_pull_none>,
1736 <0 RK_PB4 1 &pcfg_pull_none>,
1738 <0 RK_PD0 1 &pcfg_pull_none>,
1740 <0 RK_PC3 1 &pcfg_pull_none>,
1742 <0 RK_PC0 1 &pcfg_pull_none>,
1744 <0 RK_PC1 1 &pcfg_pull_none>;
1749 fephyled_speed100: fephyled-speed100 {
1750 rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
1753 fephyled_speed10: fephyled-speed10 {
1754 rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
1757 fephyled_duplex: fephyled-duplex {
1758 rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
1761 fephyled_rxm0: fephyled-rxm0 {
1762 rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
1765 fephyled_txm0: fephyled-txm0 {
1766 rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
1769 fephyled_linkm0: fephyled-linkm0 {
1770 rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
1773 fephyled_rxm1: fephyled-rxm1 {
1774 rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
1777 fephyled_txm1: fephyled-txm1 {
1778 rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
1781 fephyled_linkm1: fephyled-linkm1 {
1782 rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
1787 tsadc_int: tsadc-int {
1788 rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
1790 tsadc_gpio: tsadc-gpio {
1791 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
1796 hdmi_cec: hdmi-cec {
1797 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
1800 hdmi_hpd: hdmi-hpd {
1801 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
1806 dvp_d2d9_m0:dvp-d2d9-m0 {
1809 <3 RK_PA4 2 &pcfg_pull_none>,
1811 <3 RK_PA5 2 &pcfg_pull_none>,
1813 <3 RK_PA6 2 &pcfg_pull_none>,
1815 <3 RK_PA7 2 &pcfg_pull_none>,
1817 <3 RK_PB0 2 &pcfg_pull_none>,
1819 <3 RK_PB1 2 &pcfg_pull_none>,
1821 <3 RK_PB2 2 &pcfg_pull_none>,
1823 <3 RK_PB3 2 &pcfg_pull_none>,
1825 <3 RK_PA1 2 &pcfg_pull_none>,
1827 <3 RK_PA0 2 &pcfg_pull_none>,
1829 <3 RK_PA3 2 &pcfg_pull_none>,
1831 <3 RK_PA2 2 &pcfg_pull_none>;
1836 dvp_d2d9_m1:dvp-d2d9-m1 {
1839 <3 RK_PA4 2 &pcfg_pull_none>,
1841 <3 RK_PA5 2 &pcfg_pull_none>,
1843 <3 RK_PA6 2 &pcfg_pull_none>,
1845 <3 RK_PA7 2 &pcfg_pull_none>,
1847 <3 RK_PB0 2 &pcfg_pull_none>,
1849 <2 RK_PC0 4 &pcfg_pull_none>,
1851 <2 RK_PC1 4 &pcfg_pull_none>,
1853 <2 RK_PC2 4 &pcfg_pull_none>,
1855 <3 RK_PA1 2 &pcfg_pull_none>,
1857 <3 RK_PA0 2 &pcfg_pull_none>,
1859 <2 RK_PB7 4 &pcfg_pull_none>,
1861 <3 RK_PA2 2 &pcfg_pull_none>;