arch/arm64/boot/dts/renesas/r8a77970.dtsi

   1 /*
   2  * Device Tree Source for the r8a77970 SoC
   3  *
   4  * Copyright (C) 2016-2017 Renesas Electronics Corp.
   5  * Copyright (C) 2017 Cogent Embedded, Inc.
   6  *
   7  * This file is licensed under the terms of the GNU General Public License
   8  * version 2.  This program is licensed "as is" without any warranty of any
   9  * kind, whether express or implied.
  10  */
  11
  12 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15 #include <dt-bindings/power/r8a77970-sysc.h>
  16
  17 / {
  18         compatible = "renesas,r8a77970";
  19         #address-cells = <2>;
  20         #size-cells = <2>;
  21
  22         aliases {
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28         };
  29
  30         cpus {
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33
  34                 a53_0: cpu@0 {
  35                         device_type = "cpu";
  36                         compatible = "arm,cortex-a53", "arm,armv8";
  37                         reg = <0>;
  38                         clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
  39                         power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
  40                         next-level-cache = <&L2_CA53>;
  41                         enable-method = "psci";
  42                 };
  43
  44                 L2_CA53: cache-controller {
  45                         compatible = "cache";
  46                         power-domains = <&sysc R8A77970_PD_CA53_SCU>;
  47                         cache-unified;
  48                         cache-level = <2>;
  49                 };
  50         };
  51
  52         extal_clk: extal {
  53                 compatible = "fixed-clock";
  54                 #clock-cells = <0>;
  55                 /* This value must be overridden by the board */
  56                 clock-frequency = <0>;
  57         };
  58
  59         extalr_clk: extalr {
  60                 compatible = "fixed-clock";
  61                 #clock-cells = <0>;
  62                 /* This value must be overridden by the board */
  63                 clock-frequency = <0>;
  64         };
  65
  66         psci {
  67                 compatible = "arm,psci-1.0", "arm,psci-0.2";
  68                 method = "smc";
  69         };
  70
  71         /* External SCIF clock - to be overridden by boards that provide it */
  72         scif_clk: scif {
  73                 compatible = "fixed-clock";
  74                 #clock-cells = <0>;
  75                 clock-frequency = <0>;
  76         };
  77
  78         soc {
  79                 compatible = "simple-bus";
  80                 interrupt-parent = <&gic>;
  81
  82                 #address-cells = <2>;
  83                 #size-cells = <2>;
  84                 ranges;
  85
  86                 gic: interrupt-controller@f1010000 {
  87                         compatible = "arm,gic-400";
  88                         #interrupt-cells = <3>;
  89                         #address-cells = <0>;
  90                         interrupt-controller;
  91                         reg = <0 0xf1010000 0 0x1000>,
  92                               <0 0xf1020000 0 0x20000>,
  93                               <0 0xf1040000 0 0x20000>,
  94                               <0 0xf1060000 0 0x20000>;
  95                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) |
  96                                       IRQ_TYPE_LEVEL_HIGH)>;
  97                         clocks = <&cpg CPG_MOD 408>;
  98                         clock-names = "clk";
  99                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 100                         resets = <&cpg 408>;
 101                 };
 102
 103                 rwdt: watchdog@e6020000 {
 104                         compatible = "renesas,r8a77970-wdt",
 105                                      "renesas,rcar-gen3-wdt";
 106                         reg = <0 0xe6020000 0 0x0c>;
 107                         clocks = <&cpg CPG_MOD 402>;
 108                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 109                         resets = <&cpg 402>;
 110                         status = "disabled";
 111                 };
 112
 113                 cpg: clock-controller@e6150000 {
 114                         compatible = "renesas,r8a77970-cpg-mssr";
 115                         reg = <0 0xe6150000 0 0x1000>;
 116                         clocks = <&extal_clk>, <&extalr_clk>;
 117                         clock-names = "extal", "extalr";
 118                         #clock-cells = <2>;
 119                         #power-domain-cells = <0>;
 120                         #reset-cells = <1>;
 121                 };
 122
 123                 rst: reset-controller@e6160000 {
 124                         compatible = "renesas,r8a77970-rst";
 125                         reg = <0 0xe6160000 0 0x200>;
 126                 };
 127
 128                 sysc: system-controller@e6180000 {
 129                         compatible = "renesas,r8a77970-sysc";
 130                         reg = <0 0xe6180000 0 0x440>;
 131                         #power-domain-cells = <1>;
 132                 };
 133
 134                 ipmmu_vi0: mmu@febd0000 {
 135                         compatible = "renesas,ipmmu-r8a77970";
 136                         reg = <0 0xfebd0000 0 0x1000>;
 137                         renesas,ipmmu-main = <&ipmmu_mm 9>;
 138                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 139                         #iommu-cells = <1>;
 140                         status = "disabled";
 141                 };
 142
 143                 ipmmu_ir: mmu@ff8b0000 {
 144                         compatible = "renesas,ipmmu-r8a77970";
 145                         reg = <0 0xff8b0000 0 0x1000>;
 146                         renesas,ipmmu-main = <&ipmmu_mm 3>;
 147                         power-domains = <&sysc R8A77970_PD_A3IR>;
 148                         #iommu-cells = <1>;
 149                         status = "disabled";
 150                 };
 151
 152                 ipmmu_rt: mmu@ffc80000 {
 153                         compatible = "renesas,ipmmu-r8a77970";
 154                         reg = <0 0xffc80000 0 0x1000>;
 155                         renesas,ipmmu-main = <&ipmmu_mm 7>;
 156                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 157                         #iommu-cells = <1>;
 158                 };
 159
 160                 ipmmu_ds1: mmu@e7740000 {
 161                         compatible = "renesas,ipmmu-r8a77970";
 162                         reg = <0 0xe7740000 0 0x1000>;
 163                         renesas,ipmmu-main = <&ipmmu_mm 1>;
 164                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 165                         #iommu-cells = <1>;
 166                 };
 167
 168                 ipmmu_mm: mmu@e67b0000 {
 169                         compatible = "renesas,ipmmu-r8a77970";
 170                         reg = <0 0xe67b0000 0 0x1000>;
 171                         interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
 172                                      <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
 173                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 174                         #iommu-cells = <1>;
 175                 };
 176
 177                 pfc: pin-controller@e6060000 {
 178                         compatible = "renesas,pfc-r8a77970";
 179                         reg = <0 0xe6060000 0 0x504>;
 180                 };
 181
 182                 gpio0: gpio@e6050000 {
 183                         compatible = "renesas,gpio-r8a77970",
 184                                      "renesas,rcar-gen3-gpio";
 185                         reg = <0 0xe6050000 0 0x50>;
 186                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 187                         #gpio-cells = <2>;
 188                         gpio-controller;
 189                         gpio-ranges = <&pfc 0 0 22>;
 190                         #interrupt-cells = <2>;
 191                         interrupt-controller;
 192                         clocks = <&cpg CPG_MOD 912>;
 193                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 194                         resets = <&cpg 912>;
 195                 };
 196
 197                 gpio1: gpio@e6051000 {
 198                         compatible = "renesas,gpio-r8a77970",
 199                                      "renesas,rcar-gen3-gpio";
 200                         reg = <0 0xe6051000 0 0x50>;
 201                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 202                         #gpio-cells = <2>;
 203                         gpio-controller;
 204                         gpio-ranges = <&pfc 0 32 28>;
 205                         #interrupt-cells = <2>;
 206                         interrupt-controller;
 207                         clocks = <&cpg CPG_MOD 911>;
 208                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 209                         resets = <&cpg 911>;
 210                 };
 211
 212                 gpio2: gpio@e6052000 {
 213                         compatible = "renesas,gpio-r8a77970",
 214                                      "renesas,rcar-gen3-gpio";
 215                         reg = <0 0xe6052000 0 0x50>;
 216                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 217                         #gpio-cells = <2>;
 218                         gpio-controller;
 219                         gpio-ranges = <&pfc 0 64 17>;
 220                         #interrupt-cells = <2>;
 221                         interrupt-controller;
 222                         clocks = <&cpg CPG_MOD 910>;
 223                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 224                         resets = <&cpg 910>;
 225                 };
 226
 227                 gpio3: gpio@e6053000 {
 228                         compatible = "renesas,gpio-r8a77970",
 229                                      "renesas,rcar-gen3-gpio";
 230                         reg = <0 0xe6053000 0 0x50>;
 231                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 232                         #gpio-cells = <2>;
 233                         gpio-controller;
 234                         gpio-ranges = <&pfc 0 96 17>;
 235                         #interrupt-cells = <2>;
 236                         interrupt-controller;
 237                         clocks = <&cpg CPG_MOD 909>;
 238                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 239                         resets = <&cpg 909>;
 240                 };
 241
 242                 gpio4: gpio@e6054000 {
 243                         compatible = "renesas,gpio-r8a77970",
 244                                      "renesas,rcar-gen3-gpio";
 245                         reg = <0 0xe6054000 0 0x50>;
 246                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 247                         #gpio-cells = <2>;
 248                         gpio-controller;
 249                         gpio-ranges = <&pfc 0 128 6>;
 250                         #interrupt-cells = <2>;
 251                         interrupt-controller;
 252                         clocks = <&cpg CPG_MOD 908>;
 253                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 254                         resets = <&cpg 908>;
 255                 };
 256
 257                 gpio5: gpio@e6055000 {
 258                         compatible = "renesas,gpio-r8a77970",
 259                                      "renesas,rcar-gen3-gpio";
 260                         reg = <0 0xe6055000 0 0x50>;
 261                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 262                         #gpio-cells = <2>;
 263                         gpio-controller;
 264                         gpio-ranges = <&pfc 0 160 15>;
 265                         #interrupt-cells = <2>;
 266                         interrupt-controller;
 267                         clocks = <&cpg CPG_MOD 907>;
 268                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 269                         resets = <&cpg 907>;
 270                 };
 271
 272                 intc_ex: interrupt-controller@e61c0000 {
 273                         compatible = "renesas,intc-ex-r8a77970", "renesas,irqc";
 274                         #interrupt-cells = <2>;
 275                         interrupt-controller;
 276                         reg = <0 0xe61c0000 0 0x200>;
 277                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
 278                                       GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
 279                                       GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
 280                                       GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
 281                                       GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
 282                                       GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
 283                         clocks = <&cpg CPG_MOD 407>;
 284                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 285                         resets = <&cpg 407>;
 286                 };
 287
 288                 prr: chipid@fff00044 {
 289                         compatible = "renesas,prr";
 290                         reg = <0 0xfff00044 0 4>;
 291                 };
 292
 293                 dmac1: dma-controller@e7300000 {
 294                         compatible = "renesas,dmac-r8a77970",
 295                                      "renesas,rcar-dmac";
 296                         reg = <0 0xe7300000 0 0x10000>;
 297                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 298                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 299                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 300                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 301                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 302                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 303                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 304                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 305                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
 306                         interrupt-names = "error",
 307                                           "ch0", "ch1", "ch2", "ch3",
 308                                           "ch4", "ch5", "ch6", "ch7";
 309                         clocks = <&cpg CPG_MOD 218>;
 310                         clock-names = "fck";
 311                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 312                         resets = <&cpg 218>;
 313                         #dma-cells = <1>;
 314                         dma-channels = <8>;
 315                         iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
 316                                <&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
 317                                <&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
 318                                <&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
 319                 };
 320
 321                 dmac2: dma-controller@e7310000 {
 322                         compatible = "renesas,dmac-r8a77970",
 323                                      "renesas,rcar-dmac";
 324                         reg = <0 0xe7310000 0 0x10000>;
 325                         interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH
 326                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 327                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 328                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 329                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 330                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 331                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 332                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH
 333                                       GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
 334                         interrupt-names = "error",
 335                                           "ch0", "ch1", "ch2", "ch3",
 336                                           "ch4", "ch5", "ch6", "ch7";
 337                         clocks = <&cpg CPG_MOD 217>;
 338                         clock-names = "fck";
 339                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 340                         resets = <&cpg 217>;
 341                         #dma-cells = <1>;
 342                         dma-channels = <8>;
 343                         iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
 344                                <&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
 345                                <&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
 346                                <&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
 347                 };
 348
 349                 i2c0: i2c@e6500000 {
 350                         compatible = "renesas,i2c-r8a77970",
 351                                      "renesas,rcar-gen3-i2c";
 352                         reg = <0 0xe6500000 0 0x40>;
 353                         interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
 354                         clocks = <&cpg CPG_MOD 931>;
 355                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 356                         resets = <&cpg 931>;
 357                         dmas = <&dmac1 0x91>, <&dmac1 0x90>,
 358                                <&dmac2 0x91>, <&dmac2 0x90>;
 359                         dma-names = "tx", "rx", "tx", "rx";
 360                         i2c-scl-internal-delay-ns = <6>;
 361                         #address-cells = <1>;
 362                         #size-cells = <0>;
 363                         status = "disabled";
 364                 };
 365
 366                 i2c1: i2c@e6508000 {
 367                         compatible = "renesas,i2c-r8a77970",
 368                                      "renesas,rcar-gen3-i2c";
 369                         reg = <0 0xe6508000 0 0x40>;
 370                         interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
 371                         clocks = <&cpg CPG_MOD 930>;
 372                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 373                         resets = <&cpg 930>;
 374                         dmas = <&dmac1 0x93>, <&dmac1 0x92>,
 375                                <&dmac2 0x93>, <&dmac2 0x92>;
 376                         dma-names = "tx", "rx", "tx", "rx";
 377                         i2c-scl-internal-delay-ns = <6>;
 378                         #address-cells = <1>;
 379                         #size-cells = <0>;
 380                         status = "disabled";
 381                 };
 382
 383                 i2c2: i2c@e6510000 {
 384                         compatible = "renesas,i2c-r8a77970",
 385                                      "renesas,rcar-gen3-i2c";
 386                         reg = <0 0xe6510000 0 0x40>;
 387                         interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
 388                         clocks = <&cpg CPG_MOD 929>;
 389                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 390                         resets = <&cpg 929>;
 391                         dmas = <&dmac1 0x95>, <&dmac1 0x94>,
 392                                <&dmac2 0x95>, <&dmac2 0x94>;
 393                         dma-names = "tx", "rx", "tx", "rx";
 394                         i2c-scl-internal-delay-ns = <6>;
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         status = "disabled";
 398                 };
 399
 400                 i2c3: i2c@e66d0000 {
 401                         compatible = "renesas,i2c-r8a77970",
 402                                      "renesas,rcar-gen3-i2c";
 403                         reg = <0 0xe66d0000 0 0x40>;
 404                         interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
 405                         clocks = <&cpg CPG_MOD 928>;
 406                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 407                         resets = <&cpg 928>;
 408                         dmas = <&dmac1 0x97>, <&dmac1 0x96>,
 409                                <&dmac2 0x97>, <&dmac2 0x96>;
 410                         dma-names = "tx", "rx", "tx", "rx";
 411                         i2c-scl-internal-delay-ns = <6>;
 412                         #address-cells = <1>;
 413                         #size-cells = <0>;
 414                         status = "disabled";
 415                 };
 416
 417                 i2c4: i2c@e66d8000 {
 418                         compatible = "renesas,i2c-r8a77970",
 419                                      "renesas,rcar-gen3-i2c";
 420                         reg = <0 0xe66d8000 0 0x40>;
 421                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
 422                         clocks = <&cpg CPG_MOD 927>;
 423                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 424                         resets = <&cpg 927>;
 425                         dmas = <&dmac1 0x99>, <&dmac1 0x98>,
 426                                <&dmac2 0x99>, <&dmac2 0x98>;
 427                         dma-names = "tx", "rx", "tx", "rx";
 428                         i2c-scl-internal-delay-ns = <6>;
 429                         #address-cells = <1>;
 430                         #size-cells = <0>;
 431                         status = "disabled";
 432                 };
 433
 434                 hscif0: serial@e6540000 {
 435                         compatible = "renesas,hscif-r8a77970",
 436                                      "renesas,rcar-gen3-hscif",
 437                                      "renesas,hscif";
 438                         reg = <0 0xe6540000 0 96>;
 439                         interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
 440                         clocks = <&cpg CPG_MOD 520>,
 441                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 442                                  <&scif_clk>;
 443                         clock-names = "fck", "brg_int", "scif_clk";
 444                         dmas = <&dmac1 0x31>, <&dmac1 0x30>,
 445                                <&dmac2 0x31>, <&dmac2 0x30>;
 446                         dma-names = "tx", "rx", "tx", "rx";
 447                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 448                         resets = <&cpg 520>;
 449                         status = "disabled";
 450                 };
 451
 452                 hscif1: serial@e6550000 {
 453                         compatible = "renesas,hscif-r8a77970",
 454                                      "renesas,rcar-gen3-hscif",
 455                                      "renesas,hscif";
 456                         reg = <0 0xe6550000 0 96>;
 457                         interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
 458                         clocks = <&cpg CPG_MOD 519>,
 459                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 460                                  <&scif_clk>;
 461                         clock-names = "fck", "brg_int", "scif_clk";
 462                         dmas = <&dmac1 0x33>, <&dmac1 0x32>,
 463                                <&dmac2 0x33>, <&dmac2 0x32>;
 464                         dma-names = "tx", "rx", "tx", "rx";
 465                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 466                         resets = <&cpg 519>;
 467                         status = "disabled";
 468                 };
 469
 470                 hscif2: serial@e6560000 {
 471                         compatible = "renesas,hscif-r8a77970",
 472                                      "renesas,rcar-gen3-hscif",
 473                                      "renesas,hscif";
 474                         reg = <0 0xe6560000 0 96>;
 475                         interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
 476                         clocks = <&cpg CPG_MOD 518>,
 477                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 478                                  <&scif_clk>;
 479                         clock-names = "fck", "brg_int", "scif_clk";
 480                         dmas = <&dmac1 0x35>, <&dmac1 0x34>,
 481                                <&dmac2 0x35>, <&dmac2 0x34>;
 482                         dma-names = "tx", "rx", "tx", "rx";
 483                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 484                         resets = <&cpg 518>;
 485                         status = "disabled";
 486                 };
 487
 488                 hscif3: serial@e66a0000 {
 489                         compatible = "renesas,hscif-r8a77970",
 490                                      "renesas,rcar-gen3-hscif", "renesas,hscif";
 491                         reg = <0 0xe66a0000 0 96>;
 492                         interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
 493                         clocks = <&cpg CPG_MOD 517>,
 494                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 495                                  <&scif_clk>;
 496                         clock-names = "fck", "brg_int", "scif_clk";
 497                         dmas = <&dmac1 0x37>, <&dmac1 0x36>,
 498                                <&dmac2 0x37>, <&dmac2 0x36>;
 499                         dma-names = "tx", "rx", "tx", "rx";
 500                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 501                         resets = <&cpg 517>;
 502                         status = "disabled";
 503                 };
 504
 505                 scif0: serial@e6e60000 {
 506                         compatible = "renesas,scif-r8a77970",
 507                                      "renesas,rcar-gen3-scif",
 508                                      "renesas,scif";
 509                         reg = <0 0xe6e60000 0 64>;
 510                         interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
 511                         clocks = <&cpg CPG_MOD 207>,
 512                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 513                                  <&scif_clk>;
 514                         clock-names = "fck", "brg_int", "scif_clk";
 515                         dmas = <&dmac1 0x51>, <&dmac1 0x50>,
 516                                <&dmac2 0x51>, <&dmac2 0x50>;
 517                         dma-names = "tx", "rx", "tx", "rx";
 518                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 519                         resets = <&cpg 207>;
 520                         status = "disabled";
 521                 };
 522
 523                 scif1: serial@e6e68000 {
 524                         compatible = "renesas,scif-r8a77970",
 525                                      "renesas,rcar-gen3-scif",
 526                                      "renesas,scif";
 527                         reg = <0 0xe6e68000 0 64>;
 528                         interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
 529                         clocks = <&cpg CPG_MOD 206>,
 530                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 531                                  <&scif_clk>;
 532                         clock-names = "fck", "brg_int", "scif_clk";
 533                         dmas = <&dmac1 0x53>, <&dmac1 0x52>,
 534                                <&dmac2 0x53>, <&dmac2 0x52>;
 535                         dma-names = "tx", "rx", "tx", "rx";
 536                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 537                         resets = <&cpg 206>;
 538                         status = "disabled";
 539                 };
 540
 541                 scif3: serial@e6c50000 {
 542                         compatible = "renesas,scif-r8a77970",
 543                                      "renesas,rcar-gen3-scif",
 544                                      "renesas,scif";
 545                         reg = <0 0xe6c50000 0 64>;
 546                         interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 547                         clocks = <&cpg CPG_MOD 204>,
 548                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 549                                  <&scif_clk>;
 550                         clock-names = "fck", "brg_int", "scif_clk";
 551                         dmas = <&dmac1 0x57>, <&dmac1 0x56>,
 552                                <&dmac2 0x57>, <&dmac2 0x56>;
 553                         dma-names = "tx", "rx", "tx", "rx";
 554                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 555                         resets = <&cpg 204>;
 556                         status = "disabled";
 557                 };
 558
 559                 scif4: serial@e6c40000 {
 560                         compatible = "renesas,scif-r8a77970",
 561                                      "renesas,rcar-gen3-scif", "renesas,scif";
 562                         reg = <0 0xe6c40000 0 64>;
 563                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 564                         clocks = <&cpg CPG_MOD 203>,
 565                                  <&cpg CPG_CORE R8A77970_CLK_S2D1>,
 566                                  <&scif_clk>;
 567                         clock-names = "fck", "brg_int", "scif_clk";
 568                         dmas = <&dmac1 0x59>, <&dmac1 0x58>,
 569                                <&dmac2 0x59>, <&dmac2 0x58>;
 570                         dma-names = "tx", "rx", "tx", "rx";
 571                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 572                         resets = <&cpg 203>;
 573                         status = "disabled";
 574                 };
 575
 576                 avb: ethernet@e6800000 {
 577                         compatible = "renesas,etheravb-r8a77970",
 578                                      "renesas,etheravb-rcar-gen3";
 579                         reg = <0 0xe6800000 0 0x800>;
 580                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 581                                      <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 582                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 583                                      <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
 584                                      <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
 585                                      <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
 586                                      <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
 587                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
 588                                      <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
 589                                      <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
 590                                      <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 591                                      <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
 592                                      <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 593                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 594                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 595                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
 599                                      <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
 600                                      <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
 601                                      <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
 602                                      <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
 603                                      <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
 604                                      <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 605                         interrupt-names = "ch0", "ch1", "ch2", "ch3",
 606                                           "ch4", "ch5", "ch6", "ch7",
 607                                           "ch8", "ch9", "ch10", "ch11",
 608                                           "ch12", "ch13", "ch14", "ch15",
 609                                           "ch16", "ch17", "ch18", "ch19",
 610                                           "ch20", "ch21", "ch22", "ch23",
 611                                           "ch24";
 612                         clocks = <&cpg CPG_MOD 812>;
 613                         power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
 614                         resets = <&cpg 812>;
 615                         phy-mode = "rgmii";
 616                         iommus = <&ipmmu_rt 3>;
 617                         #address-cells = <1>;
 618                         #size-cells = <0>;
 619                 };
 620         };
 621
 622         timer {
 623                 compatible = "arm,armv8-timer";
 624                 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 625                                       <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 626                                       <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
 627                                       <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
 628         };
 629 };