1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
5 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/phy/phy-qcom-qusb2.h>
12 #include <dt-bindings/power/qcom-aoss-qmp.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
15 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
16 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #include <dt-bindings/thermal/thermal.h>
20 interrupt-parent = <&intc>;
52 compatible = "fixed-clock";
53 clock-frequency = <38400000>;
57 sleep_clk: sleep-clk {
58 compatible = "fixed-clock";
59 clock-frequency = <32764>;
64 reserved_memory: reserved-memory {
69 aop_cmd_db_mem: memory@80820000 {
70 reg = <0x0 0x80820000 0x0 0x20000>;
71 compatible = "qcom,cmd-db";
74 smem_mem: memory@80900000 {
75 reg = <0x0 0x80900000 0x0 0x200000>;
86 compatible = "arm,armv8";
88 enable-method = "psci";
89 next-level-cache = <&L2_0>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
94 next-level-cache = <&L3_0>;
103 compatible = "arm,armv8";
105 enable-method = "psci";
106 next-level-cache = <&L2_100>;
107 #cooling-cells = <2>;
108 qcom,freq-domain = <&cpufreq_hw 0>;
110 compatible = "cache";
111 next-level-cache = <&L3_0>;
117 compatible = "arm,armv8";
119 enable-method = "psci";
120 next-level-cache = <&L2_200>;
121 #cooling-cells = <2>;
122 qcom,freq-domain = <&cpufreq_hw 0>;
124 compatible = "cache";
125 next-level-cache = <&L3_0>;
131 compatible = "arm,armv8";
133 enable-method = "psci";
134 next-level-cache = <&L2_300>;
135 #cooling-cells = <2>;
136 qcom,freq-domain = <&cpufreq_hw 0>;
138 compatible = "cache";
139 next-level-cache = <&L3_0>;
145 compatible = "arm,armv8";
147 enable-method = "psci";
148 next-level-cache = <&L2_400>;
149 #cooling-cells = <2>;
150 qcom,freq-domain = <&cpufreq_hw 0>;
152 compatible = "cache";
153 next-level-cache = <&L3_0>;
159 compatible = "arm,armv8";
161 enable-method = "psci";
162 next-level-cache = <&L2_500>;
163 #cooling-cells = <2>;
164 qcom,freq-domain = <&cpufreq_hw 0>;
166 compatible = "cache";
167 next-level-cache = <&L3_0>;
173 compatible = "arm,armv8";
175 enable-method = "psci";
176 next-level-cache = <&L2_600>;
177 #cooling-cells = <2>;
178 qcom,freq-domain = <&cpufreq_hw 1>;
180 compatible = "cache";
181 next-level-cache = <&L3_0>;
187 compatible = "arm,armv8";
189 enable-method = "psci";
190 next-level-cache = <&L2_700>;
191 #cooling-cells = <2>;
192 qcom,freq-domain = <&cpufreq_hw 1>;
194 compatible = "cache";
195 next-level-cache = <&L3_0>;
201 device_type = "memory";
202 /* We expect the bootloader to fill in the size */
203 reg = <0 0x80000000 0 0>;
207 compatible = "arm,armv8-pmuv3";
208 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
213 compatible = "qcom,scm-sc7180", "qcom,scm";
218 compatible = "qcom,tcsr-mutex";
219 syscon = <&tcsr_mutex_regs 0 0x1000>;
224 compatible = "qcom,smem";
225 memory-region = <&smem_mem>;
226 hwlocks = <&tcsr_mutex 3>;
230 compatible = "qcom,smp2p";
231 qcom,smem = <94>, <432>;
233 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
235 mboxes = <&apss_shared 6>;
237 qcom,local-pid = <0>;
238 qcom,remote-pid = <5>;
240 cdsp_smp2p_out: master-kernel {
241 qcom,entry-name = "master-kernel";
242 #qcom,smem-state-cells = <1>;
245 cdsp_smp2p_in: slave-kernel {
246 qcom,entry-name = "slave-kernel";
248 interrupt-controller;
249 #interrupt-cells = <2>;
254 compatible = "qcom,smp2p";
255 qcom,smem = <443>, <429>;
257 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
259 mboxes = <&apss_shared 10>;
261 qcom,local-pid = <0>;
262 qcom,remote-pid = <2>;
264 adsp_smp2p_out: master-kernel {
265 qcom,entry-name = "master-kernel";
266 #qcom,smem-state-cells = <1>;
269 adsp_smp2p_in: slave-kernel {
270 qcom,entry-name = "slave-kernel";
272 interrupt-controller;
273 #interrupt-cells = <2>;
278 compatible = "qcom,smp2p";
279 qcom,smem = <435>, <428>;
280 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
281 mboxes = <&apss_shared 14>;
282 qcom,local-pid = <0>;
283 qcom,remote-pid = <1>;
285 modem_smp2p_out: master-kernel {
286 qcom,entry-name = "master-kernel";
287 #qcom,smem-state-cells = <1>;
290 modem_smp2p_in: slave-kernel {
291 qcom,entry-name = "slave-kernel";
292 interrupt-controller;
293 #interrupt-cells = <2>;
298 compatible = "arm,psci-1.0";
303 #address-cells = <2>;
305 ranges = <0 0 0 0 0x10 0>;
306 dma-ranges = <0 0 0 0 0x10 0>;
307 compatible = "simple-bus";
309 gcc: clock-controller@100000 {
310 compatible = "qcom,gcc-sc7180";
311 reg = <0 0x00100000 0 0x1f0000>;
312 clocks = <&rpmhcc RPMH_CXO_CLK>,
313 <&rpmhcc RPMH_CXO_CLK_A>;
314 clock-names = "bi_tcxo", "bi_tcxo_ao";
317 #power-domain-cells = <1>;
321 compatible = "qcom,qfprom";
322 reg = <0 0x00784000 0 0x8ff>;
323 #address-cells = <1>;
326 qusb2p_hstx_trim: hstx-trim-primary@25b {
332 qupv3_id_0: geniqup@8c0000 {
333 compatible = "qcom,geni-se-qup";
334 reg = <0 0x008c0000 0 0x6000>;
335 clock-names = "m-ahb", "s-ahb";
336 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
337 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
338 #address-cells = <2>;
344 compatible = "qcom,geni-i2c";
345 reg = <0 0x00880000 0 0x4000>;
347 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&qup_i2c0_default>;
350 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
351 #address-cells = <1>;
357 compatible = "qcom,geni-spi";
358 reg = <0 0x00880000 0 0x4000>;
360 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
361 pinctrl-names = "default";
362 pinctrl-0 = <&qup_spi0_default>;
363 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
364 #address-cells = <1>;
369 uart0: serial@880000 {
370 compatible = "qcom,geni-uart";
371 reg = <0 0x00880000 0 0x4000>;
373 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&qup_uart0_default>;
376 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
381 compatible = "qcom,geni-i2c";
382 reg = <0 0x00884000 0 0x4000>;
384 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
385 pinctrl-names = "default";
386 pinctrl-0 = <&qup_i2c1_default>;
387 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
388 #address-cells = <1>;
394 compatible = "qcom,geni-spi";
395 reg = <0 0x00884000 0 0x4000>;
397 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&qup_spi1_default>;
400 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
401 #address-cells = <1>;
406 uart1: serial@884000 {
407 compatible = "qcom,geni-uart";
408 reg = <0 0x00884000 0 0x4000>;
410 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
411 pinctrl-names = "default";
412 pinctrl-0 = <&qup_uart1_default>;
413 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
418 compatible = "qcom,geni-i2c";
419 reg = <0 0x00888000 0 0x4000>;
421 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
422 pinctrl-names = "default";
423 pinctrl-0 = <&qup_i2c2_default>;
424 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
425 #address-cells = <1>;
430 uart2: serial@888000 {
431 compatible = "qcom,geni-uart";
432 reg = <0 0x00888000 0 0x4000>;
434 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
435 pinctrl-names = "default";
436 pinctrl-0 = <&qup_uart2_default>;
437 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
442 compatible = "qcom,geni-i2c";
443 reg = <0 0x0088c000 0 0x4000>;
445 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
446 pinctrl-names = "default";
447 pinctrl-0 = <&qup_i2c3_default>;
448 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
449 #address-cells = <1>;
455 compatible = "qcom,geni-spi";
456 reg = <0 0x0088c000 0 0x4000>;
458 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
459 pinctrl-names = "default";
460 pinctrl-0 = <&qup_spi3_default>;
461 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
462 #address-cells = <1>;
467 uart3: serial@88c000 {
468 compatible = "qcom,geni-uart";
469 reg = <0 0x0088c000 0 0x4000>;
471 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
472 pinctrl-names = "default";
473 pinctrl-0 = <&qup_uart3_default>;
474 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
479 compatible = "qcom,geni-i2c";
480 reg = <0 0x00890000 0 0x4000>;
482 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
483 pinctrl-names = "default";
484 pinctrl-0 = <&qup_i2c4_default>;
485 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
486 #address-cells = <1>;
491 uart4: serial@890000 {
492 compatible = "qcom,geni-uart";
493 reg = <0 0x00890000 0 0x4000>;
495 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
496 pinctrl-names = "default";
497 pinctrl-0 = <&qup_uart4_default>;
498 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
503 compatible = "qcom,geni-i2c";
504 reg = <0 0x00894000 0 0x4000>;
506 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
507 pinctrl-names = "default";
508 pinctrl-0 = <&qup_i2c5_default>;
509 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
516 compatible = "qcom,geni-spi";
517 reg = <0 0x00894000 0 0x4000>;
519 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
520 pinctrl-names = "default";
521 pinctrl-0 = <&qup_spi5_default>;
522 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
523 #address-cells = <1>;
528 uart5: serial@894000 {
529 compatible = "qcom,geni-uart";
530 reg = <0 0x00894000 0 0x4000>;
532 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
533 pinctrl-names = "default";
534 pinctrl-0 = <&qup_uart5_default>;
535 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
540 qupv3_id_1: geniqup@ac0000 {
541 compatible = "qcom,geni-se-qup";
542 reg = <0 0x00ac0000 0 0x6000>;
543 clock-names = "m-ahb", "s-ahb";
544 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
545 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
546 #address-cells = <2>;
552 compatible = "qcom,geni-i2c";
553 reg = <0 0x00a80000 0 0x4000>;
555 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&qup_i2c6_default>;
558 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
559 #address-cells = <1>;
565 compatible = "qcom,geni-spi";
566 reg = <0 0x00a80000 0 0x4000>;
568 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
569 pinctrl-names = "default";
570 pinctrl-0 = <&qup_spi6_default>;
571 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
572 #address-cells = <1>;
577 uart6: serial@a80000 {
578 compatible = "qcom,geni-uart";
579 reg = <0 0x00a80000 0 0x4000>;
581 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
582 pinctrl-names = "default";
583 pinctrl-0 = <&qup_uart6_default>;
584 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
589 compatible = "qcom,geni-i2c";
590 reg = <0 0x00a84000 0 0x4000>;
592 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
593 pinctrl-names = "default";
594 pinctrl-0 = <&qup_i2c7_default>;
595 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
596 #address-cells = <1>;
601 uart7: serial@a84000 {
602 compatible = "qcom,geni-uart";
603 reg = <0 0x00a84000 0 0x4000>;
605 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
606 pinctrl-names = "default";
607 pinctrl-0 = <&qup_uart7_default>;
608 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
613 compatible = "qcom,geni-i2c";
614 reg = <0 0x00a88000 0 0x4000>;
616 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&qup_i2c8_default>;
619 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
620 #address-cells = <1>;
626 compatible = "qcom,geni-spi";
627 reg = <0 0x00a88000 0 0x4000>;
629 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
630 pinctrl-names = "default";
631 pinctrl-0 = <&qup_spi8_default>;
632 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
633 #address-cells = <1>;
638 uart8: serial@a88000 {
639 compatible = "qcom,geni-debug-uart";
640 reg = <0 0x00a88000 0 0x4000>;
642 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
643 pinctrl-names = "default";
644 pinctrl-0 = <&qup_uart8_default>;
645 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
650 compatible = "qcom,geni-i2c";
651 reg = <0 0x00a8c000 0 0x4000>;
653 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
654 pinctrl-names = "default";
655 pinctrl-0 = <&qup_i2c9_default>;
656 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
657 #address-cells = <1>;
662 uart9: serial@a8c000 {
663 compatible = "qcom,geni-uart";
664 reg = <0 0x00a8c000 0 0x4000>;
666 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
667 pinctrl-names = "default";
668 pinctrl-0 = <&qup_uart9_default>;
669 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
674 compatible = "qcom,geni-i2c";
675 reg = <0 0x00a90000 0 0x4000>;
677 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
678 pinctrl-names = "default";
679 pinctrl-0 = <&qup_i2c10_default>;
680 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
681 #address-cells = <1>;
687 compatible = "qcom,geni-spi";
688 reg = <0 0x00a90000 0 0x4000>;
690 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
691 pinctrl-names = "default";
692 pinctrl-0 = <&qup_spi10_default>;
693 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
694 #address-cells = <1>;
699 uart10: serial@a90000 {
700 compatible = "qcom,geni-uart";
701 reg = <0 0x00a90000 0 0x4000>;
703 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&qup_uart10_default>;
706 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
711 compatible = "qcom,geni-i2c";
712 reg = <0 0x00a94000 0 0x4000>;
714 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
715 pinctrl-names = "default";
716 pinctrl-0 = <&qup_i2c11_default>;
717 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
718 #address-cells = <1>;
724 compatible = "qcom,geni-spi";
725 reg = <0 0x00a94000 0 0x4000>;
727 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
728 pinctrl-names = "default";
729 pinctrl-0 = <&qup_spi11_default>;
730 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
731 #address-cells = <1>;
736 uart11: serial@a94000 {
737 compatible = "qcom,geni-uart";
738 reg = <0 0x00a94000 0 0x4000>;
740 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
741 pinctrl-names = "default";
742 pinctrl-0 = <&qup_uart11_default>;
743 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
748 tcsr_mutex_regs: syscon@1f40000 {
749 compatible = "syscon";
750 reg = <0 0x01f40000 0 0x40000>;
753 tlmm: pinctrl@3500000 {
754 compatible = "qcom,sc7180-pinctrl";
755 reg = <0 0x03500000 0 0x300000>,
756 <0 0x03900000 0 0x300000>,
757 <0 0x03d00000 0 0x300000>;
758 reg-names = "west", "north", "south";
759 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
762 interrupt-controller;
763 #interrupt-cells = <2>;
764 gpio-ranges = <&tlmm 0 0 120>;
765 wakeup-parent = <&pdc>;
770 function = "qspi_clk";
777 function = "qspi_cs";
784 function = "qspi_cs";
788 qspi_data01: qspi-data01 {
790 pins = "gpio64", "gpio65";
791 function = "qspi_data";
795 qspi_data12: qspi-data12 {
797 pins = "gpio66", "gpio67";
798 function = "qspi_data";
802 qup_i2c0_default: qup-i2c0-default {
804 pins = "gpio34", "gpio35";
809 qup_i2c1_default: qup-i2c1-default {
811 pins = "gpio0", "gpio1";
816 qup_i2c2_default: qup-i2c2-default {
818 pins = "gpio15", "gpio16";
819 function = "qup02_i2c";
823 qup_i2c3_default: qup-i2c3-default {
825 pins = "gpio38", "gpio39";
830 qup_i2c4_default: qup-i2c4-default {
832 pins = "gpio115", "gpio116";
833 function = "qup04_i2c";
837 qup_i2c5_default: qup-i2c5-default {
839 pins = "gpio25", "gpio26";
844 qup_i2c6_default: qup-i2c6-default {
846 pins = "gpio59", "gpio60";
851 qup_i2c7_default: qup-i2c7-default {
853 pins = "gpio6", "gpio7";
854 function = "qup11_i2c";
858 qup_i2c8_default: qup-i2c8-default {
860 pins = "gpio42", "gpio43";
865 qup_i2c9_default: qup-i2c9-default {
867 pins = "gpio46", "gpio47";
868 function = "qup13_i2c";
872 qup_i2c10_default: qup-i2c10-default {
874 pins = "gpio86", "gpio87";
879 qup_i2c11_default: qup-i2c11-default {
881 pins = "gpio53", "gpio54";
886 qup_spi0_default: qup-spi0-default {
888 pins = "gpio34", "gpio35",
894 qup_spi1_default: qup-spi1-default {
896 pins = "gpio0", "gpio1",
902 qup_spi3_default: qup-spi3-default {
904 pins = "gpio38", "gpio39",
910 qup_spi5_default: qup-spi5-default {
912 pins = "gpio25", "gpio26",
918 qup_spi6_default: qup-spi6-default {
920 pins = "gpio59", "gpio60",
926 qup_spi8_default: qup-spi8-default {
928 pins = "gpio42", "gpio43",
934 qup_spi10_default: qup-spi10-default {
936 pins = "gpio86", "gpio87",
942 qup_spi11_default: qup-spi11-default {
944 pins = "gpio53", "gpio54",
950 qup_uart0_default: qup-uart0-default {
952 pins = "gpio34", "gpio35",
958 qup_uart1_default: qup-uart1-default {
960 pins = "gpio0", "gpio1",
966 qup_uart2_default: qup-uart2-default {
968 pins = "gpio15", "gpio16";
969 function = "qup02_uart";
973 qup_uart3_default: qup-uart3-default {
975 pins = "gpio38", "gpio39",
981 qup_uart4_default: qup-uart4-default {
983 pins = "gpio115", "gpio116";
984 function = "qup04_uart";
988 qup_uart5_default: qup-uart5-default {
990 pins = "gpio25", "gpio26",
996 qup_uart6_default: qup-uart6-default {
998 pins = "gpio59", "gpio60",
1004 qup_uart7_default: qup-uart7-default {
1006 pins = "gpio6", "gpio7";
1007 function = "qup11_uart";
1011 qup_uart8_default: qup-uart8-default {
1013 pins = "gpio44", "gpio45";
1018 qup_uart9_default: qup-uart9-default {
1020 pins = "gpio46", "gpio47";
1021 function = "qup13_uart";
1025 qup_uart10_default: qup-uart10-default {
1027 pins = "gpio86", "gpio87",
1033 qup_uart11_default: qup-uart11-default {
1035 pins = "gpio53", "gpio54",
1043 compatible = "qcom,qspi-v1";
1044 reg = <0 0x088dc000 0 0x600>;
1045 #address-cells = <1>;
1047 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1048 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
1049 <&gcc GCC_QSPI_CORE_CLK>;
1050 clock-names = "iface", "core";
1051 status = "disabled";
1054 usb_1_hsphy: phy@88e3000 {
1055 compatible = "qcom,sc7180-qusb2-phy";
1056 reg = <0 0x088e3000 0 0x400>;
1057 status = "disabled";
1059 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1060 <&rpmhcc RPMH_CXO_CLK>;
1061 clock-names = "cfg_ahb", "ref";
1062 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
1064 nvmem-cells = <&qusb2p_hstx_trim>;
1067 usb_1_qmpphy: phy-wrapper@88e9000 {
1068 compatible = "qcom,sc7180-qmp-usb3-phy";
1069 reg = <0 0x088e9000 0 0x18c>,
1070 <0 0x088e8000 0 0x38>;
1071 reg-names = "reg-base", "dp_com";
1072 status = "disabled";
1074 #address-cells = <2>;
1078 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1079 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
1080 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
1081 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
1082 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
1084 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
1085 <&gcc GCC_USB3_PHY_PRIM_BCR>;
1086 reset-names = "phy", "common";
1088 usb_1_ssphy: phy@88e9200 {
1089 reg = <0 0x088e9200 0 0x128>,
1090 <0 0x088e9400 0 0x200>,
1091 <0 0x088e9c00 0 0x218>,
1092 <0 0x088e9600 0 0x128>,
1093 <0 0x088e9800 0 0x200>,
1094 <0 0x088e9a00 0 0x18>;
1097 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1098 clock-names = "pipe0";
1099 clock-output-names = "usb3_phy_pipe_clk_src";
1103 system-cache-controller@9200000 {
1104 compatible = "qcom,sc7180-llcc";
1105 reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>;
1106 reg-names = "llcc_base", "llcc_broadcast_base";
1107 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
1110 usb_1: usb@a6f8800 {
1111 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
1112 reg = <0 0x0a6f8800 0 0x400>;
1113 status = "disabled";
1114 #address-cells = <2>;
1119 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1120 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1121 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1122 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1123 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
1124 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
1127 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1128 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1129 assigned-clock-rates = <19200000>, <150000000>;
1131 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1132 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
1133 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
1134 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
1135 interrupt-names = "hs_phy_irq", "ss_phy_irq",
1136 "dm_hs_phy_irq", "dp_hs_phy_irq";
1138 power-domains = <&gcc USB30_PRIM_GDSC>;
1140 resets = <&gcc GCC_USB30_PRIM_BCR>;
1142 usb_1_dwc3: dwc3@a600000 {
1143 compatible = "snps,dwc3";
1144 reg = <0 0x0a600000 0 0xe000>;
1145 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
1146 iommus = <&apps_smmu 0x540 0>;
1147 snps,dis_u2_susphy_quirk;
1148 snps,dis_enblslpm_quirk;
1149 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
1150 phy-names = "usb2-phy", "usb3-phy";
1154 pdc: interrupt-controller@b220000 {
1155 compatible = "qcom,sc7180-pdc", "qcom,pdc";
1156 reg = <0 0x0b220000 0 0x30000>;
1157 qcom,pdc-ranges = <0 480 15>, <17 497 98>,
1158 <119 634 4>, <124 639 1>;
1159 #interrupt-cells = <2>;
1160 interrupt-parent = <&intc>;
1161 interrupt-controller;
1164 pdc_reset: reset-controller@b2e0000 {
1165 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
1166 reg = <0 0x0b2e0000 0 0x20000>;
1170 tsens0: thermal-sensor@c263000 {
1171 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1172 reg = <0 0x0c263000 0 0x1ff>, /* TM */
1173 <0 0x0c222000 0 0x1ff>; /* SROT */
1174 #qcom,sensors = <15>;
1175 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
1177 interrupt-names = "uplow","critical";
1178 #thermal-sensor-cells = <1>;
1181 tsens1: thermal-sensor@c265000 {
1182 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
1183 reg = <0 0x0c265000 0 0x1ff>, /* TM */
1184 <0 0x0c223000 0 0x1ff>; /* SROT */
1185 #qcom,sensors = <10>;
1186 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
1188 interrupt-names = "uplow","critical";
1189 #thermal-sensor-cells = <1>;
1192 aoss_reset: reset-controller@c2a0000 {
1193 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
1194 reg = <0 0x0c2a0000 0 0x31000>;
1198 aoss_qmp: qmp@c300000 {
1199 compatible = "qcom,sc7180-aoss-qmp";
1200 reg = <0 0x0c300000 0 0x100000>;
1201 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
1202 mboxes = <&apss_shared 0>;
1205 #power-domain-cells = <1>;
1208 spmi_bus: spmi@c440000 {
1209 compatible = "qcom,spmi-pmic-arb";
1210 reg = <0 0x0c440000 0 0x1100>,
1211 <0 0x0c600000 0 0x2000000>,
1212 <0 0x0e600000 0 0x100000>,
1213 <0 0x0e700000 0 0xa0000>,
1214 <0 0x0c40a000 0 0x26000>;
1215 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1216 interrupt-names = "periph_irq";
1217 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1220 #address-cells = <1>;
1222 interrupt-controller;
1223 #interrupt-cells = <4>;
1227 apps_smmu: iommu@15000000 {
1228 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
1229 reg = <0 0x15000000 0 0x100000>;
1231 #global-interrupts = <1>;
1232 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
1276 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
1277 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
1278 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
1279 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
1280 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
1281 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
1282 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
1283 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
1284 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
1285 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
1286 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
1287 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
1288 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
1289 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
1290 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1291 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1292 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1293 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1294 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1295 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1296 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1297 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1298 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1299 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
1300 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
1301 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
1302 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
1303 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
1304 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
1305 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
1306 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
1307 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
1308 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
1309 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
1310 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
1311 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
1312 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
1315 intc: interrupt-controller@17a00000 {
1316 compatible = "arm,gic-v3";
1317 #address-cells = <2>;
1320 #interrupt-cells = <3>;
1321 interrupt-controller;
1322 reg = <0 0x17a00000 0 0x10000>, /* GICD */
1323 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
1324 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1326 msi-controller@17a40000 {
1327 compatible = "arm,gic-v3-its";
1330 reg = <0 0x17a40000 0 0x20000>;
1331 status = "disabled";
1335 apss_shared: mailbox@17c00000 {
1336 compatible = "qcom,sc7180-apss-shared";
1337 reg = <0 0x17c00000 0 0x10000>;
1342 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
1343 reg = <0 0x17c10000 0 0x1000>;
1344 clocks = <&sleep_clk>;
1348 #address-cells = <2>;
1351 compatible = "arm,armv7-timer-mem";
1352 reg = <0 0x17c20000 0 0x1000>;
1356 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1357 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1358 reg = <0 0x17c21000 0 0x1000>,
1359 <0 0x17c22000 0 0x1000>;
1364 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1365 reg = <0 0x17c23000 0 0x1000>;
1366 status = "disabled";
1371 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1372 reg = <0 0x17c25000 0 0x1000>;
1373 status = "disabled";
1378 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1379 reg = <0 0x17c27000 0 0x1000>;
1380 status = "disabled";
1385 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1386 reg = <0 0x17c29000 0 0x1000>;
1387 status = "disabled";
1392 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1393 reg = <0 0x17c2b000 0 0x1000>;
1394 status = "disabled";
1399 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1400 reg = <0 0x17c2d000 0 0x1000>;
1401 status = "disabled";
1405 apps_rsc: rsc@18200000 {
1406 compatible = "qcom,rpmh-rsc";
1407 reg = <0 0x18200000 0 0x10000>,
1408 <0 0x18210000 0 0x10000>,
1409 <0 0x18220000 0 0x10000>;
1410 reg-names = "drv-0", "drv-1", "drv-2";
1411 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1412 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1413 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1414 qcom,tcs-offset = <0xd00>;
1416 qcom,tcs-config = <ACTIVE_TCS 2>,
1421 rpmhcc: clock-controller {
1422 compatible = "qcom,sc7180-rpmh-clk";
1423 clocks = <&xo_board>;
1428 rpmhpd: power-controller {
1429 compatible = "qcom,sc7180-rpmhpd";
1430 #power-domain-cells = <1>;
1431 operating-points-v2 = <&rpmhpd_opp_table>;
1433 rpmhpd_opp_table: opp-table {
1434 compatible = "operating-points-v2";
1436 rpmhpd_opp_ret: opp1 {
1437 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1440 rpmhpd_opp_min_svs: opp2 {
1441 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1444 rpmhpd_opp_low_svs: opp3 {
1445 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1448 rpmhpd_opp_svs: opp4 {
1449 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1452 rpmhpd_opp_svs_l1: opp5 {
1453 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1456 rpmhpd_opp_svs_l2: opp6 {
1460 rpmhpd_opp_nom: opp7 {
1461 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1464 rpmhpd_opp_nom_l1: opp8 {
1465 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1468 rpmhpd_opp_nom_l2: opp9 {
1469 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1472 rpmhpd_opp_turbo: opp10 {
1473 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1476 rpmhpd_opp_turbo_l1: opp11 {
1477 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1483 cpufreq_hw: cpufreq@18323000 {
1484 compatible = "qcom,cpufreq-hw";
1485 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
1486 reg-names = "freq-domain0", "freq-domain1";
1488 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
1489 clock-names = "xo", "alternate";
1491 #freq-domain-cells = <1>;
1497 polling-delay-passive = <250>;
1498 polling-delay = <1000>;
1500 thermal-sensors = <&tsens0 1>;
1503 cpu0_alert0: trip-point0 {
1504 temperature = <90000>;
1505 hysteresis = <2000>;
1509 cpu0_alert1: trip-point1 {
1510 temperature = <95000>;
1511 hysteresis = <2000>;
1515 cpu0_crit: cpu_crit {
1516 temperature = <110000>;
1517 hysteresis = <1000>;
1524 trip = <&cpu0_alert0>;
1525 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1526 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1527 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1528 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1529 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1530 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1533 trip = <&cpu0_alert1>;
1534 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1535 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1536 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1537 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1538 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1539 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1545 polling-delay-passive = <250>;
1546 polling-delay = <1000>;
1548 thermal-sensors = <&tsens0 2>;
1551 cpu1_alert0: trip-point0 {
1552 temperature = <90000>;
1553 hysteresis = <2000>;
1557 cpu1_alert1: trip-point1 {
1558 temperature = <95000>;
1559 hysteresis = <2000>;
1563 cpu1_crit: cpu_crit {
1564 temperature = <110000>;
1565 hysteresis = <1000>;
1572 trip = <&cpu1_alert0>;
1573 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1574 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1575 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1576 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1577 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1578 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1581 trip = <&cpu1_alert1>;
1582 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1583 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1584 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1585 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1586 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1587 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1593 polling-delay-passive = <250>;
1594 polling-delay = <1000>;
1596 thermal-sensors = <&tsens0 3>;
1599 cpu2_alert0: trip-point0 {
1600 temperature = <90000>;
1601 hysteresis = <2000>;
1605 cpu2_alert1: trip-point1 {
1606 temperature = <95000>;
1607 hysteresis = <2000>;
1611 cpu2_crit: cpu_crit {
1612 temperature = <110000>;
1613 hysteresis = <1000>;
1620 trip = <&cpu2_alert0>;
1621 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1622 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1623 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1624 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1625 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1626 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1629 trip = <&cpu2_alert1>;
1630 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1631 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1632 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1633 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1634 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1635 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1641 polling-delay-passive = <250>;
1642 polling-delay = <1000>;
1644 thermal-sensors = <&tsens0 4>;
1647 cpu3_alert0: trip-point0 {
1648 temperature = <90000>;
1649 hysteresis = <2000>;
1653 cpu3_alert1: trip-point1 {
1654 temperature = <95000>;
1655 hysteresis = <2000>;
1659 cpu3_crit: cpu_crit {
1660 temperature = <110000>;
1661 hysteresis = <1000>;
1668 trip = <&cpu3_alert0>;
1669 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1670 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1671 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1672 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1673 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1674 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1677 trip = <&cpu3_alert1>;
1678 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1679 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1680 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1681 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1682 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1683 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1689 polling-delay-passive = <250>;
1690 polling-delay = <1000>;
1692 thermal-sensors = <&tsens0 5>;
1695 cpu4_alert0: trip-point0 {
1696 temperature = <90000>;
1697 hysteresis = <2000>;
1701 cpu4_alert1: trip-point1 {
1702 temperature = <95000>;
1703 hysteresis = <2000>;
1707 cpu4_crit: cpu_crit {
1708 temperature = <110000>;
1709 hysteresis = <1000>;
1716 trip = <&cpu4_alert0>;
1717 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1718 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1719 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1720 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1721 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1722 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1725 trip = <&cpu4_alert1>;
1726 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1727 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1728 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1729 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1730 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1731 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1737 polling-delay-passive = <250>;
1738 polling-delay = <1000>;
1740 thermal-sensors = <&tsens0 6>;
1743 cpu5_alert0: trip-point0 {
1744 temperature = <90000>;
1745 hysteresis = <2000>;
1749 cpu5_alert1: trip-point1 {
1750 temperature = <95000>;
1751 hysteresis = <2000>;
1755 cpu5_crit: cpu_crit {
1756 temperature = <110000>;
1757 hysteresis = <1000>;
1764 trip = <&cpu5_alert0>;
1765 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1766 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1767 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1768 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1769 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1770 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1773 trip = <&cpu5_alert1>;
1774 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1775 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1776 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1777 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1778 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1779 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1785 polling-delay-passive = <250>;
1786 polling-delay = <1000>;
1788 thermal-sensors = <&tsens0 9>;
1791 cpu6_alert0: trip-point0 {
1792 temperature = <90000>;
1793 hysteresis = <2000>;
1797 cpu6_alert1: trip-point1 {
1798 temperature = <95000>;
1799 hysteresis = <2000>;
1803 cpu6_crit: cpu_crit {
1804 temperature = <110000>;
1805 hysteresis = <1000>;
1812 trip = <&cpu6_alert0>;
1813 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1814 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1817 trip = <&cpu6_alert1>;
1818 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1819 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1825 polling-delay-passive = <250>;
1826 polling-delay = <1000>;
1828 thermal-sensors = <&tsens0 10>;
1831 cpu7_alert0: trip-point0 {
1832 temperature = <90000>;
1833 hysteresis = <2000>;
1837 cpu7_alert1: trip-point1 {
1838 temperature = <95000>;
1839 hysteresis = <2000>;
1843 cpu7_crit: cpu_crit {
1844 temperature = <110000>;
1845 hysteresis = <1000>;
1852 trip = <&cpu7_alert0>;
1853 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1854 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1857 trip = <&cpu7_alert1>;
1858 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1859 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1865 polling-delay-passive = <250>;
1866 polling-delay = <1000>;
1868 thermal-sensors = <&tsens0 11>;
1871 cpu8_alert0: trip-point0 {
1872 temperature = <90000>;
1873 hysteresis = <2000>;
1877 cpu8_alert1: trip-point1 {
1878 temperature = <95000>;
1879 hysteresis = <2000>;
1883 cpu8_crit: cpu_crit {
1884 temperature = <110000>;
1885 hysteresis = <1000>;
1892 trip = <&cpu8_alert0>;
1893 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1894 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1897 trip = <&cpu8_alert1>;
1898 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1899 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1905 polling-delay-passive = <250>;
1906 polling-delay = <1000>;
1908 thermal-sensors = <&tsens0 12>;
1911 cpu9_alert0: trip-point0 {
1912 temperature = <90000>;
1913 hysteresis = <2000>;
1917 cpu9_alert1: trip-point1 {
1918 temperature = <95000>;
1919 hysteresis = <2000>;
1923 cpu9_crit: cpu_crit {
1924 temperature = <110000>;
1925 hysteresis = <1000>;
1932 trip = <&cpu9_alert0>;
1933 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1934 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1937 trip = <&cpu9_alert1>;
1938 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1945 polling-delay-passive = <250>;
1946 polling-delay = <1000>;
1948 thermal-sensors = <&tsens0 0>;
1951 aoss0_alert0: trip-point0 {
1952 temperature = <90000>;
1953 hysteresis = <2000>;
1960 polling-delay-passive = <250>;
1961 polling-delay = <1000>;
1963 thermal-sensors = <&tsens0 7>;
1966 cpuss0_alert0: trip-point0 {
1967 temperature = <90000>;
1968 hysteresis = <2000>;
1971 cpuss0_crit: cluster0_crit {
1972 temperature = <110000>;
1973 hysteresis = <2000>;
1980 polling-delay-passive = <250>;
1981 polling-delay = <1000>;
1983 thermal-sensors = <&tsens0 8>;
1986 cpuss1_alert0: trip-point0 {
1987 temperature = <90000>;
1988 hysteresis = <2000>;
1991 cpuss1_crit: cluster0_crit {
1992 temperature = <110000>;
1993 hysteresis = <2000>;
2000 polling-delay-passive = <250>;
2001 polling-delay = <1000>;
2003 thermal-sensors = <&tsens0 13>;
2006 gpuss0_alert0: trip-point0 {
2007 temperature = <90000>;
2008 hysteresis = <2000>;
2015 polling-delay-passive = <250>;
2016 polling-delay = <1000>;
2018 thermal-sensors = <&tsens0 14>;
2021 gpuss1_alert0: trip-point0 {
2022 temperature = <90000>;
2023 hysteresis = <2000>;
2030 polling-delay-passive = <250>;
2031 polling-delay = <1000>;
2033 thermal-sensors = <&tsens1 0>;
2036 aoss1_alert0: trip-point0 {
2037 temperature = <90000>;
2038 hysteresis = <2000>;
2045 polling-delay-passive = <250>;
2046 polling-delay = <1000>;
2048 thermal-sensors = <&tsens1 1>;
2051 cwlan_alert0: trip-point0 {
2052 temperature = <90000>;
2053 hysteresis = <2000>;
2060 polling-delay-passive = <250>;
2061 polling-delay = <1000>;
2063 thermal-sensors = <&tsens1 2>;
2066 audio_alert0: trip-point0 {
2067 temperature = <90000>;
2068 hysteresis = <2000>;
2075 polling-delay-passive = <250>;
2076 polling-delay = <1000>;
2078 thermal-sensors = <&tsens1 3>;
2081 ddr_alert0: trip-point0 {
2082 temperature = <90000>;
2083 hysteresis = <2000>;
2090 polling-delay-passive = <250>;
2091 polling-delay = <1000>;
2093 thermal-sensors = <&tsens1 4>;
2096 q6_hvx_alert0: trip-point0 {
2097 temperature = <90000>;
2098 hysteresis = <2000>;
2105 polling-delay-passive = <250>;
2106 polling-delay = <1000>;
2108 thermal-sensors = <&tsens1 5>;
2111 camera_alert0: trip-point0 {
2112 temperature = <90000>;
2113 hysteresis = <2000>;
2120 polling-delay-passive = <250>;
2121 polling-delay = <1000>;
2123 thermal-sensors = <&tsens1 6>;
2126 mdm_alert0: trip-point0 {
2127 temperature = <90000>;
2128 hysteresis = <2000>;
2135 polling-delay-passive = <250>;
2136 polling-delay = <1000>;
2138 thermal-sensors = <&tsens1 7>;
2141 mdm_dsp_alert0: trip-point0 {
2142 temperature = <90000>;
2143 hysteresis = <2000>;
2150 polling-delay-passive = <250>;
2151 polling-delay = <1000>;
2153 thermal-sensors = <&tsens1 8>;
2156 npu_alert0: trip-point0 {
2157 temperature = <90000>;
2158 hysteresis = <2000>;
2165 polling-delay-passive = <250>;
2166 polling-delay = <1000>;
2168 thermal-sensors = <&tsens1 9>;
2171 video_alert0: trip-point0 {
2172 temperature = <90000>;
2173 hysteresis = <2000>;
2181 compatible = "arm,armv8-timer";
2182 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
2183 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
2184 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
2185 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;