arch/arm64/boot/dts/qcom/msm8998.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7
   8 / {
   9         interrupt-parent = <&intc>;
  10
  11         qcom,msm-id = <292 0x0>;
  12
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         chosen { };
  17
  18         memory {
  19                 device_type = "memory";
  20                 /* We expect the bootloader to fill in the reg */
  21                 reg = <0 0 0 0>;
  22         };
  23
  24         reserved-memory {
  25                 #address-cells = <2>;
  26                 #size-cells = <2>;
  27                 ranges;
  28
  29                 memory@85800000 {
  30                         reg = <0x0 0x85800000 0x0 0x800000>;
  31                         no-map;
  32                 };
  33
  34                 smem_mem: smem-mem@86000000 {
  35                         reg = <0x0 0x86000000 0x0 0x200000>;
  36                         no-map;
  37                 };
  38
  39                 memory@86200000 {
  40                         reg = <0x0 0x86200000 0x0 0x2600000>;
  41                         no-map;
  42                 };
  43
  44                 rmtfs {
  45                         compatible = "qcom,rmtfs-mem";
  46
  47                         size = <0x0 0x200000>;
  48                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  49                         no-map;
  50
  51                         qcom,client-id = <1>;
  52                         qcom,vmid = <15>;
  53                 };
  54         };
  55
  56         clocks {
  57                 xo: xo-board {
  58                         compatible = "fixed-clock";
  59                         #clock-cells = <0>;
  60                         clock-frequency = <19200000>;
  61                         clock-output-names = "xo_board";
  62                 };
  63
  64                 sleep_clk {
  65                         compatible = "fixed-clock";
  66                         #clock-cells = <0>;
  67                         clock-frequency = <32764>;
  68                 };
  69         };
  70
  71         cpus {
  72                 #address-cells = <2>;
  73                 #size-cells = <0>;
  74
  75                 CPU0: cpu@0 {
  76                         device_type = "cpu";
  77                         compatible = "arm,armv8";
  78                         reg = <0x0 0x0>;
  79                         enable-method = "psci";
  80                         efficiency = <1024>;
  81                         next-level-cache = <&L2_0>;
  82                         L2_0: l2-cache {
  83                                 compatible = "arm,arch-cache";
  84                                 cache-level = <2>;
  85                         };
  86                         L1_I_0: l1-icache {
  87                                 compatible = "arm,arch-cache";
  88                         };
  89                         L1_D_0: l1-dcache {
  90                                 compatible = "arm,arch-cache";
  91                         };
  92                 };
  93
  94                 CPU1: cpu@1 {
  95                         device_type = "cpu";
  96                         compatible = "arm,armv8";
  97                         reg = <0x0 0x1>;
  98                         enable-method = "psci";
  99                         efficiency = <1024>;
 100                         next-level-cache = <&L2_0>;
 101                         L1_I_1: l1-icache {
 102                                 compatible = "arm,arch-cache";
 103                         };
 104                         L1_D_1: l1-dcache {
 105                                 compatible = "arm,arch-cache";
 106                         };
 107                 };
 108
 109                 CPU2: cpu@2 {
 110                         device_type = "cpu";
 111                         compatible = "arm,armv8";
 112                         reg = <0x0 0x2>;
 113                         enable-method = "psci";
 114                         efficiency = <1024>;
 115                         next-level-cache = <&L2_0>;
 116                         L1_I_2: l1-icache {
 117                                 compatible = "arm,arch-cache";
 118                         };
 119                         L1_D_2: l1-dcache {
 120                                 compatible = "arm,arch-cache";
 121                         };
 122                 };
 123
 124                 CPU3: cpu@3 {
 125                         device_type = "cpu";
 126                         compatible = "arm,armv8";
 127                         reg = <0x0 0x3>;
 128                         enable-method = "psci";
 129                         efficiency = <1024>;
 130                         next-level-cache = <&L2_0>;
 131                         L1_I_3: l1-icache {
 132                                 compatible = "arm,arch-cache";
 133                         };
 134                         L1_D_3: l1-dcache {
 135                                 compatible = "arm,arch-cache";
 136                         };
 137                 };
 138
 139                 CPU4: cpu@100 {
 140                         device_type = "cpu";
 141                         compatible = "arm,armv8";
 142                         reg = <0x0 0x100>;
 143                         enable-method = "psci";
 144                         efficiency = <1536>;
 145                         next-level-cache = <&L2_1>;
 146                         L2_1: l2-cache {
 147                                 compatible = "arm,arch-cache";
 148                                 cache-level = <2>;
 149                         };
 150                         L1_I_100: l1-icache {
 151                                 compatible = "arm,arch-cache";
 152                         };
 153                         L1_D_100: l1-dcache {
 154                                 compatible = "arm,arch-cache";
 155                         };
 156                 };
 157
 158                 CPU5: cpu@101 {
 159                         device_type = "cpu";
 160                         compatible = "arm,armv8";
 161                         reg = <0x0 0x101>;
 162                         enable-method = "psci";
 163                         efficiency = <1536>;
 164                         next-level-cache = <&L2_1>;
 165                         L1_I_101: l1-icache {
 166                                 compatible = "arm,arch-cache";
 167                         };
 168                         L1_D_101: l1-dcache {
 169                                 compatible = "arm,arch-cache";
 170                         };
 171                 };
 172
 173                 CPU6: cpu@102 {
 174                         device_type = "cpu";
 175                         compatible = "arm,armv8";
 176                         reg = <0x0 0x102>;
 177                         enable-method = "psci";
 178                         efficiency = <1536>;
 179                         next-level-cache = <&L2_1>;
 180                         L1_I_102: l1-icache {
 181                                 compatible = "arm,arch-cache";
 182                         };
 183                         L1_D_102: l1-dcache {
 184                                 compatible = "arm,arch-cache";
 185                         };
 186                 };
 187
 188                 CPU7: cpu@103 {
 189                         device_type = "cpu";
 190                         compatible = "arm,armv8";
 191                         reg = <0x0 0x103>;
 192                         enable-method = "psci";
 193                         efficiency = <1536>;
 194                         next-level-cache = <&L2_1>;
 195                         L1_I_103: l1-icache {
 196                                 compatible = "arm,arch-cache";
 197                         };
 198                         L1_D_103: l1-dcache {
 199                                 compatible = "arm,arch-cache";
 200                         };
 201                 };
 202
 203                 cpu-map {
 204                         cluster0 {
 205                                 core0 {
 206                                         cpu = <&CPU0>;
 207                                 };
 208
 209                                 core1 {
 210                                         cpu = <&CPU1>;
 211                                 };
 212
 213                                 core2 {
 214                                         cpu = <&CPU2>;
 215                                 };
 216
 217                                 core3 {
 218                                         cpu = <&CPU3>;
 219                                 };
 220                         };
 221
 222                         cluster1 {
 223                                 core0 {
 224                                         cpu = <&CPU4>;
 225                                 };
 226
 227                                 core1 {
 228                                         cpu = <&CPU5>;
 229                                 };
 230
 231                                 core2 {
 232                                         cpu = <&CPU6>;
 233                                 };
 234
 235                                 core3 {
 236                                         cpu = <&CPU7>;
 237                                 };
 238                         };
 239                 };
 240         };
 241
 242         firmware {
 243                 scm {
 244                         compatible = "qcom,scm-msm8998", "qcom,scm";
 245                 };
 246         };
 247
 248         tcsr_mutex: hwlock {
 249                 compatible = "qcom,tcsr-mutex";
 250                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 251                 #hwlock-cells = <1>;
 252         };
 253
 254         psci {
 255                 compatible = "arm,psci-1.0";
 256                 method = "smc";
 257         };
 258
 259         rpm-glink {
 260                 compatible = "qcom,glink-rpm";
 261
 262                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 263                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 264                 mboxes = <&apcs_glb 0>;
 265
 266                 rpm_requests: rpm-requests {
 267                         compatible = "qcom,rpm-msm8998";
 268                         qcom,glink-channels = "rpm_requests";
 269                 };
 270         };
 271
 272         smem {
 273                 compatible = "qcom,smem";
 274                 memory-region = <&smem_mem>;
 275                 hwlocks = <&tcsr_mutex 3>;
 276         };
 277
 278         smp2p-lpass {
 279                 compatible = "qcom,smp2p";
 280                 qcom,smem = <443>, <429>;
 281
 282                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 283
 284                 mboxes = <&apcs_glb 10>;
 285
 286                 qcom,local-pid = <0>;
 287                 qcom,remote-pid = <2>;
 288
 289                 adsp_smp2p_out: master-kernel {
 290                         qcom,entry-name = "master-kernel";
 291                         #qcom,smem-state-cells = <1>;
 292                 };
 293
 294                 adsp_smp2p_in: slave-kernel {
 295                         qcom,entry-name = "slave-kernel";
 296
 297                         interrupt-controller;
 298                         #interrupt-cells = <2>;
 299                 };
 300         };
 301
 302         smp2p-mpss {
 303                 compatible = "qcom,smp2p";
 304                 qcom,smem = <435>, <428>;
 305                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 306                 mboxes = <&apcs_glb 14>;
 307                 qcom,local-pid = <0>;
 308                 qcom,remote-pid = <1>;
 309
 310                 modem_smp2p_out: master-kernel {
 311                         qcom,entry-name = "master-kernel";
 312                         #qcom,smem-state-cells = <1>;
 313                 };
 314
 315                 modem_smp2p_in: slave-kernel {
 316                         qcom,entry-name = "slave-kernel";
 317                         interrupt-controller;
 318                         #interrupt-cells = <2>;
 319                 };
 320         };
 321
 322         smp2p-slpi {
 323                 compatible = "qcom,smp2p";
 324                 qcom,smem = <481>, <430>;
 325                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 326                 mboxes = <&apcs_glb 26>;
 327                 qcom,local-pid = <0>;
 328                 qcom,remote-pid = <3>;
 329
 330                 slpi_smp2p_out: master-kernel {
 331                         qcom,entry-name = "master-kernel";
 332                         #qcom,smem-state-cells = <1>;
 333                 };
 334
 335                 slpi_smp2p_in: slave-kernel {
 336                         qcom,entry-name = "slave-kernel";
 337                         interrupt-controller;
 338                         #interrupt-cells = <2>;
 339                 };
 340         };
 341
 342         thermal-zones {
 343                 cpu-thermal0 {
 344                         polling-delay-passive = <250>;
 345                         polling-delay = <1000>;
 346
 347                         thermal-sensors = <&tsens0 6>;
 348
 349                         trips {
 350                                 cpu_alert0: trip0 {
 351                                         temperature = <75000>;
 352                                         hysteresis = <2000>;
 353                                         type = "passive";
 354                                 };
 355
 356                                 cpu_crit0: trip1 {
 357                                         temperature = <110000>;
 358                                         hysteresis = <2000>;
 359                                         type = "critical";
 360                                 };
 361                         };
 362                 };
 363
 364                 cpu-thermal1 {
 365                         polling-delay-passive = <250>;
 366                         polling-delay = <1000>;
 367
 368                         thermal-sensors = <&tsens0 7>;
 369
 370                         trips {
 371                                 cpu_alert1: trip0 {
 372                                         temperature = <75000>;
 373                                         hysteresis = <2000>;
 374                                         type = "passive";
 375                                 };
 376
 377                                 cpu_crit1: trip1 {
 378                                         temperature = <110000>;
 379                                         hysteresis = <2000>;
 380                                         type = "critical";
 381                                 };
 382                         };
 383                 };
 384
 385                 cpu-thermal2 {
 386                         polling-delay-passive = <250>;
 387                         polling-delay = <1000>;
 388
 389                         thermal-sensors = <&tsens0 8>;
 390
 391                         trips {
 392                                 cpu_alert2: trip0 {
 393                                         temperature = <75000>;
 394                                         hysteresis = <2000>;
 395                                         type = "passive";
 396                                 };
 397
 398                                 cpu_crit2: trip1 {
 399                                         temperature = <110000>;
 400                                         hysteresis = <2000>;
 401                                         type = "critical";
 402                                 };
 403                         };
 404                 };
 405
 406                 cpu-thermal3 {
 407                         polling-delay-passive = <250>;
 408                         polling-delay = <1000>;
 409
 410                         thermal-sensors = <&tsens0 9>;
 411
 412                         trips {
 413                                 cpu_alert3: trip0 {
 414                                         temperature = <75000>;
 415                                         hysteresis = <2000>;
 416                                         type = "passive";
 417                                 };
 418
 419                                 cpu_crit3: trip1 {
 420                                         temperature = <110000>;
 421                                         hysteresis = <2000>;
 422                                         type = "critical";
 423                                 };
 424                         };
 425                 };
 426
 427                 cpu-thermal4 {
 428                         polling-delay-passive = <250>;
 429                         polling-delay = <1000>;
 430
 431                         thermal-sensors = <&tsens0 10>;
 432
 433                         trips {
 434                                 cpu_alert4: trip0 {
 435                                         temperature = <75000>;
 436                                         hysteresis = <2000>;
 437                                         type = "passive";
 438                                 };
 439
 440                                 cpu_crit4: trip1 {
 441                                         temperature = <110000>;
 442                                         hysteresis = <2000>;
 443                                         type = "critical";
 444                                 };
 445                         };
 446                 };
 447
 448                 cpu-thermal5 {
 449                         polling-delay-passive = <250>;
 450                         polling-delay = <1000>;
 451
 452                         thermal-sensors = <&tsens0 11>;
 453
 454                         trips {
 455                                 cpu_alert5: trip0 {
 456                                         temperature = <75000>;
 457                                         hysteresis = <2000>;
 458                                         type = "passive";
 459                                 };
 460
 461                                 cpu_crit5: trip1 {
 462                                         temperature = <110000>;
 463                                         hysteresis = <2000>;
 464                                         type = "critical";
 465                                 };
 466                         };
 467                 };
 468
 469                 cpu-thermal6 {
 470                         polling-delay-passive = <250>;
 471                         polling-delay = <1000>;
 472
 473                         thermal-sensors = <&tsens1 0>;
 474
 475                         trips {
 476                                 cpu_alert6: trip0 {
 477                                         temperature = <75000>;
 478                                         hysteresis = <2000>;
 479                                         type = "passive";
 480                                 };
 481
 482                                 cpu_crit6: trip1 {
 483                                         temperature = <110000>;
 484                                         hysteresis = <2000>;
 485                                         type = "critical";
 486                                 };
 487                         };
 488                 };
 489
 490                 cpu-thermal7 {
 491                         polling-delay-passive = <250>;
 492                         polling-delay = <1000>;
 493
 494                         thermal-sensors = <&tsens1 1>;
 495
 496                         trips {
 497                                 cpu_alert7: trip0 {
 498                                         temperature = <75000>;
 499                                         hysteresis = <2000>;
 500                                         type = "passive";
 501                                 };
 502
 503                                 cpu_crit7: trip1 {
 504                                         temperature = <110000>;
 505                                         hysteresis = <2000>;
 506                                         type = "critical";
 507                                 };
 508                         };
 509                 };
 510
 511                 gpu-thermal {
 512                         polling-delay-passive = <250>;
 513                         polling-delay = <1000>;
 514
 515                         thermal-sensors = <&tsens1 3>;
 516                 };
 517         };
 518
 519         timer {
 520                 compatible = "arm,armv8-timer";
 521                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 522                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 523                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 524                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 525         };
 526
 527         soc: soc {
 528                 #address-cells = <1>;
 529                 #size-cells = <1>;
 530                 ranges = <0 0 0 0xffffffff>;
 531                 compatible = "simple-bus";
 532
 533                 rpm_msg_ram: memory@68000 {
 534                         compatible = "qcom,rpm-msg-ram";
 535                         reg = <0x778000 0x7000>;
 536                 };
 537
 538                 qfprom: qfprom@780000 {
 539                         compatible = "qcom,qfprom";
 540                         reg = <0x780000 0x621c>;
 541                         #address-cells = <1>;
 542                         #size-cells = <1>;
 543                 };
 544
 545                 gcc: clock-controller@100000 {
 546                         compatible = "qcom,gcc-msm8998";
 547                         #clock-cells = <1>;
 548                         #reset-cells = <1>;
 549                         #power-domain-cells = <1>;
 550                         reg = <0x100000 0xb0000>;
 551                 };
 552
 553                 tlmm: pinctrl@3400000 {
 554                         compatible = "qcom,msm8998-pinctrl";
 555                         reg = <0x3400000 0xc00000>;
 556                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 557                         gpio-controller;
 558                         #gpio-cells = <0x2>;
 559                         interrupt-controller;
 560                         #interrupt-cells = <0x2>;
 561                 };
 562
 563                 spmi_bus: spmi@800f000 {
 564                         compatible = "qcom,spmi-pmic-arb";
 565                         reg =   <0x800f000 0x1000>,
 566                                 <0x8400000 0x1000000>,
 567                                 <0x9400000 0x1000000>,
 568                                 <0xa400000 0x220000>,
 569                                 <0x800a000 0x3000>;
 570                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 571                         interrupt-names = "periph_irq";
 572                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 573                         qcom,ee = <0>;
 574                         qcom,channel = <0>;
 575                         #address-cells = <2>;
 576                         #size-cells = <0>;
 577                         interrupt-controller;
 578                         #interrupt-cells = <4>;
 579                         cell-index = <0>;
 580                 };
 581
 582                 tsens0: thermal@10aa000 {
 583                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 584                         reg = <0x10aa000 0x2000>;
 585
 586                         #qcom,sensors = <12>;
 587                         #thermal-sensor-cells = <1>;
 588                 };
 589
 590                 tsens1: thermal@10ad000 {
 591                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 592                         reg = <0x10ad000 0x2000>;
 593
 594                         #qcom,sensors = <8>;
 595                         #thermal-sensor-cells = <1>;
 596                 };
 597
 598                 tcsr_mutex_regs: syscon@1f40000 {
 599                         compatible = "syscon";
 600                         reg = <0x1f40000 0x20000>;
 601                 };
 602
 603                 apcs_glb: mailbox@9820000 {
 604                         compatible = "qcom,msm8998-apcs-hmss-global";
 605                         reg = <0x17911000 0x1000>;
 606
 607                         #mbox-cells = <1>;
 608                 };
 609
 610                 sdhc2: sdhci@c0a4900 {
 611                         compatible = "qcom,sdhci-msm-v4";
 612                         reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
 613                         reg-names = "hc_mem", "core_mem";
 614
 615                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 616                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 617                         interrupt-names = "hc_irq", "pwr_irq";
 618
 619                         clock-names = "iface", "core", "xo";
 620                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 621                                  <&gcc GCC_SDCC2_APPS_CLK>,
 622                                  <&xo>;
 623                         bus-width = <4>;
 624                         status = "disabled";
 625                 };
 626
 627                 blsp2_uart1: serial@c1b0000 {
 628                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 629                         reg = <0xc1b0000 0x1000>;
 630                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 631                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 632                                  <&gcc GCC_BLSP2_AHB_CLK>;
 633                         clock-names = "core", "iface";
 634                         status = "disabled";
 635                 };
 636
 637                 timer@17920000 {
 638                         #address-cells = <1>;
 639                         #size-cells = <1>;
 640                         ranges;
 641                         compatible = "arm,armv7-timer-mem";
 642                         reg = <0x17920000 0x1000>;
 643
 644                         frame@17921000 {
 645                                 frame-number = <0>;
 646                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 647                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 648                                 reg = <0x17921000 0x1000>,
 649                                       <0x17922000 0x1000>;
 650                         };
 651
 652                         frame@17923000 {
 653                                 frame-number = <1>;
 654                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 655                                 reg = <0x17923000 0x1000>;
 656                                 status = "disabled";
 657                         };
 658
 659                         frame@17924000 {
 660                                 frame-number = <2>;
 661                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 662                                 reg = <0x17924000 0x1000>;
 663                                 status = "disabled";
 664                         };
 665
 666                         frame@17925000 {
 667                                 frame-number = <3>;
 668                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 669                                 reg = <0x17925000 0x1000>;
 670                                 status = "disabled";
 671                         };
 672
 673                         frame@17926000 {
 674                                 frame-number = <4>;
 675                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 676                                 reg = <0x17926000 0x1000>;
 677                                 status = "disabled";
 678                         };
 679
 680                         frame@17927000 {
 681                                 frame-number = <5>;
 682                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 683                                 reg = <0x17927000 0x1000>;
 684                                 status = "disabled";
 685                         };
 686
 687                         frame@17928000 {
 688                                 frame-number = <6>;
 689                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 690                                 reg = <0x17928000 0x1000>;
 691                                 status = "disabled";
 692                         };
 693                 };
 694
 695                 intc: interrupt-controller@17a00000 {
 696                         compatible = "arm,gic-v3";
 697                         reg = <0x17a00000 0x10000>,       /* GICD */
 698                               <0x17b00000 0x100000>;      /* GICR * 8 */
 699                         #interrupt-cells = <3>;
 700                         #address-cells = <1>;
 701                         #size-cells = <1>;
 702                         ranges;
 703                         interrupt-controller;
 704                         #redistributor-regions = <1>;
 705                         redistributor-stride = <0x0 0x20000>;
 706                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 707                 };
 708         };
 709 };
 710
 711 #include "msm8998-pins.dtsi"