1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/gpio/gpio.h>
9 interrupt-parent = <&intc>;
11 qcom,msm-id = <292 0x0>;
19 device_type = "memory";
20 /* We expect the bootloader to fill in the reg */
30 reg = <0x0 0x85800000 0x0 0x800000>;
34 smem_mem: smem-mem@86000000 {
35 reg = <0x0 0x86000000 0x0 0x200000>;
40 reg = <0x0 0x86200000 0x0 0x2600000>;
45 compatible = "qcom,rmtfs-mem";
47 size = <0x0 0x200000>;
48 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
58 compatible = "fixed-clock";
60 clock-frequency = <19200000>;
61 clock-output-names = "xo_board";
65 compatible = "fixed-clock";
67 clock-frequency = <32764>;
77 compatible = "arm,armv8";
79 enable-method = "psci";
81 next-level-cache = <&L2_0>;
83 compatible = "arm,arch-cache";
87 compatible = "arm,arch-cache";
90 compatible = "arm,arch-cache";
96 compatible = "arm,armv8";
98 enable-method = "psci";
100 next-level-cache = <&L2_0>;
102 compatible = "arm,arch-cache";
105 compatible = "arm,arch-cache";
111 compatible = "arm,armv8";
113 enable-method = "psci";
115 next-level-cache = <&L2_0>;
117 compatible = "arm,arch-cache";
120 compatible = "arm,arch-cache";
126 compatible = "arm,armv8";
128 enable-method = "psci";
130 next-level-cache = <&L2_0>;
132 compatible = "arm,arch-cache";
135 compatible = "arm,arch-cache";
141 compatible = "arm,armv8";
143 enable-method = "psci";
145 next-level-cache = <&L2_1>;
147 compatible = "arm,arch-cache";
150 L1_I_100: l1-icache {
151 compatible = "arm,arch-cache";
153 L1_D_100: l1-dcache {
154 compatible = "arm,arch-cache";
160 compatible = "arm,armv8";
162 enable-method = "psci";
164 next-level-cache = <&L2_1>;
165 L1_I_101: l1-icache {
166 compatible = "arm,arch-cache";
168 L1_D_101: l1-dcache {
169 compatible = "arm,arch-cache";
175 compatible = "arm,armv8";
177 enable-method = "psci";
179 next-level-cache = <&L2_1>;
180 L1_I_102: l1-icache {
181 compatible = "arm,arch-cache";
183 L1_D_102: l1-dcache {
184 compatible = "arm,arch-cache";
190 compatible = "arm,armv8";
192 enable-method = "psci";
194 next-level-cache = <&L2_1>;
195 L1_I_103: l1-icache {
196 compatible = "arm,arch-cache";
198 L1_D_103: l1-dcache {
199 compatible = "arm,arch-cache";
244 compatible = "qcom,scm-msm8998", "qcom,scm";
249 compatible = "qcom,tcsr-mutex";
250 syscon = <&tcsr_mutex_regs 0 0x1000>;
255 compatible = "arm,psci-1.0";
260 compatible = "qcom,glink-rpm";
262 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
263 qcom,rpm-msg-ram = <&rpm_msg_ram>;
264 mboxes = <&apcs_glb 0>;
266 rpm_requests: rpm-requests {
267 compatible = "qcom,rpm-msm8998";
268 qcom,glink-channels = "rpm_requests";
273 compatible = "qcom,smem";
274 memory-region = <&smem_mem>;
275 hwlocks = <&tcsr_mutex 3>;
279 compatible = "qcom,smp2p";
280 qcom,smem = <443>, <429>;
282 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
284 mboxes = <&apcs_glb 10>;
286 qcom,local-pid = <0>;
287 qcom,remote-pid = <2>;
289 adsp_smp2p_out: master-kernel {
290 qcom,entry-name = "master-kernel";
291 #qcom,smem-state-cells = <1>;
294 adsp_smp2p_in: slave-kernel {
295 qcom,entry-name = "slave-kernel";
297 interrupt-controller;
298 #interrupt-cells = <2>;
303 compatible = "qcom,smp2p";
304 qcom,smem = <435>, <428>;
305 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
306 mboxes = <&apcs_glb 14>;
307 qcom,local-pid = <0>;
308 qcom,remote-pid = <1>;
310 modem_smp2p_out: master-kernel {
311 qcom,entry-name = "master-kernel";
312 #qcom,smem-state-cells = <1>;
315 modem_smp2p_in: slave-kernel {
316 qcom,entry-name = "slave-kernel";
317 interrupt-controller;
318 #interrupt-cells = <2>;
323 compatible = "qcom,smp2p";
324 qcom,smem = <481>, <430>;
325 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
326 mboxes = <&apcs_glb 26>;
327 qcom,local-pid = <0>;
328 qcom,remote-pid = <3>;
330 slpi_smp2p_out: master-kernel {
331 qcom,entry-name = "master-kernel";
332 #qcom,smem-state-cells = <1>;
335 slpi_smp2p_in: slave-kernel {
336 qcom,entry-name = "slave-kernel";
337 interrupt-controller;
338 #interrupt-cells = <2>;
344 polling-delay-passive = <250>;
345 polling-delay = <1000>;
347 thermal-sensors = <&tsens0 6>;
351 temperature = <75000>;
357 temperature = <110000>;
365 polling-delay-passive = <250>;
366 polling-delay = <1000>;
368 thermal-sensors = <&tsens0 7>;
372 temperature = <75000>;
378 temperature = <110000>;
386 polling-delay-passive = <250>;
387 polling-delay = <1000>;
389 thermal-sensors = <&tsens0 8>;
393 temperature = <75000>;
399 temperature = <110000>;
407 polling-delay-passive = <250>;
408 polling-delay = <1000>;
410 thermal-sensors = <&tsens0 9>;
414 temperature = <75000>;
420 temperature = <110000>;
428 polling-delay-passive = <250>;
429 polling-delay = <1000>;
431 thermal-sensors = <&tsens0 10>;
435 temperature = <75000>;
441 temperature = <110000>;
449 polling-delay-passive = <250>;
450 polling-delay = <1000>;
452 thermal-sensors = <&tsens0 11>;
456 temperature = <75000>;
462 temperature = <110000>;
470 polling-delay-passive = <250>;
471 polling-delay = <1000>;
473 thermal-sensors = <&tsens1 0>;
477 temperature = <75000>;
483 temperature = <110000>;
491 polling-delay-passive = <250>;
492 polling-delay = <1000>;
494 thermal-sensors = <&tsens1 1>;
498 temperature = <75000>;
504 temperature = <110000>;
512 polling-delay-passive = <250>;
513 polling-delay = <1000>;
515 thermal-sensors = <&tsens1 3>;
520 compatible = "arm,armv8-timer";
521 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
522 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
523 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
524 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
528 #address-cells = <1>;
530 ranges = <0 0 0 0xffffffff>;
531 compatible = "simple-bus";
533 rpm_msg_ram: memory@68000 {
534 compatible = "qcom,rpm-msg-ram";
535 reg = <0x778000 0x7000>;
538 qfprom: qfprom@780000 {
539 compatible = "qcom,qfprom";
540 reg = <0x780000 0x621c>;
541 #address-cells = <1>;
544 qusb2_hstx_trim: hstx-trim@423a {
550 gcc: clock-controller@100000 {
551 compatible = "qcom,gcc-msm8998";
554 #power-domain-cells = <1>;
555 reg = <0x100000 0xb0000>;
558 tlmm: pinctrl@3400000 {
559 compatible = "qcom,msm8998-pinctrl";
560 reg = <0x3400000 0xc00000>;
561 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
564 interrupt-controller;
565 #interrupt-cells = <0x2>;
568 spmi_bus: spmi@800f000 {
569 compatible = "qcom,spmi-pmic-arb";
570 reg = <0x800f000 0x1000>,
571 <0x8400000 0x1000000>,
572 <0x9400000 0x1000000>,
573 <0xa400000 0x220000>,
575 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
576 interrupt-names = "periph_irq";
577 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
580 #address-cells = <2>;
582 interrupt-controller;
583 #interrupt-cells = <4>;
587 tsens0: thermal@10aa000 {
588 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
589 reg = <0x10aa000 0x2000>;
591 #qcom,sensors = <12>;
592 #thermal-sensor-cells = <1>;
595 tsens1: thermal@10ad000 {
596 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
597 reg = <0x10ad000 0x2000>;
600 #thermal-sensor-cells = <1>;
603 tcsr_mutex_regs: syscon@1f40000 {
604 compatible = "syscon";
605 reg = <0x1f40000 0x20000>;
608 apcs_glb: mailbox@9820000 {
609 compatible = "qcom,msm8998-apcs-hmss-global";
610 reg = <0x17911000 0x1000>;
616 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
617 reg = <0x0a8f8800 0x400>;
619 #address-cells = <1>;
623 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
624 <&gcc GCC_USB30_MASTER_CLK>,
625 <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
626 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
627 <&gcc GCC_USB30_SLEEP_CLK>;
628 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
631 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
632 <&gcc GCC_USB30_MASTER_CLK>;
633 assigned-clock-rates = <19200000>, <120000000>;
635 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
636 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
637 interrupt-names = "hs_phy_irq", "ss_phy_irq";
639 power-domains = <&gcc USB_30_GDSC>;
641 resets = <&gcc GCC_USB_30_BCR>;
643 usb3_dwc3: dwc3@a800000 {
644 compatible = "snps,dwc3";
645 reg = <0x0a800000 0xcd00>;
646 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
647 snps,dis_u2_susphy_quirk;
648 snps,dis_enblslpm_quirk;
649 phys = <&qusb2phy>, <&usb1_ssphy>;
650 phy-names = "usb2-phy", "usb3-phy";
651 snps,has-lpm-erratum;
652 snps,hird-threshold = /bits/ 8 <0x10>;
656 usb3phy: phy@c010000 {
657 compatible = "qcom,msm8998-qmp-usb3-phy";
658 reg = <0x0c010000 0x18c>;
661 #address-cells = <1>;
665 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
666 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
667 <&gcc GCC_USB3_CLKREF_CLK>;
668 clock-names = "aux", "cfg_ahb", "ref";
670 resets = <&gcc GCC_USB3_PHY_BCR>,
671 <&gcc GCC_USB3PHY_PHY_BCR>;
672 reset-names = "phy", "common";
674 usb1_ssphy: lane@c010200 {
675 reg = <0xc010200 0x128>,
681 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
682 clock-names = "pipe0";
683 clock-output-names = "usb3_phy_pipe_clk_src";
687 qusb2phy: phy@c012000 {
688 compatible = "qcom,msm8998-qusb2-phy";
689 reg = <0x0c012000 0x2a8>;
693 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
694 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
695 clock-names = "cfg_ahb", "ref";
697 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
699 nvmem-cells = <&qusb2_hstx_trim>;
702 sdhc2: sdhci@c0a4900 {
703 compatible = "qcom,sdhci-msm-v4";
704 reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
705 reg-names = "hc_mem", "core_mem";
707 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
708 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
709 interrupt-names = "hc_irq", "pwr_irq";
711 clock-names = "iface", "core", "xo";
712 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
713 <&gcc GCC_SDCC2_APPS_CLK>,
719 blsp1_i2c1: i2c@c175000 {
720 compatible = "qcom,i2c-qup-v2.2.1";
721 reg = <0x0c175000 0x600>;
722 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
725 <&gcc GCC_BLSP1_AHB_CLK>;
726 clock-names = "core", "iface";
727 clock-frequency = <400000>;
730 #address-cells = <1>;
734 blsp1_i2c2: i2c@c176000 {
735 compatible = "qcom,i2c-qup-v2.2.1";
736 reg = <0x0c176000 0x600>;
737 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
739 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
740 <&gcc GCC_BLSP1_AHB_CLK>;
741 clock-names = "core", "iface";
742 clock-frequency = <400000>;
745 #address-cells = <1>;
749 blsp1_i2c3: i2c@c177000 {
750 compatible = "qcom,i2c-qup-v2.2.1";
751 reg = <0x0c177000 0x600>;
752 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
755 <&gcc GCC_BLSP1_AHB_CLK>;
756 clock-names = "core", "iface";
757 clock-frequency = <400000>;
760 #address-cells = <1>;
764 blsp1_i2c4: i2c@c178000 {
765 compatible = "qcom,i2c-qup-v2.2.1";
766 reg = <0x0c178000 0x600>;
767 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
770 <&gcc GCC_BLSP1_AHB_CLK>;
771 clock-names = "core", "iface";
772 clock-frequency = <400000>;
775 #address-cells = <1>;
779 blsp1_i2c5: i2c@c179000 {
780 compatible = "qcom,i2c-qup-v2.2.1";
781 reg = <0x0c179000 0x600>;
782 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
784 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
785 <&gcc GCC_BLSP1_AHB_CLK>;
786 clock-names = "core", "iface";
787 clock-frequency = <400000>;
790 #address-cells = <1>;
794 blsp1_i2c6: i2c@c17a000 {
795 compatible = "qcom,i2c-qup-v2.2.1";
796 reg = <0x0c17a000 0x600>;
797 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
800 <&gcc GCC_BLSP1_AHB_CLK>;
801 clock-names = "core", "iface";
802 clock-frequency = <400000>;
805 #address-cells = <1>;
809 blsp2_i2c0: i2c@c1b5000 {
810 compatible = "qcom,i2c-qup-v2.2.1";
811 reg = <0x0c1b5000 0x600>;
812 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
815 <&gcc GCC_BLSP2_AHB_CLK>;
816 clock-names = "core", "iface";
817 clock-frequency = <400000>;
820 #address-cells = <1>;
824 blsp2_i2c1: i2c@c1b6000 {
825 compatible = "qcom,i2c-qup-v2.2.1";
826 reg = <0x0c1b6000 0x600>;
827 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
830 <&gcc GCC_BLSP2_AHB_CLK>;
831 clock-names = "core", "iface";
832 clock-frequency = <400000>;
835 #address-cells = <1>;
839 blsp2_i2c2: i2c@c1b7000 {
840 compatible = "qcom,i2c-qup-v2.2.1";
841 reg = <0x0c1b7000 0x600>;
842 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
845 <&gcc GCC_BLSP2_AHB_CLK>;
846 clock-names = "core", "iface";
847 clock-frequency = <400000>;
850 #address-cells = <1>;
854 blsp2_i2c3: i2c@c1b8000 {
855 compatible = "qcom,i2c-qup-v2.2.1";
856 reg = <0x0c1b8000 0x600>;
857 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
859 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
860 <&gcc GCC_BLSP2_AHB_CLK>;
861 clock-names = "core", "iface";
862 clock-frequency = <400000>;
865 #address-cells = <1>;
869 blsp2_i2c4: i2c@c1b9000 {
870 compatible = "qcom,i2c-qup-v2.2.1";
871 reg = <0x0c1b9000 0x600>;
872 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
874 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
875 <&gcc GCC_BLSP2_AHB_CLK>;
876 clock-names = "core", "iface";
877 clock-frequency = <400000>;
880 #address-cells = <1>;
884 blsp2_i2c5: i2c@c1ba000 {
885 compatible = "qcom,i2c-qup-v2.2.1";
886 reg = <0x0c175000 0x600>;
887 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
890 <&gcc GCC_BLSP2_AHB_CLK>;
891 clock-names = "core", "iface";
892 clock-frequency = <400000>;
895 #address-cells = <1>;
899 blsp2_uart1: serial@c1b0000 {
900 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
901 reg = <0xc1b0000 0x1000>;
902 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
904 <&gcc GCC_BLSP2_AHB_CLK>;
905 clock-names = "core", "iface";
910 #address-cells = <1>;
913 compatible = "arm,armv7-timer-mem";
914 reg = <0x17920000 0x1000>;
918 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
919 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
920 reg = <0x17921000 0x1000>,
926 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
927 reg = <0x17923000 0x1000>;
933 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
934 reg = <0x17924000 0x1000>;
940 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
941 reg = <0x17925000 0x1000>;
947 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
948 reg = <0x17926000 0x1000>;
954 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
955 reg = <0x17927000 0x1000>;
961 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
962 reg = <0x17928000 0x1000>;
967 intc: interrupt-controller@17a00000 {
968 compatible = "arm,gic-v3";
969 reg = <0x17a00000 0x10000>, /* GICD */
970 <0x17b00000 0x100000>; /* GICR * 8 */
971 #interrupt-cells = <3>;
972 #address-cells = <1>;
975 interrupt-controller;
976 #redistributor-regions = <1>;
977 redistributor-stride = <0x0 0x20000>;
978 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
983 #include "msm8998-pins.dtsi"