arch/arm64/boot/dts/qcom/msm8998.dtsi

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2016, The Linux Foundation. All rights reserved. */
   3
   4 #include <dt-bindings/interrupt-controller/arm-gic.h>
   5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
   6 #include <dt-bindings/clock/qcom,rpmcc.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8
   9 / {
  10         interrupt-parent = <&intc>;
  11
  12         qcom,msm-id = <292 0x0>;
  13
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         chosen { };
  18
  19         memory {
  20                 device_type = "memory";
  21                 /* We expect the bootloader to fill in the reg */
  22                 reg = <0 0 0 0>;
  23         };
  24
  25         reserved-memory {
  26                 #address-cells = <2>;
  27                 #size-cells = <2>;
  28                 ranges;
  29
  30                 memory@85800000 {
  31                         reg = <0x0 0x85800000 0x0 0x800000>;
  32                         no-map;
  33                 };
  34
  35                 smem_mem: smem-mem@86000000 {
  36                         reg = <0x0 0x86000000 0x0 0x200000>;
  37                         no-map;
  38                 };
  39
  40                 memory@86200000 {
  41                         reg = <0x0 0x86200000 0x0 0x2d00000>;
  42                         no-map;
  43                 };
  44
  45                 rmtfs {
  46                         compatible = "qcom,rmtfs-mem";
  47
  48                         size = <0x0 0x200000>;
  49                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  50                         no-map;
  51
  52                         qcom,client-id = <1>;
  53                         qcom,vmid = <15>;
  54                 };
  55         };
  56
  57         clocks {
  58                 xo: xo-board {
  59                         compatible = "fixed-clock";
  60                         #clock-cells = <0>;
  61                         clock-frequency = <19200000>;
  62                         clock-output-names = "xo_board";
  63                 };
  64
  65                 sleep_clk {
  66                         compatible = "fixed-clock";
  67                         #clock-cells = <0>;
  68                         clock-frequency = <32764>;
  69                 };
  70         };
  71
  72         cpus {
  73                 #address-cells = <2>;
  74                 #size-cells = <0>;
  75
  76                 CPU0: cpu@0 {
  77                         device_type = "cpu";
  78                         compatible = "arm,armv8";
  79                         reg = <0x0 0x0>;
  80                         enable-method = "psci";
  81                         efficiency = <1024>;
  82                         next-level-cache = <&L2_0>;
  83                         L2_0: l2-cache {
  84                                 compatible = "arm,arch-cache";
  85                                 cache-level = <2>;
  86                         };
  87                         L1_I_0: l1-icache {
  88                                 compatible = "arm,arch-cache";
  89                         };
  90                         L1_D_0: l1-dcache {
  91                                 compatible = "arm,arch-cache";
  92                         };
  93                 };
  94
  95                 CPU1: cpu@1 {
  96                         device_type = "cpu";
  97                         compatible = "arm,armv8";
  98                         reg = <0x0 0x1>;
  99                         enable-method = "psci";
 100                         efficiency = <1024>;
 101                         next-level-cache = <&L2_0>;
 102                         L1_I_1: l1-icache {
 103                                 compatible = "arm,arch-cache";
 104                         };
 105                         L1_D_1: l1-dcache {
 106                                 compatible = "arm,arch-cache";
 107                         };
 108                 };
 109
 110                 CPU2: cpu@2 {
 111                         device_type = "cpu";
 112                         compatible = "arm,armv8";
 113                         reg = <0x0 0x2>;
 114                         enable-method = "psci";
 115                         efficiency = <1024>;
 116                         next-level-cache = <&L2_0>;
 117                         L1_I_2: l1-icache {
 118                                 compatible = "arm,arch-cache";
 119                         };
 120                         L1_D_2: l1-dcache {
 121                                 compatible = "arm,arch-cache";
 122                         };
 123                 };
 124
 125                 CPU3: cpu@3 {
 126                         device_type = "cpu";
 127                         compatible = "arm,armv8";
 128                         reg = <0x0 0x3>;
 129                         enable-method = "psci";
 130                         efficiency = <1024>;
 131                         next-level-cache = <&L2_0>;
 132                         L1_I_3: l1-icache {
 133                                 compatible = "arm,arch-cache";
 134                         };
 135                         L1_D_3: l1-dcache {
 136                                 compatible = "arm,arch-cache";
 137                         };
 138                 };
 139
 140                 CPU4: cpu@100 {
 141                         device_type = "cpu";
 142                         compatible = "arm,armv8";
 143                         reg = <0x0 0x100>;
 144                         enable-method = "psci";
 145                         efficiency = <1536>;
 146                         next-level-cache = <&L2_1>;
 147                         L2_1: l2-cache {
 148                                 compatible = "arm,arch-cache";
 149                                 cache-level = <2>;
 150                         };
 151                         L1_I_100: l1-icache {
 152                                 compatible = "arm,arch-cache";
 153                         };
 154                         L1_D_100: l1-dcache {
 155                                 compatible = "arm,arch-cache";
 156                         };
 157                 };
 158
 159                 CPU5: cpu@101 {
 160                         device_type = "cpu";
 161                         compatible = "arm,armv8";
 162                         reg = <0x0 0x101>;
 163                         enable-method = "psci";
 164                         efficiency = <1536>;
 165                         next-level-cache = <&L2_1>;
 166                         L1_I_101: l1-icache {
 167                                 compatible = "arm,arch-cache";
 168                         };
 169                         L1_D_101: l1-dcache {
 170                                 compatible = "arm,arch-cache";
 171                         };
 172                 };
 173
 174                 CPU6: cpu@102 {
 175                         device_type = "cpu";
 176                         compatible = "arm,armv8";
 177                         reg = <0x0 0x102>;
 178                         enable-method = "psci";
 179                         efficiency = <1536>;
 180                         next-level-cache = <&L2_1>;
 181                         L1_I_102: l1-icache {
 182                                 compatible = "arm,arch-cache";
 183                         };
 184                         L1_D_102: l1-dcache {
 185                                 compatible = "arm,arch-cache";
 186                         };
 187                 };
 188
 189                 CPU7: cpu@103 {
 190                         device_type = "cpu";
 191                         compatible = "arm,armv8";
 192                         reg = <0x0 0x103>;
 193                         enable-method = "psci";
 194                         efficiency = <1536>;
 195                         next-level-cache = <&L2_1>;
 196                         L1_I_103: l1-icache {
 197                                 compatible = "arm,arch-cache";
 198                         };
 199                         L1_D_103: l1-dcache {
 200                                 compatible = "arm,arch-cache";
 201                         };
 202                 };
 203
 204                 cpu-map {
 205                         cluster0 {
 206                                 core0 {
 207                                         cpu = <&CPU0>;
 208                                 };
 209
 210                                 core1 {
 211                                         cpu = <&CPU1>;
 212                                 };
 213
 214                                 core2 {
 215                                         cpu = <&CPU2>;
 216                                 };
 217
 218                                 core3 {
 219                                         cpu = <&CPU3>;
 220                                 };
 221                         };
 222
 223                         cluster1 {
 224                                 core0 {
 225                                         cpu = <&CPU4>;
 226                                 };
 227
 228                                 core1 {
 229                                         cpu = <&CPU5>;
 230                                 };
 231
 232                                 core2 {
 233                                         cpu = <&CPU6>;
 234                                 };
 235
 236                                 core3 {
 237                                         cpu = <&CPU7>;
 238                                 };
 239                         };
 240                 };
 241         };
 242
 243         firmware {
 244                 scm {
 245                         compatible = "qcom,scm-msm8998", "qcom,scm";
 246                 };
 247         };
 248
 249         tcsr_mutex: hwlock {
 250                 compatible = "qcom,tcsr-mutex";
 251                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 252                 #hwlock-cells = <1>;
 253         };
 254
 255         psci {
 256                 compatible = "arm,psci-1.0";
 257                 method = "smc";
 258         };
 259
 260         rpm-glink {
 261                 compatible = "qcom,glink-rpm";
 262
 263                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 264                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 265                 mboxes = <&apcs_glb 0>;
 266
 267                 rpm_requests: rpm-requests {
 268                         compatible = "qcom,rpm-msm8998";
 269                         qcom,glink-channels = "rpm_requests";
 270
 271                         rpmcc: clock-controller {
 272                                 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
 273                                 #clock-cells = <1>;
 274                         };
 275                 };
 276         };
 277
 278         smem {
 279                 compatible = "qcom,smem";
 280                 memory-region = <&smem_mem>;
 281                 hwlocks = <&tcsr_mutex 3>;
 282         };
 283
 284         smp2p-lpass {
 285                 compatible = "qcom,smp2p";
 286                 qcom,smem = <443>, <429>;
 287
 288                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 289
 290                 mboxes = <&apcs_glb 10>;
 291
 292                 qcom,local-pid = <0>;
 293                 qcom,remote-pid = <2>;
 294
 295                 adsp_smp2p_out: master-kernel {
 296                         qcom,entry-name = "master-kernel";
 297                         #qcom,smem-state-cells = <1>;
 298                 };
 299
 300                 adsp_smp2p_in: slave-kernel {
 301                         qcom,entry-name = "slave-kernel";
 302
 303                         interrupt-controller;
 304                         #interrupt-cells = <2>;
 305                 };
 306         };
 307
 308         smp2p-mpss {
 309                 compatible = "qcom,smp2p";
 310                 qcom,smem = <435>, <428>;
 311                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 312                 mboxes = <&apcs_glb 14>;
 313                 qcom,local-pid = <0>;
 314                 qcom,remote-pid = <1>;
 315
 316                 modem_smp2p_out: master-kernel {
 317                         qcom,entry-name = "master-kernel";
 318                         #qcom,smem-state-cells = <1>;
 319                 };
 320
 321                 modem_smp2p_in: slave-kernel {
 322                         qcom,entry-name = "slave-kernel";
 323                         interrupt-controller;
 324                         #interrupt-cells = <2>;
 325                 };
 326         };
 327
 328         smp2p-slpi {
 329                 compatible = "qcom,smp2p";
 330                 qcom,smem = <481>, <430>;
 331                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
 332                 mboxes = <&apcs_glb 26>;
 333                 qcom,local-pid = <0>;
 334                 qcom,remote-pid = <3>;
 335
 336                 slpi_smp2p_out: master-kernel {
 337                         qcom,entry-name = "master-kernel";
 338                         #qcom,smem-state-cells = <1>;
 339                 };
 340
 341                 slpi_smp2p_in: slave-kernel {
 342                         qcom,entry-name = "slave-kernel";
 343                         interrupt-controller;
 344                         #interrupt-cells = <2>;
 345                 };
 346         };
 347
 348         thermal-zones {
 349                 cpu-thermal0 {
 350                         polling-delay-passive = <250>;
 351                         polling-delay = <1000>;
 352
 353                         thermal-sensors = <&tsens0 6>;
 354
 355                         trips {
 356                                 cpu_alert0: trip0 {
 357                                         temperature = <75000>;
 358                                         hysteresis = <2000>;
 359                                         type = "passive";
 360                                 };
 361
 362                                 cpu_crit0: trip1 {
 363                                         temperature = <110000>;
 364                                         hysteresis = <2000>;
 365                                         type = "critical";
 366                                 };
 367                         };
 368                 };
 369
 370                 cpu-thermal1 {
 371                         polling-delay-passive = <250>;
 372                         polling-delay = <1000>;
 373
 374                         thermal-sensors = <&tsens0 7>;
 375
 376                         trips {
 377                                 cpu_alert1: trip0 {
 378                                         temperature = <75000>;
 379                                         hysteresis = <2000>;
 380                                         type = "passive";
 381                                 };
 382
 383                                 cpu_crit1: trip1 {
 384                                         temperature = <110000>;
 385                                         hysteresis = <2000>;
 386                                         type = "critical";
 387                                 };
 388                         };
 389                 };
 390
 391                 cpu-thermal2 {
 392                         polling-delay-passive = <250>;
 393                         polling-delay = <1000>;
 394
 395                         thermal-sensors = <&tsens0 8>;
 396
 397                         trips {
 398                                 cpu_alert2: trip0 {
 399                                         temperature = <75000>;
 400                                         hysteresis = <2000>;
 401                                         type = "passive";
 402                                 };
 403
 404                                 cpu_crit2: trip1 {
 405                                         temperature = <110000>;
 406                                         hysteresis = <2000>;
 407                                         type = "critical";
 408                                 };
 409                         };
 410                 };
 411
 412                 cpu-thermal3 {
 413                         polling-delay-passive = <250>;
 414                         polling-delay = <1000>;
 415
 416                         thermal-sensors = <&tsens0 9>;
 417
 418                         trips {
 419                                 cpu_alert3: trip0 {
 420                                         temperature = <75000>;
 421                                         hysteresis = <2000>;
 422                                         type = "passive";
 423                                 };
 424
 425                                 cpu_crit3: trip1 {
 426                                         temperature = <110000>;
 427                                         hysteresis = <2000>;
 428                                         type = "critical";
 429                                 };
 430                         };
 431                 };
 432
 433                 cpu-thermal4 {
 434                         polling-delay-passive = <250>;
 435                         polling-delay = <1000>;
 436
 437                         thermal-sensors = <&tsens0 10>;
 438
 439                         trips {
 440                                 cpu_alert4: trip0 {
 441                                         temperature = <75000>;
 442                                         hysteresis = <2000>;
 443                                         type = "passive";
 444                                 };
 445
 446                                 cpu_crit4: trip1 {
 447                                         temperature = <110000>;
 448                                         hysteresis = <2000>;
 449                                         type = "critical";
 450                                 };
 451                         };
 452                 };
 453
 454                 cpu-thermal5 {
 455                         polling-delay-passive = <250>;
 456                         polling-delay = <1000>;
 457
 458                         thermal-sensors = <&tsens0 11>;
 459
 460                         trips {
 461                                 cpu_alert5: trip0 {
 462                                         temperature = <75000>;
 463                                         hysteresis = <2000>;
 464                                         type = "passive";
 465                                 };
 466
 467                                 cpu_crit5: trip1 {
 468                                         temperature = <110000>;
 469                                         hysteresis = <2000>;
 470                                         type = "critical";
 471                                 };
 472                         };
 473                 };
 474
 475                 cpu-thermal6 {
 476                         polling-delay-passive = <250>;
 477                         polling-delay = <1000>;
 478
 479                         thermal-sensors = <&tsens1 0>;
 480
 481                         trips {
 482                                 cpu_alert6: trip0 {
 483                                         temperature = <75000>;
 484                                         hysteresis = <2000>;
 485                                         type = "passive";
 486                                 };
 487
 488                                 cpu_crit6: trip1 {
 489                                         temperature = <110000>;
 490                                         hysteresis = <2000>;
 491                                         type = "critical";
 492                                 };
 493                         };
 494                 };
 495
 496                 cpu-thermal7 {
 497                         polling-delay-passive = <250>;
 498                         polling-delay = <1000>;
 499
 500                         thermal-sensors = <&tsens1 1>;
 501
 502                         trips {
 503                                 cpu_alert7: trip0 {
 504                                         temperature = <75000>;
 505                                         hysteresis = <2000>;
 506                                         type = "passive";
 507                                 };
 508
 509                                 cpu_crit7: trip1 {
 510                                         temperature = <110000>;
 511                                         hysteresis = <2000>;
 512                                         type = "critical";
 513                                 };
 514                         };
 515                 };
 516
 517                 gpu-thermal {
 518                         polling-delay-passive = <250>;
 519                         polling-delay = <1000>;
 520
 521                         thermal-sensors = <&tsens1 3>;
 522                 };
 523         };
 524
 525         timer {
 526                 compatible = "arm,armv8-timer";
 527                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
 528                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
 529                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
 530                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
 531         };
 532
 533         soc: soc {
 534                 #address-cells = <1>;
 535                 #size-cells = <1>;
 536                 ranges = <0 0 0 0xffffffff>;
 537                 compatible = "simple-bus";
 538
 539                 rpm_msg_ram: memory@68000 {
 540                         compatible = "qcom,rpm-msg-ram";
 541                         reg = <0x778000 0x7000>;
 542                 };
 543
 544                 qfprom: qfprom@780000 {
 545                         compatible = "qcom,qfprom";
 546                         reg = <0x780000 0x621c>;
 547                         #address-cells = <1>;
 548                         #size-cells = <1>;
 549
 550                         qusb2_hstx_trim: hstx-trim@423a {
 551                                 reg = <0x423a 0x1>;
 552                                 bits = <0 4>;
 553                         };
 554                 };
 555
 556                 gcc: clock-controller@100000 {
 557                         compatible = "qcom,gcc-msm8998";
 558                         #clock-cells = <1>;
 559                         #reset-cells = <1>;
 560                         #power-domain-cells = <1>;
 561                         reg = <0x100000 0xb0000>;
 562                 };
 563
 564                 tlmm: pinctrl@3400000 {
 565                         compatible = "qcom,msm8998-pinctrl";
 566                         reg = <0x3400000 0xc00000>;
 567                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 568                         gpio-controller;
 569                         #gpio-cells = <0x2>;
 570                         interrupt-controller;
 571                         #interrupt-cells = <0x2>;
 572                 };
 573
 574                 spmi_bus: spmi@800f000 {
 575                         compatible = "qcom,spmi-pmic-arb";
 576                         reg =   <0x800f000 0x1000>,
 577                                 <0x8400000 0x1000000>,
 578                                 <0x9400000 0x1000000>,
 579                                 <0xa400000 0x220000>,
 580                                 <0x800a000 0x3000>;
 581                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 582                         interrupt-names = "periph_irq";
 583                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 584                         qcom,ee = <0>;
 585                         qcom,channel = <0>;
 586                         #address-cells = <2>;
 587                         #size-cells = <0>;
 588                         interrupt-controller;
 589                         #interrupt-cells = <4>;
 590                         cell-index = <0>;
 591                 };
 592
 593                 tsens0: thermal@10aa000 {
 594                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 595                         reg = <0x10aa000 0x2000>;
 596
 597                         #qcom,sensors = <12>;
 598                         #thermal-sensor-cells = <1>;
 599                 };
 600
 601                 tsens1: thermal@10ad000 {
 602                         compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
 603                         reg = <0x10ad000 0x2000>;
 604
 605                         #qcom,sensors = <8>;
 606                         #thermal-sensor-cells = <1>;
 607                 };
 608
 609                 tcsr_mutex_regs: syscon@1f40000 {
 610                         compatible = "syscon";
 611                         reg = <0x1f40000 0x20000>;
 612                 };
 613
 614                 apcs_glb: mailbox@9820000 {
 615                         compatible = "qcom,msm8998-apcs-hmss-global";
 616                         reg = <0x17911000 0x1000>;
 617
 618                         #mbox-cells = <1>;
 619                 };
 620
 621                 usb3: usb@a8f8800 {
 622                         compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
 623                         reg = <0x0a8f8800 0x400>;
 624                         status = "disabled";
 625                         #address-cells = <1>;
 626                         #size-cells = <1>;
 627                         ranges;
 628
 629                         clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>,
 630                                  <&gcc GCC_USB30_MASTER_CLK>,
 631                                  <&gcc GCC_AGGRE1_USB3_AXI_CLK>,
 632                                  <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 633                                  <&gcc GCC_USB30_SLEEP_CLK>;
 634                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
 635                                       "sleep";
 636
 637                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 638                                           <&gcc GCC_USB30_MASTER_CLK>;
 639                         assigned-clock-rates = <19200000>, <120000000>;
 640
 641                         interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 642                                      <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
 643                         interrupt-names = "hs_phy_irq", "ss_phy_irq";
 644
 645                         power-domains = <&gcc USB_30_GDSC>;
 646
 647                         resets = <&gcc GCC_USB_30_BCR>;
 648
 649                         usb3_dwc3: dwc3@a800000 {
 650                                 compatible = "snps,dwc3";
 651                                 reg = <0x0a800000 0xcd00>;
 652                                 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
 653                                 snps,dis_u2_susphy_quirk;
 654                                 snps,dis_enblslpm_quirk;
 655                                 phys = <&qusb2phy>, <&usb1_ssphy>;
 656                                 phy-names = "usb2-phy", "usb3-phy";
 657                                 snps,has-lpm-erratum;
 658                                 snps,hird-threshold = /bits/ 8 <0x10>;
 659                         };
 660                 };
 661
 662                 usb3phy: phy@c010000 {
 663                         compatible = "qcom,msm8998-qmp-usb3-phy";
 664                         reg = <0x0c010000 0x18c>;
 665                         status = "disabled";
 666                         #clock-cells = <1>;
 667                         #address-cells = <1>;
 668                         #size-cells = <1>;
 669                         ranges;
 670
 671                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 672                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 673                                  <&gcc GCC_USB3_CLKREF_CLK>;
 674                         clock-names = "aux", "cfg_ahb", "ref";
 675
 676                         resets = <&gcc GCC_USB3_PHY_BCR>,
 677                                  <&gcc GCC_USB3PHY_PHY_BCR>;
 678                         reset-names = "phy", "common";
 679
 680                         usb1_ssphy: lane@c010200 {
 681                                 reg = <0xc010200 0x128>,
 682                                       <0xc010400 0x200>,
 683                                       <0xc010c00 0x20c>,
 684                                       <0xc010600 0x128>,
 685                                       <0xc010800 0x200>;
 686                                 #phy-cells = <0>;
 687                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 688                                 clock-names = "pipe0";
 689                                 clock-output-names = "usb3_phy_pipe_clk_src";
 690                         };
 691                 };
 692
 693                 qusb2phy: phy@c012000 {
 694                         compatible = "qcom,msm8998-qusb2-phy";
 695                         reg = <0x0c012000 0x2a8>;
 696                         status = "disabled";
 697                         #phy-cells = <0>;
 698
 699                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 700                                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 701                         clock-names = "cfg_ahb", "ref";
 702
 703                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 704
 705                         nvmem-cells = <&qusb2_hstx_trim>;
 706                 };
 707
 708                 sdhc2: sdhci@c0a4900 {
 709                         compatible = "qcom,sdhci-msm-v4";
 710                         reg = <0xc0a4900 0x314>, <0xc0a4000 0x800>;
 711                         reg-names = "hc_mem", "core_mem";
 712
 713                         interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
 714                                      <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
 715                         interrupt-names = "hc_irq", "pwr_irq";
 716
 717                         clock-names = "iface", "core", "xo";
 718                         clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 719                                  <&gcc GCC_SDCC2_APPS_CLK>,
 720                                  <&xo>;
 721                         bus-width = <4>;
 722                         status = "disabled";
 723                 };
 724
 725                 blsp1_i2c1: i2c@c175000 {
 726                         compatible = "qcom,i2c-qup-v2.2.1";
 727                         reg = <0x0c175000 0x600>;
 728                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 729
 730                         clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
 731                                  <&gcc GCC_BLSP1_AHB_CLK>;
 732                         clock-names = "core", "iface";
 733                         clock-frequency = <400000>;
 734
 735                         status = "disabled";
 736                         #address-cells = <1>;
 737                         #size-cells = <0>;
 738                 };
 739
 740                 blsp1_i2c2: i2c@c176000 {
 741                         compatible = "qcom,i2c-qup-v2.2.1";
 742                         reg = <0x0c176000 0x600>;
 743                         interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 744
 745                         clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
 746                                  <&gcc GCC_BLSP1_AHB_CLK>;
 747                         clock-names = "core", "iface";
 748                         clock-frequency = <400000>;
 749
 750                         status = "disabled";
 751                         #address-cells = <1>;
 752                         #size-cells = <0>;
 753                 };
 754
 755                 blsp1_i2c3: i2c@c177000 {
 756                         compatible = "qcom,i2c-qup-v2.2.1";
 757                         reg = <0x0c177000 0x600>;
 758                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 759
 760                         clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
 761                                  <&gcc GCC_BLSP1_AHB_CLK>;
 762                         clock-names = "core", "iface";
 763                         clock-frequency = <400000>;
 764
 765                         status = "disabled";
 766                         #address-cells = <1>;
 767                         #size-cells = <0>;
 768                 };
 769
 770                 blsp1_i2c4: i2c@c178000 {
 771                         compatible = "qcom,i2c-qup-v2.2.1";
 772                         reg = <0x0c178000 0x600>;
 773                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 774
 775                         clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
 776                                  <&gcc GCC_BLSP1_AHB_CLK>;
 777                         clock-names = "core", "iface";
 778                         clock-frequency = <400000>;
 779
 780                         status = "disabled";
 781                         #address-cells = <1>;
 782                         #size-cells = <0>;
 783                 };
 784
 785                 blsp1_i2c5: i2c@c179000 {
 786                         compatible = "qcom,i2c-qup-v2.2.1";
 787                         reg = <0x0c179000 0x600>;
 788                         interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
 789
 790                         clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
 791                                  <&gcc GCC_BLSP1_AHB_CLK>;
 792                         clock-names = "core", "iface";
 793                         clock-frequency = <400000>;
 794
 795                         status = "disabled";
 796                         #address-cells = <1>;
 797                         #size-cells = <0>;
 798                 };
 799
 800                 blsp1_i2c6: i2c@c17a000 {
 801                         compatible = "qcom,i2c-qup-v2.2.1";
 802                         reg = <0x0c17a000 0x600>;
 803                         interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
 804
 805                         clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
 806                                  <&gcc GCC_BLSP1_AHB_CLK>;
 807                         clock-names = "core", "iface";
 808                         clock-frequency = <400000>;
 809
 810                         status = "disabled";
 811                         #address-cells = <1>;
 812                         #size-cells = <0>;
 813                 };
 814
 815                 blsp2_i2c0: i2c@c1b5000 {
 816                         compatible = "qcom,i2c-qup-v2.2.1";
 817                         reg = <0x0c1b5000 0x600>;
 818                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 819
 820                         clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
 821                                  <&gcc GCC_BLSP2_AHB_CLK>;
 822                         clock-names = "core", "iface";
 823                         clock-frequency = <400000>;
 824
 825                         status = "disabled";
 826                         #address-cells = <1>;
 827                         #size-cells = <0>;
 828                 };
 829
 830                 blsp2_i2c1: i2c@c1b6000 {
 831                         compatible = "qcom,i2c-qup-v2.2.1";
 832                         reg = <0x0c1b6000 0x600>;
 833                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 834
 835                         clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
 836                                  <&gcc GCC_BLSP2_AHB_CLK>;
 837                         clock-names = "core", "iface";
 838                         clock-frequency = <400000>;
 839
 840                         status = "disabled";
 841                         #address-cells = <1>;
 842                         #size-cells = <0>;
 843                 };
 844
 845                 blsp2_i2c2: i2c@c1b7000 {
 846                         compatible = "qcom,i2c-qup-v2.2.1";
 847                         reg = <0x0c1b7000 0x600>;
 848                         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 849
 850                         clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
 851                                  <&gcc GCC_BLSP2_AHB_CLK>;
 852                         clock-names = "core", "iface";
 853                         clock-frequency = <400000>;
 854
 855                         status = "disabled";
 856                         #address-cells = <1>;
 857                         #size-cells = <0>;
 858                 };
 859
 860                 blsp2_i2c3: i2c@c1b8000 {
 861                         compatible = "qcom,i2c-qup-v2.2.1";
 862                         reg = <0x0c1b8000 0x600>;
 863                         interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
 864
 865                         clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
 866                                  <&gcc GCC_BLSP2_AHB_CLK>;
 867                         clock-names = "core", "iface";
 868                         clock-frequency = <400000>;
 869
 870                         status = "disabled";
 871                         #address-cells = <1>;
 872                         #size-cells = <0>;
 873                 };
 874
 875                 blsp2_i2c4: i2c@c1b9000 {
 876                         compatible = "qcom,i2c-qup-v2.2.1";
 877                         reg = <0x0c1b9000 0x600>;
 878                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
 879
 880                         clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
 881                                  <&gcc GCC_BLSP2_AHB_CLK>;
 882                         clock-names = "core", "iface";
 883                         clock-frequency = <400000>;
 884
 885                         status = "disabled";
 886                         #address-cells = <1>;
 887                         #size-cells = <0>;
 888                 };
 889
 890                 blsp2_i2c5: i2c@c1ba000 {
 891                         compatible = "qcom,i2c-qup-v2.2.1";
 892                         reg = <0x0c175000 0x600>;
 893                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 894
 895                         clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
 896                                  <&gcc GCC_BLSP2_AHB_CLK>;
 897                         clock-names = "core", "iface";
 898                         clock-frequency = <400000>;
 899
 900                         status = "disabled";
 901                         #address-cells = <1>;
 902                         #size-cells = <0>;
 903                 };
 904
 905                 blsp2_uart1: serial@c1b0000 {
 906                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 907                         reg = <0xc1b0000 0x1000>;
 908                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 909                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 910                                  <&gcc GCC_BLSP2_AHB_CLK>;
 911                         clock-names = "core", "iface";
 912                         status = "disabled";
 913                 };
 914
 915                 timer@17920000 {
 916                         #address-cells = <1>;
 917                         #size-cells = <1>;
 918                         ranges;
 919                         compatible = "arm,armv7-timer-mem";
 920                         reg = <0x17920000 0x1000>;
 921
 922                         frame@17921000 {
 923                                 frame-number = <0>;
 924                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 925                                              <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 926                                 reg = <0x17921000 0x1000>,
 927                                       <0x17922000 0x1000>;
 928                         };
 929
 930                         frame@17923000 {
 931                                 frame-number = <1>;
 932                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 933                                 reg = <0x17923000 0x1000>;
 934                                 status = "disabled";
 935                         };
 936
 937                         frame@17924000 {
 938                                 frame-number = <2>;
 939                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 940                                 reg = <0x17924000 0x1000>;
 941                                 status = "disabled";
 942                         };
 943
 944                         frame@17925000 {
 945                                 frame-number = <3>;
 946                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 947                                 reg = <0x17925000 0x1000>;
 948                                 status = "disabled";
 949                         };
 950
 951                         frame@17926000 {
 952                                 frame-number = <4>;
 953                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 954                                 reg = <0x17926000 0x1000>;
 955                                 status = "disabled";
 956                         };
 957
 958                         frame@17927000 {
 959                                 frame-number = <5>;
 960                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
 961                                 reg = <0x17927000 0x1000>;
 962                                 status = "disabled";
 963                         };
 964
 965                         frame@17928000 {
 966                                 frame-number = <6>;
 967                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
 968                                 reg = <0x17928000 0x1000>;
 969                                 status = "disabled";
 970                         };
 971                 };
 972
 973                 intc: interrupt-controller@17a00000 {
 974                         compatible = "arm,gic-v3";
 975                         reg = <0x17a00000 0x10000>,       /* GICD */
 976                               <0x17b00000 0x100000>;      /* GICR * 8 */
 977                         #interrupt-cells = <3>;
 978                         #address-cells = <1>;
 979                         #size-cells = <1>;
 980                         ranges;
 981                         interrupt-controller;
 982                         #redistributor-regions = <1>;
 983                         redistributor-stride = <0x0 0x20000>;
 984                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 985                 };
 986         };
 987 };
 988
 989 #include "msm8998-pins.dtsi"