arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16 #include <dt-bindings/clock/qcom,rpmcc.h>
  17
  18 / {
  19         interrupt-parent = <&intc>;
  20
  21         #address-cells = <2>;
  22         #size-cells = <2>;
  23
  24         chosen { };
  25
  26         memory {
  27                 device_type = "memory";
  28                 /* We expect the bootloader to fill in the reg */
  29                 reg = <0 0 0 0>;
  30         };
  31
  32         reserved-memory {
  33                 #address-cells = <2>;
  34                 #size-cells = <2>;
  35                 ranges;
  36
  37                 mba_region: mba@91500000 {
  38                         reg = <0x0 0x91500000 0x0 0x200000>;
  39                         no-map;
  40                 };
  41
  42                 slpi_region: slpi@90b00000 {
  43                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  44                         no-map;
  45                 };
  46
  47                 venus_region: venus@90400000 {
  48                         reg = <0x0 0x90400000 0x0 0x700000>;
  49                         no-map;
  50                 };
  51
  52                 adsp_region: adsp@8ea00000 {
  53                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  54                         no-map;
  55                 };
  56
  57                 mpss_region: mpss@88800000 {
  58                         reg = <0x0 0x88800000 0x0 0x6200000>;
  59                         no-map;
  60                 };
  61
  62                 smem_mem: smem-mem@86000000 {
  63                         reg = <0x0 0x86000000 0x0 0x200000>;
  64                         no-map;
  65                 };
  66
  67                 memory@85800000 {
  68                         reg = <0x0 0x85800000 0x0 0x800000>;
  69                         no-map;
  70                 };
  71
  72                 memory@86200000 {
  73                         reg = <0x0 0x86200000 0x0 0x2600000>;
  74                         no-map;
  75                 };
  76
  77                 rmtfs@86700000 {
  78                         compatible = "qcom,rmtfs-mem";
  79
  80                         size = <0x0 0x200000>;
  81                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  82                         no-map;
  83
  84                         qcom,client-id = <1>;
  85                         qcom,vmid = <15>;
  86                 };
  87         };
  88
  89         cpus {
  90                 #address-cells = <2>;
  91                 #size-cells = <0>;
  92
  93                 CPU0: cpu@0 {
  94                         device_type = "cpu";
  95                         compatible = "qcom,kryo";
  96                         reg = <0x0 0x0>;
  97                         enable-method = "psci";
  98                         next-level-cache = <&L2_0>;
  99                         L2_0: l2-cache {
 100                               compatible = "cache";
 101                               cache-level = <2>;
 102                         };
 103                 };
 104
 105                 CPU1: cpu@1 {
 106                         device_type = "cpu";
 107                         compatible = "qcom,kryo";
 108                         reg = <0x0 0x1>;
 109                         enable-method = "psci";
 110                         next-level-cache = <&L2_0>;
 111                 };
 112
 113                 CPU2: cpu@100 {
 114                         device_type = "cpu";
 115                         compatible = "qcom,kryo";
 116                         reg = <0x0 0x100>;
 117                         enable-method = "psci";
 118                         next-level-cache = <&L2_1>;
 119                         L2_1: l2-cache {
 120                               compatible = "cache";
 121                               cache-level = <2>;
 122                         };
 123                 };
 124
 125                 CPU3: cpu@101 {
 126                         device_type = "cpu";
 127                         compatible = "qcom,kryo";
 128                         reg = <0x0 0x101>;
 129                         enable-method = "psci";
 130                         next-level-cache = <&L2_1>;
 131                 };
 132
 133                 cpu-map {
 134                         cluster0 {
 135                                 core0 {
 136                                         cpu = <&CPU0>;
 137                                 };
 138
 139                                 core1 {
 140                                         cpu = <&CPU1>;
 141                                 };
 142                         };
 143
 144                         cluster1 {
 145                                 core0 {
 146                                         cpu = <&CPU2>;
 147                                 };
 148
 149                                 core1 {
 150                                         cpu = <&CPU3>;
 151                                 };
 152                         };
 153                 };
 154         };
 155
 156         thermal-zones {
 157                 cpu-thermal0 {
 158                         polling-delay-passive = <250>;
 159                         polling-delay = <1000>;
 160
 161                         thermal-sensors = <&tsens0 3>;
 162
 163                         trips {
 164                                 cpu_alert0: trip0 {
 165                                         temperature = <75000>;
 166                                         hysteresis = <2000>;
 167                                         type = "passive";
 168                                 };
 169
 170                                 cpu_crit0: trip1 {
 171                                         temperature = <110000>;
 172                                         hysteresis = <2000>;
 173                                         type = "critical";
 174                                 };
 175                         };
 176                 };
 177
 178                 cpu-thermal1 {
 179                         polling-delay-passive = <250>;
 180                         polling-delay = <1000>;
 181
 182                         thermal-sensors = <&tsens0 5>;
 183
 184                         trips {
 185                                 cpu_alert1: trip0 {
 186                                         temperature = <75000>;
 187                                         hysteresis = <2000>;
 188                                         type = "passive";
 189                                 };
 190
 191                                 cpu_crit1: trip1 {
 192                                         temperature = <110000>;
 193                                         hysteresis = <2000>;
 194                                         type = "critical";
 195                                 };
 196                         };
 197                 };
 198
 199                 cpu-thermal2 {
 200                         polling-delay-passive = <250>;
 201                         polling-delay = <1000>;
 202
 203                         thermal-sensors = <&tsens0 8>;
 204
 205                         trips {
 206                                 cpu_alert2: trip0 {
 207                                         temperature = <75000>;
 208                                         hysteresis = <2000>;
 209                                         type = "passive";
 210                                 };
 211
 212                                 cpu_crit2: trip1 {
 213                                         temperature = <110000>;
 214                                         hysteresis = <2000>;
 215                                         type = "critical";
 216                                 };
 217                         };
 218                 };
 219
 220                 cpu-thermal3 {
 221                         polling-delay-passive = <250>;
 222                         polling-delay = <1000>;
 223
 224                         thermal-sensors = <&tsens0 10>;
 225
 226                         trips {
 227                                 cpu_alert3: trip0 {
 228                                         temperature = <75000>;
 229                                         hysteresis = <2000>;
 230                                         type = "passive";
 231                                 };
 232
 233                                 cpu_crit3: trip1 {
 234                                         temperature = <110000>;
 235                                         hysteresis = <2000>;
 236                                         type = "critical";
 237                                 };
 238                         };
 239                 };
 240         };
 241
 242         timer {
 243                 compatible = "arm,armv8-timer";
 244                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 245                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 246                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 248         };
 249
 250         clocks {
 251                 xo_board: xo_board {
 252                         compatible = "fixed-clock";
 253                         #clock-cells = <0>;
 254                         clock-frequency = <19200000>;
 255                         clock-output-names = "xo_board";
 256                 };
 257
 258                 sleep_clk: sleep_clk {
 259                         compatible = "fixed-clock";
 260                         #clock-cells = <0>;
 261                         clock-frequency = <32764>;
 262                         clock-output-names = "sleep_clk";
 263                 };
 264         };
 265
 266         psci {
 267                 compatible = "arm,psci-1.0";
 268                 method = "smc";
 269         };
 270
 271         firmware {
 272                 scm {
 273                         compatible = "qcom,scm-msm8996";
 274
 275                         qcom,dload-mode = <&tcsr 0x13000>;
 276                 };
 277         };
 278
 279         tcsr_mutex: hwlock {
 280                 compatible = "qcom,tcsr-mutex";
 281                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 282                 #hwlock-cells = <1>;
 283         };
 284
 285         smem {
 286                 compatible = "qcom,smem";
 287                 memory-region = <&smem_mem>;
 288                 hwlocks = <&tcsr_mutex 3>;
 289         };
 290
 291         rpm-glink {
 292                 compatible = "qcom,glink-rpm";
 293
 294                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 295
 296                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 297
 298                 mboxes = <&apcs_glb 0>;
 299
 300                 rpm_requests {
 301                         compatible = "qcom,rpm-msm8996";
 302                         qcom,glink-channels = "rpm_requests";
 303
 304                         rpmcc: qcom,rpmcc {
 305                                 compatible = "qcom,rpmcc-msm8996";
 306                                 #clock-cells = <1>;
 307                         };
 308
 309                         rpmpd: power-controller {
 310                                 compatible = "qcom,msm8996-rpmpd";
 311                                 #power-domain-cells = <1>;
 312                                 operating-points-v2 = <&rpmpd_opp_table>;
 313
 314                                 rpmpd_opp_table: opp-table {
 315                                         compatible = "operating-points-v2";
 316
 317                                         rpmpd_opp1: opp1 {
 318                                                 opp-level = <1>;
 319                                         };
 320
 321                                         rpmpd_opp2: opp2 {
 322                                                 opp-level = <2>;
 323                                         };
 324
 325                                         rpmpd_opp3: opp3 {
 326                                                 opp-level = <3>;
 327                                         };
 328
 329                                         rpmpd_opp4: opp4 {
 330                                                 opp-level = <4>;
 331                                         };
 332
 333                                         rpmpd_opp5: opp5 {
 334                                                 opp-level = <5>;
 335                                         };
 336
 337                                         rpmpd_opp6: opp6 {
 338                                                 opp-level = <6>;
 339                                         };
 340                                 };
 341                         };
 342
 343                         pm8994-regulators {
 344                                 compatible = "qcom,rpm-pm8994-regulators";
 345
 346                                 pm8994_s1: s1 {};
 347                                 pm8994_s2: s2 {};
 348                                 pm8994_s3: s3 {};
 349                                 pm8994_s4: s4 {};
 350                                 pm8994_s5: s5 {};
 351                                 pm8994_s6: s6 {};
 352                                 pm8994_s7: s7 {};
 353                                 pm8994_s8: s8 {};
 354                                 pm8994_s9: s9 {};
 355                                 pm8994_s10: s10 {};
 356                                 pm8994_s11: s11 {};
 357                                 pm8994_s12: s12 {};
 358
 359                                 pm8994_l1: l1 {};
 360                                 pm8994_l2: l2 {};
 361                                 pm8994_l3: l3 {};
 362                                 pm8994_l4: l4 {};
 363                                 pm8994_l5: l5 {};
 364                                 pm8994_l6: l6 {};
 365                                 pm8994_l7: l7 {};
 366                                 pm8994_l8: l8 {};
 367                                 pm8994_l9: l9 {};
 368                                 pm8994_l10: l10 {};
 369                                 pm8994_l11: l11 {};
 370                                 pm8994_l12: l12 {};
 371                                 pm8994_l13: l13 {};
 372                                 pm8994_l14: l14 {};
 373                                 pm8994_l15: l15 {};
 374                                 pm8994_l16: l16 {};
 375                                 pm8994_l17: l17 {};
 376                                 pm8994_l18: l18 {};
 377                                 pm8994_l19: l19 {};
 378                                 pm8994_l20: l20 {};
 379                                 pm8994_l21: l21 {};
 380                                 pm8994_l22: l22 {};
 381                                 pm8994_l23: l23 {};
 382                                 pm8994_l24: l24 {};
 383                                 pm8994_l25: l25 {};
 384                                 pm8994_l26: l26 {};
 385                                 pm8994_l27: l27 {};
 386                                 pm8994_l28: l28 {};
 387                                 pm8994_l29: l29 {};
 388                                 pm8994_l30: l30 {};
 389                                 pm8994_l31: l31 {};
 390                                 pm8994_l32: l32 {};
 391                         };
 392
 393                 };
 394         };
 395
 396         soc: soc {
 397                 #address-cells = <1>;
 398                 #size-cells = <1>;
 399                 ranges = <0 0 0 0xffffffff>;
 400                 compatible = "simple-bus";
 401
 402                 rpm_msg_ram: memory@68000 {
 403                         compatible = "qcom,rpm-msg-ram";
 404                         reg = <0x68000 0x6000>;
 405                 };
 406
 407                 rng: rng@83000 {
 408                         compatible = "qcom,prng-ee";
 409                         reg = <0x00083000 0x1000>;
 410                         clocks = <&gcc GCC_PRNG_AHB_CLK>;
 411                         clock-names = "core";
 412                 };
 413
 414                 tcsr_mutex_regs: syscon@740000 {
 415                         compatible = "syscon";
 416                         reg = <0x740000 0x20000>;
 417                 };
 418
 419                 tsens0: thermal-sensor@4a9000 {
 420                         compatible = "qcom,msm8996-tsens";
 421                         reg = <0x4a9000 0x1000>, /* TM */
 422                               <0x4a8000 0x1000>; /* SROT */
 423                         #qcom,sensors = <13>;
 424                         #thermal-sensor-cells = <1>;
 425                 };
 426
 427                 tsens1: thermal-sensor@4ad000 {
 428                         compatible = "qcom,msm8996-tsens";
 429                         reg = <0x4ad000 0x1000>, /* TM */
 430                               <0x4ac000 0x1000>; /* SROT */
 431                         #qcom,sensors = <8>;
 432                         #thermal-sensor-cells = <1>;
 433                 };
 434
 435                 tcsr: syscon@7a0000 {
 436                         compatible = "qcom,tcsr-msm8996", "syscon";
 437                         reg = <0x7a0000 0x18000>;
 438                 };
 439
 440                 intc: interrupt-controller@9bc0000 {
 441                         compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
 442                         #interrupt-cells = <3>;
 443                         interrupt-controller;
 444                         #redistributor-regions = <1>;
 445                         redistributor-stride = <0x0 0x40000>;
 446                         reg = <0x09bc0000 0x10000>,
 447                               <0x09c00000 0x100000>;
 448                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 449                 };
 450
 451                 apcs_glb: mailbox@9820000 {
 452                         compatible = "qcom,msm8996-apcs-hmss-global";
 453                         reg = <0x9820000 0x1000>;
 454
 455                         #mbox-cells = <1>;
 456                 };
 457
 458                 gcc: clock-controller@300000 {
 459                         compatible = "qcom,gcc-msm8996";
 460                         #clock-cells = <1>;
 461                         #reset-cells = <1>;
 462                         #power-domain-cells = <1>;
 463                         reg = <0x300000 0x90000>;
 464                 };
 465
 466                 kryocc: clock-controller@6400000 {
 467                         compatible = "qcom,apcc-msm8996";
 468                         reg = <0x6400000 0x90000>;
 469                         #clock-cells = <1>;
 470                 };
 471
 472                 blsp1_uart1: serial@7570000 {
 473                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 474                         reg = <0x07570000 0x1000>;
 475                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 476                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 477                                  <&gcc GCC_BLSP1_AHB_CLK>;
 478                         clock-names = "core", "iface";
 479                         status = "disabled";
 480                 };
 481
 482                 blsp1_spi0: spi@7575000 {
 483                         compatible = "qcom,spi-qup-v2.2.1";
 484                         reg = <0x07575000 0x600>;
 485                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 486                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 487                                  <&gcc GCC_BLSP1_AHB_CLK>;
 488                         clock-names = "core", "iface";
 489                         pinctrl-names = "default", "sleep";
 490                         pinctrl-0 = <&blsp1_spi0_default>;
 491                         pinctrl-1 = <&blsp1_spi0_sleep>;
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         status = "disabled";
 495                 };
 496
 497                 blsp2_i2c0: i2c@75b5000 {
 498                         compatible = "qcom,i2c-qup-v2.2.1";
 499                         reg = <0x075b5000 0x1000>;
 500                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 501                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 502                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 503                         clock-names = "iface", "core";
 504                         pinctrl-names = "default", "sleep";
 505                         pinctrl-0 = <&blsp2_i2c0_default>;
 506                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         status = "disabled";
 510                 };
 511
 512                 blsp2_uart1: serial@75b0000 {
 513                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 514                         reg = <0x75b0000 0x1000>;
 515                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 516                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 517                                  <&gcc GCC_BLSP2_AHB_CLK>;
 518                         clock-names = "core", "iface";
 519                         status = "disabled";
 520                 };
 521
 522                 blsp2_i2c1: i2c@75b6000 {
 523                         compatible = "qcom,i2c-qup-v2.2.1";
 524                         reg = <0x075b6000 0x1000>;
 525                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 526                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 527                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 528                         clock-names = "iface", "core";
 529                         pinctrl-names = "default", "sleep";
 530                         pinctrl-0 = <&blsp2_i2c1_default>;
 531                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 532                         #address-cells = <1>;
 533                         #size-cells = <0>;
 534                         status = "disabled";
 535                 };
 536
 537                 blsp2_uart2: serial@75b1000 {
 538                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 539                         reg = <0x075b1000 0x1000>;
 540                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 541                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 542                                  <&gcc GCC_BLSP2_AHB_CLK>;
 543                         clock-names = "core", "iface";
 544                         status = "disabled";
 545                 };
 546
 547                 blsp1_i2c2: i2c@7577000 {
 548                         compatible = "qcom,i2c-qup-v2.2.1";
 549                         reg = <0x07577000 0x1000>;
 550                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 551                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 552                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 553                         clock-names = "iface", "core";
 554                         pinctrl-names = "default", "sleep";
 555                         pinctrl-0 = <&blsp1_i2c2_default>;
 556                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 557                         #address-cells = <1>;
 558                         #size-cells = <0>;
 559                         status = "disabled";
 560                 };
 561
 562                 blsp2_spi5: spi@75ba000{
 563                         compatible = "qcom,spi-qup-v2.2.1";
 564                         reg = <0x075ba000 0x600>;
 565                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 566                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
 567                                  <&gcc GCC_BLSP2_AHB_CLK>;
 568                         clock-names = "core", "iface";
 569                         pinctrl-names = "default", "sleep";
 570                         pinctrl-0 = <&blsp2_spi5_default>;
 571                         pinctrl-1 = <&blsp2_spi5_sleep>;
 572                         #address-cells = <1>;
 573                         #size-cells = <0>;
 574                         status = "disabled";
 575                 };
 576
 577                 sdhc2: sdhci@74a4900 {
 578                          status = "disabled";
 579                          compatible = "qcom,sdhci-msm-v4";
 580                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 581                          reg-names = "hc_mem", "core_mem";
 582
 583                          interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
 584                                       <0 221 IRQ_TYPE_LEVEL_HIGH>;
 585                          interrupt-names = "hc_irq", "pwr_irq";
 586
 587                          clock-names = "iface", "core", "xo";
 588                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 589                          <&gcc GCC_SDCC2_APPS_CLK>,
 590                          <&xo_board>;
 591                          bus-width = <4>;
 592                  };
 593
 594                 msmgpio: pinctrl@1010000 {
 595                         compatible = "qcom,msm8996-pinctrl";
 596                         reg = <0x01010000 0x300000>;
 597                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 598                         gpio-controller;
 599                         #gpio-cells = <2>;
 600                         interrupt-controller;
 601                         #interrupt-cells = <2>;
 602                 };
 603
 604                 timer@9840000 {
 605                         #address-cells = <1>;
 606                         #size-cells = <1>;
 607                         ranges;
 608                         compatible = "arm,armv7-timer-mem";
 609                         reg = <0x09840000 0x1000>;
 610                         clock-frequency = <19200000>;
 611
 612                         frame@9850000 {
 613                                 frame-number = <0>;
 614                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 615                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 616                                 reg = <0x09850000 0x1000>,
 617                                       <0x09860000 0x1000>;
 618                         };
 619
 620                         frame@9870000 {
 621                                 frame-number = <1>;
 622                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 623                                 reg = <0x09870000 0x1000>;
 624                                 status = "disabled";
 625                         };
 626
 627                         frame@9880000 {
 628                                 frame-number = <2>;
 629                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 630                                 reg = <0x09880000 0x1000>;
 631                                 status = "disabled";
 632                         };
 633
 634                         frame@9890000 {
 635                                 frame-number = <3>;
 636                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 637                                 reg = <0x09890000 0x1000>;
 638                                 status = "disabled";
 639                         };
 640
 641                         frame@98a0000 {
 642                                 frame-number = <4>;
 643                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 644                                 reg = <0x098a0000 0x1000>;
 645                                 status = "disabled";
 646                         };
 647
 648                         frame@98b0000 {
 649                                 frame-number = <5>;
 650                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 651                                 reg = <0x098b0000 0x1000>;
 652                                 status = "disabled";
 653                         };
 654
 655                         frame@98c0000 {
 656                                 frame-number = <6>;
 657                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 658                                 reg = <0x098c0000 0x1000>;
 659                                 status = "disabled";
 660                         };
 661                 };
 662
 663                 spmi_bus: qcom,spmi@400f000 {
 664                         compatible = "qcom,spmi-pmic-arb";
 665                         reg = <0x400f000 0x1000>,
 666                               <0x4400000 0x800000>,
 667                               <0x4c00000 0x800000>,
 668                               <0x5800000 0x200000>,
 669                               <0x400a000 0x002100>;
 670                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 671                         interrupt-names = "periph_irq";
 672                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 673                         qcom,ee = <0>;
 674                         qcom,channel = <0>;
 675                         #address-cells = <2>;
 676                         #size-cells = <0>;
 677                         interrupt-controller;
 678                         #interrupt-cells = <4>;
 679                 };
 680
 681                 ufsphy: phy@627000 {
 682                         compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
 683                         reg = <0x627000 0xda8>;
 684                         reg-names = "phy_mem";
 685                         #phy-cells = <0>;
 686
 687                         vdda-phy-supply = <&pm8994_l28>;
 688                         vdda-pll-supply = <&pm8994_l12>;
 689
 690                         vdda-phy-max-microamp = <18380>;
 691                         vdda-pll-max-microamp = <9440>;
 692
 693                         vddp-ref-clk-supply = <&pm8994_l25>;
 694                         vddp-ref-clk-max-microamp = <100>;
 695                         vddp-ref-clk-always-on;
 696
 697                         clock-names = "ref_clk_src", "ref_clk";
 698                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 699                                  <&gcc GCC_UFS_CLKREF_CLK>;
 700                         status = "disabled";
 701                 };
 702
 703                 ufshc@624000 {
 704                         compatible = "qcom,ufshc";
 705                         reg = <0x624000 0x2500>;
 706                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 707
 708                         phys = <&ufsphy>;
 709                         phy-names = "ufsphy";
 710
 711                         vcc-supply = <&pm8994_l20>;
 712                         vccq-supply = <&pm8994_l25>;
 713                         vccq2-supply = <&pm8994_s4>;
 714
 715                         vcc-max-microamp = <600000>;
 716                         vccq-max-microamp = <450000>;
 717                         vccq2-max-microamp = <450000>;
 718
 719                         power-domains = <&gcc UFS_GDSC>;
 720
 721                         clock-names =
 722                                 "core_clk_src",
 723                                 "core_clk",
 724                                 "bus_clk",
 725                                 "bus_aggr_clk",
 726                                 "iface_clk",
 727                                 "core_clk_unipro_src",
 728                                 "core_clk_unipro",
 729                                 "core_clk_ice",
 730                                 "ref_clk",
 731                                 "tx_lane0_sync_clk",
 732                                 "rx_lane0_sync_clk";
 733                         clocks =
 734                                 <&gcc UFS_AXI_CLK_SRC>,
 735                                 <&gcc GCC_UFS_AXI_CLK>,
 736                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
 737                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 738                                 <&gcc GCC_UFS_AHB_CLK>,
 739                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
 740                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 741                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
 742                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
 743                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 744                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
 745                         freq-table-hz =
 746                                 <100000000 200000000>,
 747                                 <0 0>,
 748                                 <0 0>,
 749                                 <0 0>,
 750                                 <0 0>,
 751                                 <150000000 300000000>,
 752                                 <0 0>,
 753                                 <0 0>,
 754                                 <0 0>,
 755                                 <0 0>,
 756                                 <0 0>;
 757
 758                         lanes-per-direction = <1>;
 759                         status = "disabled";
 760
 761                         ufs_variant {
 762                                 compatible = "qcom,ufs_variant";
 763                         };
 764                 };
 765
 766                 mmcc: clock-controller@8c0000 {
 767                         compatible = "qcom,mmcc-msm8996";
 768                         #clock-cells = <1>;
 769                         #reset-cells = <1>;
 770                         #power-domain-cells = <1>;
 771                         reg = <0x8c0000 0x40000>;
 772                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 773                                           <&mmcc MMPLL1_PLL>,
 774                                           <&mmcc MMPLL3_PLL>,
 775                                           <&mmcc MMPLL4_PLL>,
 776                                           <&mmcc MMPLL5_PLL>;
 777                         assigned-clock-rates = <624000000>,
 778                                                <810000000>,
 779                                                <980000000>,
 780                                                <960000000>,
 781                                                <825000000>;
 782                 };
 783
 784                 qfprom@74000 {
 785                         compatible = "qcom,qfprom";
 786                         reg = <0x74000 0x8ff>;
 787                         #address-cells = <1>;
 788                         #size-cells = <1>;
 789
 790                         qusb2p_hstx_trim: hstx_trim@24e {
 791                                 reg = <0x24e 0x2>;
 792                                 bits = <5 4>;
 793                         };
 794
 795                         qusb2s_hstx_trim: hstx_trim@24f {
 796                                 reg = <0x24f 0x1>;
 797                                 bits = <1 4>;
 798                         };
 799                 };
 800
 801                 phy@34000 {
 802                         compatible = "qcom,msm8996-qmp-pcie-phy";
 803                         reg = <0x34000 0x488>;
 804                         #clock-cells = <1>;
 805                         #address-cells = <1>;
 806                         #size-cells = <1>;
 807                         ranges;
 808
 809                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 810                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 811                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 812                         clock-names = "aux", "cfg_ahb", "ref";
 813
 814                         vdda-phy-supply = <&pm8994_l28>;
 815                         vdda-pll-supply = <&pm8994_l12>;
 816
 817                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 818                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 819                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 820                         reset-names = "phy", "common", "cfg";
 821                         status = "disabled";
 822
 823                         pciephy_0: lane@35000 {
 824                                 reg = <0x035000 0x130>,
 825                                         <0x035200 0x200>,
 826                                         <0x035400 0x1dc>;
 827                                 #phy-cells = <0>;
 828
 829                                 clock-output-names = "pcie_0_pipe_clk_src";
 830                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 831                                 clock-names = "pipe0";
 832                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 833                                 reset-names = "lane0";
 834                         };
 835
 836                         pciephy_1: lane@36000 {
 837                                 reg = <0x036000 0x130>,
 838                                         <0x036200 0x200>,
 839                                         <0x036400 0x1dc>;
 840                                 #phy-cells = <0>;
 841
 842                                 clock-output-names = "pcie_1_pipe_clk_src";
 843                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 844                                 clock-names = "pipe1";
 845                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 846                                 reset-names = "lane1";
 847                         };
 848
 849                         pciephy_2: lane@37000 {
 850                                 reg = <0x037000 0x130>,
 851                                         <0x037200 0x200>,
 852                                         <0x037400 0x1dc>;
 853                                 #phy-cells = <0>;
 854
 855                                 clock-output-names = "pcie_2_pipe_clk_src";
 856                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 857                                 clock-names = "pipe2";
 858                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 859                                 reset-names = "lane2";
 860                         };
 861                 };
 862
 863                 phy@7410000 {
 864                         compatible = "qcom,msm8996-qmp-usb3-phy";
 865                         reg = <0x7410000 0x1c4>;
 866                         #clock-cells = <1>;
 867                         #address-cells = <1>;
 868                         #size-cells = <1>;
 869                         ranges;
 870
 871                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 872                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 873                                 <&gcc GCC_USB3_CLKREF_CLK>;
 874                         clock-names = "aux", "cfg_ahb", "ref";
 875
 876                         vdda-phy-supply = <&pm8994_l28>;
 877                         vdda-pll-supply = <&pm8994_l12>;
 878
 879                         resets = <&gcc GCC_USB3_PHY_BCR>,
 880                                 <&gcc GCC_USB3PHY_PHY_BCR>;
 881                         reset-names = "phy", "common";
 882                         status = "disabled";
 883
 884                         ssusb_phy_0: lane@7410200 {
 885                                 reg = <0x7410200 0x200>,
 886                                         <0x7410400 0x130>,
 887                                         <0x7410600 0x1a8>;
 888                                 #phy-cells = <0>;
 889
 890                                 clock-output-names = "usb3_phy_pipe_clk_src";
 891                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 892                                 clock-names = "pipe0";
 893                         };
 894                 };
 895
 896                 hsusb_phy1: phy@7411000 {
 897                         compatible = "qcom,msm8996-qusb2-phy";
 898                         reg = <0x7411000 0x180>;
 899                         #phy-cells = <0>;
 900
 901                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 902                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 903                         clock-names = "cfg_ahb", "ref";
 904
 905                         vdda-pll-supply = <&pm8994_l12>;
 906                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 907
 908                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 909                         nvmem-cells = <&qusb2p_hstx_trim>;
 910                         status = "disabled";
 911                 };
 912
 913                 hsusb_phy2: phy@7412000 {
 914                         compatible = "qcom,msm8996-qusb2-phy";
 915                         reg = <0x7412000 0x180>;
 916                         #phy-cells = <0>;
 917
 918                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 919                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
 920                         clock-names = "cfg_ahb", "ref";
 921
 922                         vdda-pll-supply = <&pm8994_l12>;
 923                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 924
 925                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 926                         nvmem-cells = <&qusb2s_hstx_trim>;
 927                         status = "disabled";
 928                 };
 929
 930                 usb2: usb@76f8800 {
 931                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 932                         reg = <0x76f8800 0x400>;
 933                         #address-cells = <1>;
 934                         #size-cells = <1>;
 935                         ranges;
 936
 937                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
 938                                 <&gcc GCC_USB20_MASTER_CLK>,
 939                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 940                                 <&gcc GCC_USB20_SLEEP_CLK>,
 941                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 942
 943                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 944                                           <&gcc GCC_USB20_MASTER_CLK>;
 945                         assigned-clock-rates = <19200000>, <60000000>;
 946
 947                         power-domains = <&gcc USB30_GDSC>;
 948                         status = "disabled";
 949
 950                         dwc3@7600000 {
 951                                 compatible = "snps,dwc3";
 952                                 reg = <0x7600000 0xcc00>;
 953                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 954                                 phys = <&hsusb_phy2>;
 955                                 phy-names = "usb2-phy";
 956                         };
 957                 };
 958
 959                 usb3: usb@6af8800 {
 960                         compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
 961                         reg = <0x6af8800 0x400>;
 962                         #address-cells = <1>;
 963                         #size-cells = <1>;
 964                         ranges;
 965
 966                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 967                                 <&gcc GCC_USB30_MASTER_CLK>,
 968                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
 969                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 970                                 <&gcc GCC_USB30_SLEEP_CLK>,
 971                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 972
 973                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 974                                           <&gcc GCC_USB30_MASTER_CLK>;
 975                         assigned-clock-rates = <19200000>, <120000000>;
 976
 977                         power-domains = <&gcc USB30_GDSC>;
 978                         status = "disabled";
 979
 980                         dwc3@6a00000 {
 981                                 compatible = "snps,dwc3";
 982                                 reg = <0x6a00000 0xcc00>;
 983                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 984                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 985                                 phy-names = "usb2-phy", "usb3-phy";
 986                         };
 987                 };
 988
 989                 vfe_smmu: arm,smmu@da0000 {
 990                         compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
 991                         reg = <0xda0000 0x10000>;
 992
 993                         #global-interrupts = <1>;
 994                         interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
 995                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
 996                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 997                         power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
 998                         clocks = <&mmcc SMMU_VFE_AHB_CLK>,
 999                                  <&mmcc SMMU_VFE_AXI_CLK>;
1000                         clock-names = "iface",
1001                                       "bus";
1002                         #iommu-cells = <1>;
1003                         status = "disabled";
1004                 };
1005
1006                 camss: camss@a00000 {
1007                         compatible = "qcom,msm8996-camss";
1008                         reg = <0xa34000 0x1000>,
1009                                 <0xa00030 0x4>,
1010                                 <0xa35000 0x1000>,
1011                                 <0xa00038 0x4>,
1012                                 <0xa36000 0x1000>,
1013                                 <0xa00040 0x4>,
1014                                 <0xa30000 0x100>,
1015                                 <0xa30400 0x100>,
1016                                 <0xa30800 0x100>,
1017                                 <0xa30c00 0x100>,
1018                                 <0xa31000 0x500>,
1019                                 <0xa00020 0x10>,
1020                                 <0xa10000 0x1000>,
1021                                 <0xa14000 0x1000>;
1022                         reg-names = "csiphy0",
1023                                 "csiphy0_clk_mux",
1024                                 "csiphy1",
1025                                 "csiphy1_clk_mux",
1026                                 "csiphy2",
1027                                 "csiphy2_clk_mux",
1028                                 "csid0",
1029                                 "csid1",
1030                                 "csid2",
1031                                 "csid3",
1032                                 "ispif",
1033                                 "csi_clk_mux",
1034                                 "vfe0",
1035                                 "vfe1";
1036                         interrupts = <GIC_SPI 78 0>,
1037                                 <GIC_SPI 79 0>,
1038                                 <GIC_SPI 80 0>,
1039                                 <GIC_SPI 296 0>,
1040                                 <GIC_SPI 297 0>,
1041                                 <GIC_SPI 298 0>,
1042                                 <GIC_SPI 299 0>,
1043                                 <GIC_SPI 309 0>,
1044                                 <GIC_SPI 314 0>,
1045                                 <GIC_SPI 315 0>;
1046                         interrupt-names = "csiphy0",
1047                                 "csiphy1",
1048                                 "csiphy2",
1049                                 "csid0",
1050                                 "csid1",
1051                                 "csid2",
1052                                 "csid3",
1053                                 "ispif",
1054                                 "vfe0",
1055                                 "vfe1";
1056                         power-domains = <&mmcc VFE0_GDSC>;
1057                         clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
1058                                 <&mmcc CAMSS_ISPIF_AHB_CLK>,
1059                                 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
1060                                 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
1061                                 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
1062                                 <&mmcc CAMSS_CSI0_AHB_CLK>,
1063                                 <&mmcc CAMSS_CSI0_CLK>,
1064                                 <&mmcc CAMSS_CSI0PHY_CLK>,
1065                                 <&mmcc CAMSS_CSI0PIX_CLK>,
1066                                 <&mmcc CAMSS_CSI0RDI_CLK>,
1067                                 <&mmcc CAMSS_CSI1_AHB_CLK>,
1068                                 <&mmcc CAMSS_CSI1_CLK>,
1069                                 <&mmcc CAMSS_CSI1PHY_CLK>,
1070                                 <&mmcc CAMSS_CSI1PIX_CLK>,
1071                                 <&mmcc CAMSS_CSI1RDI_CLK>,
1072                                 <&mmcc CAMSS_CSI2_AHB_CLK>,
1073                                 <&mmcc CAMSS_CSI2_CLK>,
1074                                 <&mmcc CAMSS_CSI2PHY_CLK>,
1075                                 <&mmcc CAMSS_CSI2PIX_CLK>,
1076                                 <&mmcc CAMSS_CSI2RDI_CLK>,
1077                                 <&mmcc CAMSS_CSI3_AHB_CLK>,
1078                                 <&mmcc CAMSS_CSI3_CLK>,
1079                                 <&mmcc CAMSS_CSI3PHY_CLK>,
1080                                 <&mmcc CAMSS_CSI3PIX_CLK>,
1081                                 <&mmcc CAMSS_CSI3RDI_CLK>,
1082                                 <&mmcc CAMSS_AHB_CLK>,
1083                                 <&mmcc CAMSS_VFE0_CLK>,
1084                                 <&mmcc CAMSS_CSI_VFE0_CLK>,
1085                                 <&mmcc CAMSS_VFE0_AHB_CLK>,
1086                                 <&mmcc CAMSS_VFE0_STREAM_CLK>,
1087                                 <&mmcc CAMSS_VFE1_CLK>,
1088                                 <&mmcc CAMSS_CSI_VFE1_CLK>,
1089                                 <&mmcc CAMSS_VFE1_AHB_CLK>,
1090                                 <&mmcc CAMSS_VFE1_STREAM_CLK>,
1091                                 <&mmcc CAMSS_VFE_AHB_CLK>,
1092                                 <&mmcc CAMSS_VFE_AXI_CLK>;
1093                         clock-names = "top_ahb",
1094                                 "ispif_ahb",
1095                                 "csiphy0_timer",
1096                                 "csiphy1_timer",
1097                                 "csiphy2_timer",
1098                                 "csi0_ahb",
1099                                 "csi0",
1100                                 "csi0_phy",
1101                                 "csi0_pix",
1102                                 "csi0_rdi",
1103                                 "csi1_ahb",
1104                                 "csi1",
1105                                 "csi1_phy",
1106                                 "csi1_pix",
1107                                 "csi1_rdi",
1108                                 "csi2_ahb",
1109                                 "csi2",
1110                                 "csi2_phy",
1111                                 "csi2_pix",
1112                                 "csi2_rdi",
1113                                 "csi3_ahb",
1114                                 "csi3",
1115                                 "csi3_phy",
1116                                 "csi3_pix",
1117                                 "csi3_rdi",
1118                                 "ahb",
1119                                 "vfe0",
1120                                 "csi_vfe0",
1121                                 "vfe0_ahb",
1122                                 "vfe0_stream",
1123                                 "vfe1",
1124                                 "csi_vfe1",
1125                                 "vfe1_ahb",
1126                                 "vfe1_stream",
1127                                 "vfe_ahb",
1128                                 "vfe_axi";
1129                         vdda-supply = <&pm8994_l2>;
1130                         iommus = <&vfe_smmu 0>,
1131                                  <&vfe_smmu 1>,
1132                                  <&vfe_smmu 2>,
1133                                  <&vfe_smmu 3>;
1134                         status = "disabled";
1135                         ports {
1136                                 #address-cells = <1>;
1137                                 #size-cells = <0>;
1138                         };
1139                 };
1140
1141                 agnoc@0 {
1142                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
1143                         compatible = "simple-pm-bus";
1144                         #address-cells = <1>;
1145                         #size-cells = <1>;
1146                         ranges;
1147
1148                         pcie0: pcie@600000 {
1149                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1150                                 status = "disabled";
1151                                 power-domains = <&gcc PCIE0_GDSC>;
1152                                 bus-range = <0x00 0xff>;
1153                                 num-lanes = <1>;
1154
1155                                 reg = <0x00600000 0x2000>,
1156                                       <0x0c000000 0xf1d>,
1157                                       <0x0c000f20 0xa8>,
1158                                       <0x0c100000 0x100000>;
1159                                 reg-names = "parf", "dbi", "elbi","config";
1160
1161                                 phys = <&pciephy_0>;
1162                                 phy-names = "pciephy";
1163
1164                                 #address-cells = <3>;
1165                                 #size-cells = <2>;
1166                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
1167                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
1168
1169                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
1170                                 interrupt-names = "msi";
1171                                 #interrupt-cells = <1>;
1172                                 interrupt-map-mask = <0 0 0 0x7>;
1173                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1174                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1175                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1176                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1177
1178                                 pinctrl-names = "default", "sleep";
1179                                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
1180                                 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
1181
1182
1183                                 vdda-supply = <&pm8994_l28>;
1184
1185                                 linux,pci-domain = <0>;
1186
1187                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
1188                                         <&gcc GCC_PCIE_0_AUX_CLK>,
1189                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1190                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1191                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1192
1193                                 clock-names =  "pipe",
1194                                                 "aux",
1195                                                 "cfg",
1196                                                 "bus_master",
1197                                                 "bus_slave";
1198
1199                         };
1200
1201                         pcie1: pcie@608000 {
1202                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1203                                 power-domains = <&gcc PCIE1_GDSC>;
1204                                 bus-range = <0x00 0xff>;
1205                                 num-lanes = <1>;
1206
1207                                 status  = "disabled";
1208
1209                                 reg = <0x00608000 0x2000>,
1210                                       <0x0d000000 0xf1d>,
1211                                       <0x0d000f20 0xa8>,
1212                                       <0x0d100000 0x100000>;
1213
1214                                 reg-names = "parf", "dbi", "elbi","config";
1215
1216                                 phys = <&pciephy_1>;
1217                                 phy-names = "pciephy";
1218
1219                                 #address-cells = <3>;
1220                                 #size-cells = <2>;
1221                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1222                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1223
1224                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1225                                 interrupt-names = "msi";
1226                                 #interrupt-cells = <1>;
1227                                 interrupt-map-mask = <0 0 0 0x7>;
1228                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1229                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1230                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1231                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1232
1233                                 pinctrl-names = "default", "sleep";
1234                                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1235                                 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1236
1237
1238                                 vdda-supply = <&pm8994_l28>;
1239                                 linux,pci-domain = <1>;
1240
1241                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1242                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1243                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1244                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1245                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1246
1247                                 clock-names =  "pipe",
1248                                                 "aux",
1249                                                 "cfg",
1250                                                 "bus_master",
1251                                                 "bus_slave";
1252                         };
1253
1254                         pcie2: pcie@610000 {
1255                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1256                                 power-domains = <&gcc PCIE2_GDSC>;
1257                                 bus-range = <0x00 0xff>;
1258                                 num-lanes = <1>;
1259                                 status = "disabled";
1260                                 reg = <0x00610000 0x2000>,
1261                                       <0x0e000000 0xf1d>,
1262                                       <0x0e000f20 0xa8>,
1263                                       <0x0e100000 0x100000>;
1264
1265                                 reg-names = "parf", "dbi", "elbi","config";
1266
1267                                 phys = <&pciephy_2>;
1268                                 phy-names = "pciephy";
1269
1270                                 #address-cells = <3>;
1271                                 #size-cells = <2>;
1272                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1273                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1274
1275                                 device_type = "pci";
1276
1277                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1278                                 interrupt-names = "msi";
1279                                 #interrupt-cells = <1>;
1280                                 interrupt-map-mask = <0 0 0 0x7>;
1281                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1282                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1283                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1284                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1285
1286                                 pinctrl-names = "default", "sleep";
1287                                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1288                                 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1289
1290                                 vdda-supply = <&pm8994_l28>;
1291
1292                                 linux,pci-domain = <2>;
1293                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1294                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1295                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1296                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1297                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1298
1299                                 clock-names =  "pipe",
1300                                                 "aux",
1301                                                 "cfg",
1302                                                 "bus_master",
1303                                                 "bus_slave";
1304                         };
1305                 };
1306         };
1307
1308         adsp-pil {
1309                 compatible = "qcom,msm8996-adsp-pil";
1310
1311                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1312                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1313                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1314                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1315                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1316                 interrupt-names = "wdog", "fatal", "ready",
1317                                   "handover", "stop-ack";
1318
1319                 clocks = <&xo_board>;
1320                 clock-names = "xo";
1321
1322                 memory-region = <&adsp_region>;
1323
1324                 qcom,smem-states = <&adsp_smp2p_out 0>;
1325                 qcom,smem-state-names = "stop";
1326
1327                 smd-edge {
1328                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1329
1330                         label = "lpass";
1331                         mboxes = <&apcs_glb 8>;
1332                         qcom,smd-edge = <1>;
1333                         qcom,remote-pid = <2>;
1334                 };
1335         };
1336
1337         adsp-smp2p {
1338                 compatible = "qcom,smp2p";
1339                 qcom,smem = <443>, <429>;
1340
1341                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1342
1343                 mboxes = <&apcs_glb 10>;
1344
1345                 qcom,local-pid = <0>;
1346                 qcom,remote-pid = <2>;
1347
1348                 adsp_smp2p_out: master-kernel {
1349                         qcom,entry-name = "master-kernel";
1350                         #qcom,smem-state-cells = <1>;
1351                 };
1352
1353                 adsp_smp2p_in: slave-kernel {
1354                         qcom,entry-name = "slave-kernel";
1355
1356                         interrupt-controller;
1357                         #interrupt-cells = <2>;
1358                 };
1359         };
1360
1361         modem-smp2p {
1362                 compatible = "qcom,smp2p";
1363                 qcom,smem = <435>, <428>;
1364
1365                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1366
1367                 mboxes = <&apcs_glb 14>;
1368
1369                 qcom,local-pid = <0>;
1370                 qcom,remote-pid = <1>;
1371
1372                 modem_smp2p_out: master-kernel {
1373                         qcom,entry-name = "master-kernel";
1374                         #qcom,smem-state-cells = <1>;
1375                 };
1376
1377                 modem_smp2p_in: slave-kernel {
1378                         qcom,entry-name = "slave-kernel";
1379
1380                         interrupt-controller;
1381                         #interrupt-cells = <2>;
1382                 };
1383         };
1384
1385         smp2p-slpi {
1386                 compatible = "qcom,smp2p";
1387                 qcom,smem = <481>, <430>;
1388
1389                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1390
1391                 mboxes = <&apcs_glb 26>;
1392
1393                 qcom,local-pid = <0>;
1394                 qcom,remote-pid = <3>;
1395
1396                 slpi_smp2p_in: slave-kernel {
1397                         qcom,entry-name = "slave-kernel";
1398                         interrupt-controller;
1399                         #interrupt-cells = <2>;
1400                 };
1401
1402                 slpi_smp2p_out: master-kernel {
1403                         qcom,entry-name = "master-kernel";
1404                         #qcom,smem-state-cells = <1>;
1405                 };
1406         };
1407
1408 };
1409 #include "msm8996-pins.dtsi"