arch/arm64/boot/dts/qcom/msm8996.dtsi

   1 /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <dt-bindings/interrupt-controller/arm-gic.h>
  14 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
  15 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
  16 #include <dt-bindings/clock/qcom,rpmcc.h>
  17
  18 / {
  19         model = "Qualcomm Technologies, Inc. MSM8996";
  20
  21         interrupt-parent = <&intc>;
  22
  23         #address-cells = <2>;
  24         #size-cells = <2>;
  25
  26         chosen { };
  27
  28         memory {
  29                 device_type = "memory";
  30                 /* We expect the bootloader to fill in the reg */
  31                 reg = <0 0 0 0>;
  32         };
  33
  34         reserved-memory {
  35                 #address-cells = <2>;
  36                 #size-cells = <2>;
  37                 ranges;
  38
  39                 mba_region: mba@91500000 {
  40                         reg = <0x0 0x91500000 0x0 0x200000>;
  41                         no-map;
  42                 };
  43
  44                 slpi_region: slpi@90b00000 {
  45                         reg = <0x0 0x90b00000 0x0 0xa00000>;
  46                         no-map;
  47                 };
  48
  49                 venus_region: venus@90400000 {
  50                         reg = <0x0 0x90400000 0x0 0x700000>;
  51                         no-map;
  52                 };
  53
  54                 adsp_region: adsp@8ea00000 {
  55                         reg = <0x0 0x8ea00000 0x0 0x1a00000>;
  56                         no-map;
  57                 };
  58
  59                 mpss_region: mpss@88800000 {
  60                         reg = <0x0 0x88800000 0x0 0x6200000>;
  61                         no-map;
  62                 };
  63
  64                 smem_mem: smem-mem@86000000 {
  65                         reg = <0x0 0x86000000 0x0 0x200000>;
  66                         no-map;
  67                 };
  68
  69                 memory@85800000 {
  70                         reg = <0x0 0x85800000 0x0 0x800000>;
  71                         no-map;
  72                 };
  73
  74                 memory@86200000 {
  75                         reg = <0x0 0x86200000 0x0 0x2600000>;
  76                         no-map;
  77                 };
  78
  79                 rmtfs@86700000 {
  80                         compatible = "qcom,rmtfs-mem";
  81
  82                         size = <0x0 0x200000>;
  83                         alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
  84                         no-map;
  85
  86                         qcom,client-id = <1>;
  87                         qcom,vmid = <15>;
  88                 };
  89         };
  90
  91         cpus {
  92                 #address-cells = <2>;
  93                 #size-cells = <0>;
  94
  95                 CPU0: cpu@0 {
  96                         device_type = "cpu";
  97                         compatible = "qcom,kryo";
  98                         reg = <0x0 0x0>;
  99                         enable-method = "psci";
 100                         next-level-cache = <&L2_0>;
 101                         L2_0: l2-cache {
 102                               compatible = "cache";
 103                               cache-level = <2>;
 104                         };
 105                 };
 106
 107                 CPU1: cpu@1 {
 108                         device_type = "cpu";
 109                         compatible = "qcom,kryo";
 110                         reg = <0x0 0x1>;
 111                         enable-method = "psci";
 112                         next-level-cache = <&L2_0>;
 113                 };
 114
 115                 CPU2: cpu@100 {
 116                         device_type = "cpu";
 117                         compatible = "qcom,kryo";
 118                         reg = <0x0 0x100>;
 119                         enable-method = "psci";
 120                         next-level-cache = <&L2_1>;
 121                         L2_1: l2-cache {
 122                               compatible = "cache";
 123                               cache-level = <2>;
 124                         };
 125                 };
 126
 127                 CPU3: cpu@101 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo";
 130                         reg = <0x0 0x101>;
 131                         enable-method = "psci";
 132                         next-level-cache = <&L2_1>;
 133                 };
 134
 135                 cpu-map {
 136                         cluster0 {
 137                                 core0 {
 138                                         cpu = <&CPU0>;
 139                                 };
 140
 141                                 core1 {
 142                                         cpu = <&CPU1>;
 143                                 };
 144                         };
 145
 146                         cluster1 {
 147                                 core0 {
 148                                         cpu = <&CPU2>;
 149                                 };
 150
 151                                 core1 {
 152                                         cpu = <&CPU3>;
 153                                 };
 154                         };
 155                 };
 156         };
 157
 158         thermal-zones {
 159                 cpu-thermal0 {
 160                         polling-delay-passive = <250>;
 161                         polling-delay = <1000>;
 162
 163                         thermal-sensors = <&tsens0 3>;
 164
 165                         trips {
 166                                 cpu_alert0: trip0 {
 167                                         temperature = <75000>;
 168                                         hysteresis = <2000>;
 169                                         type = "passive";
 170                                 };
 171
 172                                 cpu_crit0: trip1 {
 173                                         temperature = <110000>;
 174                                         hysteresis = <2000>;
 175                                         type = "critical";
 176                                 };
 177                         };
 178                 };
 179
 180                 cpu-thermal1 {
 181                         polling-delay-passive = <250>;
 182                         polling-delay = <1000>;
 183
 184                         thermal-sensors = <&tsens0 5>;
 185
 186                         trips {
 187                                 cpu_alert1: trip0 {
 188                                         temperature = <75000>;
 189                                         hysteresis = <2000>;
 190                                         type = "passive";
 191                                 };
 192
 193                                 cpu_crit1: trip1 {
 194                                         temperature = <110000>;
 195                                         hysteresis = <2000>;
 196                                         type = "critical";
 197                                 };
 198                         };
 199                 };
 200
 201                 cpu-thermal2 {
 202                         polling-delay-passive = <250>;
 203                         polling-delay = <1000>;
 204
 205                         thermal-sensors = <&tsens0 8>;
 206
 207                         trips {
 208                                 cpu_alert2: trip0 {
 209                                         temperature = <75000>;
 210                                         hysteresis = <2000>;
 211                                         type = "passive";
 212                                 };
 213
 214                                 cpu_crit2: trip1 {
 215                                         temperature = <110000>;
 216                                         hysteresis = <2000>;
 217                                         type = "critical";
 218                                 };
 219                         };
 220                 };
 221
 222                 cpu-thermal3 {
 223                         polling-delay-passive = <250>;
 224                         polling-delay = <1000>;
 225
 226                         thermal-sensors = <&tsens0 10>;
 227
 228                         trips {
 229                                 cpu_alert3: trip0 {
 230                                         temperature = <75000>;
 231                                         hysteresis = <2000>;
 232                                         type = "passive";
 233                                 };
 234
 235                                 cpu_crit3: trip1 {
 236                                         temperature = <110000>;
 237                                         hysteresis = <2000>;
 238                                         type = "critical";
 239                                 };
 240                         };
 241                 };
 242         };
 243
 244         timer {
 245                 compatible = "arm,armv8-timer";
 246                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 247                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 248                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 249                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 250         };
 251
 252         clocks {
 253                 xo_board: xo_board {
 254                         compatible = "fixed-clock";
 255                         #clock-cells = <0>;
 256                         clock-frequency = <19200000>;
 257                         clock-output-names = "xo_board";
 258                 };
 259
 260                 sleep_clk: sleep_clk {
 261                         compatible = "fixed-clock";
 262                         #clock-cells = <0>;
 263                         clock-frequency = <32764>;
 264                         clock-output-names = "sleep_clk";
 265                 };
 266         };
 267
 268         psci {
 269                 compatible = "arm,psci-1.0";
 270                 method = "smc";
 271         };
 272
 273         firmware {
 274                 scm {
 275                         compatible = "qcom,scm-msm8996";
 276
 277                         qcom,dload-mode = <&tcsr 0x13000>;
 278                 };
 279         };
 280
 281         tcsr_mutex: hwlock {
 282                 compatible = "qcom,tcsr-mutex";
 283                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 284                 #hwlock-cells = <1>;
 285         };
 286
 287         smem {
 288                 compatible = "qcom,smem";
 289                 memory-region = <&smem_mem>;
 290                 hwlocks = <&tcsr_mutex 3>;
 291         };
 292
 293         rpm-glink {
 294                 compatible = "qcom,glink-rpm";
 295
 296                 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
 297
 298                 qcom,rpm-msg-ram = <&rpm_msg_ram>;
 299
 300                 mboxes = <&apcs_glb 0>;
 301
 302                 rpm_requests {
 303                         compatible = "qcom,rpm-msm8996";
 304                         qcom,glink-channels = "rpm_requests";
 305
 306                         rpmcc: qcom,rpmcc {
 307                                 compatible = "qcom,rpmcc-msm8996";
 308                                 #clock-cells = <1>;
 309                         };
 310
 311                         pm8994-regulators {
 312                                 compatible = "qcom,rpm-pm8994-regulators";
 313
 314                                 pm8994_s1: s1 {};
 315                                 pm8994_s2: s2 {};
 316                                 pm8994_s3: s3 {};
 317                                 pm8994_s4: s4 {};
 318                                 pm8994_s5: s5 {};
 319                                 pm8994_s6: s6 {};
 320                                 pm8994_s7: s7 {};
 321                                 pm8994_s8: s8 {};
 322                                 pm8994_s9: s9 {};
 323                                 pm8994_s10: s10 {};
 324                                 pm8994_s11: s11 {};
 325                                 pm8994_s12: s12 {};
 326
 327                                 pm8994_l1: l1 {};
 328                                 pm8994_l2: l2 {};
 329                                 pm8994_l3: l3 {};
 330                                 pm8994_l4: l4 {};
 331                                 pm8994_l5: l5 {};
 332                                 pm8994_l6: l6 {};
 333                                 pm8994_l7: l7 {};
 334                                 pm8994_l8: l8 {};
 335                                 pm8994_l9: l9 {};
 336                                 pm8994_l10: l10 {};
 337                                 pm8994_l11: l11 {};
 338                                 pm8994_l12: l12 {};
 339                                 pm8994_l13: l13 {};
 340                                 pm8994_l14: l14 {};
 341                                 pm8994_l15: l15 {};
 342                                 pm8994_l16: l16 {};
 343                                 pm8994_l17: l17 {};
 344                                 pm8994_l18: l18 {};
 345                                 pm8994_l19: l19 {};
 346                                 pm8994_l20: l20 {};
 347                                 pm8994_l21: l21 {};
 348                                 pm8994_l22: l22 {};
 349                                 pm8994_l23: l23 {};
 350                                 pm8994_l24: l24 {};
 351                                 pm8994_l25: l25 {};
 352                                 pm8994_l26: l26 {};
 353                                 pm8994_l27: l27 {};
 354                                 pm8994_l28: l28 {};
 355                                 pm8994_l29: l29 {};
 356                                 pm8994_l30: l30 {};
 357                                 pm8994_l31: l31 {};
 358                                 pm8994_l32: l32 {};
 359                         };
 360
 361                 };
 362         };
 363
 364         soc: soc {
 365                 #address-cells = <1>;
 366                 #size-cells = <1>;
 367                 ranges = <0 0 0 0xffffffff>;
 368                 compatible = "simple-bus";
 369
 370                 rpm_msg_ram: memory@68000 {
 371                         compatible = "qcom,rpm-msg-ram";
 372                         reg = <0x68000 0x6000>;
 373                 };
 374
 375                 tcsr_mutex_regs: syscon@740000 {
 376                         compatible = "syscon";
 377                         reg = <0x740000 0x20000>;
 378                 };
 379
 380                 tcsr: syscon@7a0000 {
 381                         compatible = "qcom,tcsr-msm8996", "syscon";
 382                         reg = <0x7a0000 0x18000>;
 383                 };
 384
 385                 intc: interrupt-controller@9bc0000 {
 386                         compatible = "arm,gic-v3";
 387                         #interrupt-cells = <3>;
 388                         interrupt-controller;
 389                         #redistributor-regions = <1>;
 390                         redistributor-stride = <0x0 0x40000>;
 391                         reg = <0x09bc0000 0x10000>,
 392                               <0x09c00000 0x100000>;
 393                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 394                 };
 395
 396                 apcs: syscon@9820000 {
 397                         compatible = "syscon";
 398                         reg = <0x9820000 0x1000>;
 399                 };
 400
 401                 apcs_glb: mailbox@9820000 {
 402                         compatible = "qcom,msm8996-apcs-hmss-global";
 403                         reg = <0x9820000 0x1000>;
 404
 405                         #mbox-cells = <1>;
 406                 };
 407
 408                 gcc: clock-controller@300000 {
 409                         compatible = "qcom,gcc-msm8996";
 410                         #clock-cells = <1>;
 411                         #reset-cells = <1>;
 412                         #power-domain-cells = <1>;
 413                         reg = <0x300000 0x90000>;
 414                 };
 415
 416                 kryocc: clock-controller@6400000 {
 417                         compatible = "qcom,apcc-msm8996";
 418                         reg = <0x6400000 0x90000>;
 419                         #clock-cells = <1>;
 420                 };
 421
 422                 blsp1_uart1: serial@7570000 {
 423                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 424                         reg = <0x07570000 0x1000>;
 425                         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 426                         clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
 427                                  <&gcc GCC_BLSP1_AHB_CLK>;
 428                         clock-names = "core", "iface";
 429                         status = "disabled";
 430                 };
 431
 432                 blsp1_spi0: spi@7575000 {
 433                         compatible = "qcom,spi-qup-v2.2.1";
 434                         reg = <0x07575000 0x600>;
 435                         interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
 436                         clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
 437                                  <&gcc GCC_BLSP1_AHB_CLK>;
 438                         clock-names = "core", "iface";
 439                         pinctrl-names = "default", "sleep";
 440                         pinctrl-0 = <&blsp1_spi0_default>;
 441                         pinctrl-1 = <&blsp1_spi0_sleep>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         status = "disabled";
 445                 };
 446
 447                 blsp2_i2c0: i2c@75b5000 {
 448                         compatible = "qcom,i2c-qup-v2.2.1";
 449                         reg = <0x075b5000 0x1000>;
 450                         interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 451                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 452                                 <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
 453                         clock-names = "iface", "core";
 454                         pinctrl-names = "default", "sleep";
 455                         pinctrl-0 = <&blsp2_i2c0_default>;
 456                         pinctrl-1 = <&blsp2_i2c0_sleep>;
 457                         #address-cells = <1>;
 458                         #size-cells = <0>;
 459                         status = "disabled";
 460                 };
 461
 462                 tsens0: thermal-sensor@4a8000 {
 463                         compatible = "qcom,msm8996-tsens";
 464                         reg = <0x4a8000 0x2000>;
 465                         #thermal-sensor-cells = <1>;
 466                 };
 467
 468                 blsp2_uart1: serial@75b0000 {
 469                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 470                         reg = <0x75b0000 0x1000>;
 471                         interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 472                         clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>,
 473                                  <&gcc GCC_BLSP2_AHB_CLK>;
 474                         clock-names = "core", "iface";
 475                         status = "disabled";
 476                 };
 477
 478                 blsp2_i2c1: i2c@75b6000 {
 479                         compatible = "qcom,i2c-qup-v2.2.1";
 480                         reg = <0x075b6000 0x1000>;
 481                         interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
 482                         clocks = <&gcc GCC_BLSP2_AHB_CLK>,
 483                                 <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
 484                         clock-names = "iface", "core";
 485                         pinctrl-names = "default", "sleep";
 486                         pinctrl-0 = <&blsp2_i2c1_default>;
 487                         pinctrl-1 = <&blsp2_i2c1_sleep>;
 488                         #address-cells = <1>;
 489                         #size-cells = <0>;
 490                         status = "disabled";
 491                 };
 492
 493                 blsp2_uart2: serial@75b1000 {
 494                         compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
 495                         reg = <0x075b1000 0x1000>;
 496                         interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 497                         clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>,
 498                                  <&gcc GCC_BLSP2_AHB_CLK>;
 499                         clock-names = "core", "iface";
 500                         status = "disabled";
 501                 };
 502
 503                 blsp1_i2c2: i2c@7577000 {
 504                         compatible = "qcom,i2c-qup-v2.2.1";
 505                         reg = <0x07577000 0x1000>;
 506                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 507                         clocks = <&gcc GCC_BLSP1_AHB_CLK>,
 508                                 <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
 509                         clock-names = "iface", "core";
 510                         pinctrl-names = "default", "sleep";
 511                         pinctrl-0 = <&blsp1_i2c2_default>;
 512                         pinctrl-1 = <&blsp1_i2c2_sleep>;
 513                         #address-cells = <1>;
 514                         #size-cells = <0>;
 515                         status = "disabled";
 516                 };
 517
 518                 blsp2_spi5: spi@75ba000{
 519                         compatible = "qcom,spi-qup-v2.2.1";
 520                         reg = <0x075ba000 0x600>;
 521                         interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
 522                         clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>,
 523                                  <&gcc GCC_BLSP2_AHB_CLK>;
 524                         clock-names = "core", "iface";
 525                         pinctrl-names = "default", "sleep";
 526                         pinctrl-0 = <&blsp2_spi5_default>;
 527                         pinctrl-1 = <&blsp2_spi5_sleep>;
 528                         #address-cells = <1>;
 529                         #size-cells = <0>;
 530                         status = "disabled";
 531                 };
 532
 533                 sdhc2: sdhci@74a4900 {
 534                          status = "disabled";
 535                          compatible = "qcom,sdhci-msm-v4";
 536                          reg = <0x74a4900 0x314>, <0x74a4000 0x800>;
 537                          reg-names = "hc_mem", "core_mem";
 538
 539                          interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>,
 540                                       <0 221 IRQ_TYPE_LEVEL_HIGH>;
 541                          interrupt-names = "hc_irq", "pwr_irq";
 542
 543                          clock-names = "iface", "core", "xo";
 544                          clocks = <&gcc GCC_SDCC2_AHB_CLK>,
 545                          <&gcc GCC_SDCC2_APPS_CLK>,
 546                          <&xo_board>;
 547                          bus-width = <4>;
 548                  };
 549
 550                 msmgpio: pinctrl@1010000 {
 551                         compatible = "qcom,msm8996-pinctrl";
 552                         reg = <0x01010000 0x300000>;
 553                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 554                         gpio-controller;
 555                         #gpio-cells = <2>;
 556                         interrupt-controller;
 557                         #interrupt-cells = <2>;
 558                 };
 559
 560                 timer@9840000 {
 561                         #address-cells = <1>;
 562                         #size-cells = <1>;
 563                         ranges;
 564                         compatible = "arm,armv7-timer-mem";
 565                         reg = <0x09840000 0x1000>;
 566                         clock-frequency = <19200000>;
 567
 568                         frame@9850000 {
 569                                 frame-number = <0>;
 570                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
 571                                              <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 572                                 reg = <0x09850000 0x1000>,
 573                                       <0x09860000 0x1000>;
 574                         };
 575
 576                         frame@9870000 {
 577                                 frame-number = <1>;
 578                                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 579                                 reg = <0x09870000 0x1000>;
 580                                 status = "disabled";
 581                         };
 582
 583                         frame@9880000 {
 584                                 frame-number = <2>;
 585                                 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 586                                 reg = <0x09880000 0x1000>;
 587                                 status = "disabled";
 588                         };
 589
 590                         frame@9890000 {
 591                                 frame-number = <3>;
 592                                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 593                                 reg = <0x09890000 0x1000>;
 594                                 status = "disabled";
 595                         };
 596
 597                         frame@98a0000 {
 598                                 frame-number = <4>;
 599                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 600                                 reg = <0x098a0000 0x1000>;
 601                                 status = "disabled";
 602                         };
 603
 604                         frame@98b0000 {
 605                                 frame-number = <5>;
 606                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 607                                 reg = <0x098b0000 0x1000>;
 608                                 status = "disabled";
 609                         };
 610
 611                         frame@98c0000 {
 612                                 frame-number = <6>;
 613                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 614                                 reg = <0x098c0000 0x1000>;
 615                                 status = "disabled";
 616                         };
 617                 };
 618
 619                 spmi_bus: qcom,spmi@400f000 {
 620                         compatible = "qcom,spmi-pmic-arb";
 621                         reg = <0x400f000 0x1000>,
 622                               <0x4400000 0x800000>,
 623                               <0x4c00000 0x800000>,
 624                               <0x5800000 0x200000>,
 625                               <0x400a000 0x002100>;
 626                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 627                         interrupt-names = "periph_irq";
 628                         interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
 629                         qcom,ee = <0>;
 630                         qcom,channel = <0>;
 631                         #address-cells = <2>;
 632                         #size-cells = <0>;
 633                         interrupt-controller;
 634                         #interrupt-cells = <4>;
 635                 };
 636
 637                 ufsphy: phy@627000 {
 638                         compatible = "qcom,msm8996-ufs-phy-qmp-14nm";
 639                         reg = <0x627000 0xda8>;
 640                         reg-names = "phy_mem";
 641                         #phy-cells = <0>;
 642
 643                         vdda-phy-supply = <&pm8994_l28>;
 644                         vdda-pll-supply = <&pm8994_l12>;
 645
 646                         vdda-phy-max-microamp = <18380>;
 647                         vdda-pll-max-microamp = <9440>;
 648
 649                         vddp-ref-clk-supply = <&pm8994_l25>;
 650                         vddp-ref-clk-max-microamp = <100>;
 651                         vddp-ref-clk-always-on;
 652
 653                         clock-names = "ref_clk_src", "ref_clk";
 654                         clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
 655                                  <&gcc GCC_UFS_CLKREF_CLK>;
 656                         status = "disabled";
 657                 };
 658
 659                 ufshc@624000 {
 660                         compatible = "qcom,ufshc";
 661                         reg = <0x624000 0x2500>;
 662                         interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
 663
 664                         phys = <&ufsphy>;
 665                         phy-names = "ufsphy";
 666
 667                         vcc-supply = <&pm8994_l20>;
 668                         vccq-supply = <&pm8994_l25>;
 669                         vccq2-supply = <&pm8994_s4>;
 670
 671                         vcc-max-microamp = <600000>;
 672                         vccq-max-microamp = <450000>;
 673                         vccq2-max-microamp = <450000>;
 674
 675                         power-domains = <&gcc UFS_GDSC>;
 676
 677                         clock-names =
 678                                 "core_clk_src",
 679                                 "core_clk",
 680                                 "bus_clk",
 681                                 "bus_aggr_clk",
 682                                 "iface_clk",
 683                                 "core_clk_unipro_src",
 684                                 "core_clk_unipro",
 685                                 "core_clk_ice",
 686                                 "ref_clk",
 687                                 "tx_lane0_sync_clk",
 688                                 "rx_lane0_sync_clk";
 689                         clocks =
 690                                 <&gcc UFS_AXI_CLK_SRC>,
 691                                 <&gcc GCC_UFS_AXI_CLK>,
 692                                 <&gcc GCC_SYS_NOC_UFS_AXI_CLK>,
 693                                 <&gcc GCC_AGGRE2_UFS_AXI_CLK>,
 694                                 <&gcc GCC_UFS_AHB_CLK>,
 695                                 <&gcc UFS_ICE_CORE_CLK_SRC>,
 696                                 <&gcc GCC_UFS_UNIPRO_CORE_CLK>,
 697                                 <&gcc GCC_UFS_ICE_CORE_CLK>,
 698                                 <&rpmcc RPM_SMD_LN_BB_CLK>,
 699                                 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>,
 700                                 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>;
 701                         freq-table-hz =
 702                                 <100000000 200000000>,
 703                                 <0 0>,
 704                                 <0 0>,
 705                                 <0 0>,
 706                                 <0 0>,
 707                                 <150000000 300000000>,
 708                                 <0 0>,
 709                                 <0 0>,
 710                                 <0 0>,
 711                                 <0 0>,
 712                                 <0 0>;
 713
 714                         lanes-per-direction = <1>;
 715                         status = "disabled";
 716
 717                         ufs_variant {
 718                                 compatible = "qcom,ufs_variant";
 719                         };
 720                 };
 721
 722                 mmcc: clock-controller@8c0000 {
 723                         compatible = "qcom,mmcc-msm8996";
 724                         #clock-cells = <1>;
 725                         #reset-cells = <1>;
 726                         #power-domain-cells = <1>;
 727                         reg = <0x8c0000 0x40000>;
 728                         assigned-clocks = <&mmcc MMPLL9_PLL>,
 729                                           <&mmcc MMPLL1_PLL>,
 730                                           <&mmcc MMPLL3_PLL>,
 731                                           <&mmcc MMPLL4_PLL>,
 732                                           <&mmcc MMPLL5_PLL>;
 733                         assigned-clock-rates = <624000000>,
 734                                                <810000000>,
 735                                                <980000000>,
 736                                                <960000000>,
 737                                                <825000000>;
 738                 };
 739
 740                 qfprom@74000 {
 741                         compatible = "qcom,qfprom";
 742                         reg = <0x74000 0x8ff>;
 743                         #address-cells = <1>;
 744                         #size-cells = <1>;
 745
 746                         qusb2p_hstx_trim: hstx_trim@24e {
 747                                 reg = <0x24e 0x2>;
 748                                 bits = <5 4>;
 749                         };
 750
 751                         qusb2s_hstx_trim: hstx_trim@24f {
 752                                 reg = <0x24f 0x1>;
 753                                 bits = <1 4>;
 754                         };
 755                 };
 756
 757                 phy@34000 {
 758                         compatible = "qcom,msm8996-qmp-pcie-phy";
 759                         reg = <0x34000 0x488>;
 760                         #clock-cells = <1>;
 761                         #address-cells = <1>;
 762                         #size-cells = <1>;
 763                         ranges;
 764
 765                         clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
 766                                 <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
 767                                 <&gcc GCC_PCIE_CLKREF_CLK>;
 768                         clock-names = "aux", "cfg_ahb", "ref";
 769
 770                         vdda-phy-supply = <&pm8994_l28>;
 771                         vdda-pll-supply = <&pm8994_l12>;
 772
 773                         resets = <&gcc GCC_PCIE_PHY_BCR>,
 774                                 <&gcc GCC_PCIE_PHY_COM_BCR>,
 775                                 <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
 776                         reset-names = "phy", "common", "cfg";
 777                         status = "disabled";
 778
 779                         pciephy_0: lane@35000 {
 780                                 reg = <0x035000 0x130>,
 781                                         <0x035200 0x200>,
 782                                         <0x035400 0x1dc>;
 783                                 #phy-cells = <0>;
 784
 785                                 clock-output-names = "pcie_0_pipe_clk_src";
 786                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
 787                                 clock-names = "pipe0";
 788                                 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
 789                                 reset-names = "lane0";
 790                         };
 791
 792                         pciephy_1: lane@36000 {
 793                                 reg = <0x036000 0x130>,
 794                                         <0x036200 0x200>,
 795                                         <0x036400 0x1dc>;
 796                                 #phy-cells = <0>;
 797
 798                                 clock-output-names = "pcie_1_pipe_clk_src";
 799                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
 800                                 clock-names = "pipe1";
 801                                 resets = <&gcc GCC_PCIE_1_PHY_BCR>;
 802                                 reset-names = "lane1";
 803                         };
 804
 805                         pciephy_2: lane@37000 {
 806                                 reg = <0x037000 0x130>,
 807                                         <0x037200 0x200>,
 808                                         <0x037400 0x1dc>;
 809                                 #phy-cells = <0>;
 810
 811                                 clock-output-names = "pcie_2_pipe_clk_src";
 812                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>;
 813                                 clock-names = "pipe2";
 814                                 resets = <&gcc GCC_PCIE_2_PHY_BCR>;
 815                                 reset-names = "lane2";
 816                         };
 817                 };
 818
 819                 phy@7410000 {
 820                         compatible = "qcom,msm8996-qmp-usb3-phy";
 821                         reg = <0x7410000 0x1c4>;
 822                         #clock-cells = <1>;
 823                         #address-cells = <1>;
 824                         #size-cells = <1>;
 825                         ranges;
 826
 827                         clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 828                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 829                                 <&gcc GCC_USB3_CLKREF_CLK>;
 830                         clock-names = "aux", "cfg_ahb", "ref";
 831
 832                         vdda-phy-supply = <&pm8994_l28>;
 833                         vdda-pll-supply = <&pm8994_l12>;
 834
 835                         resets = <&gcc GCC_USB3_PHY_BCR>,
 836                                 <&gcc GCC_USB3PHY_PHY_BCR>;
 837                         reset-names = "phy", "common";
 838                         status = "disabled";
 839
 840                         ssusb_phy_0: lane@7410200 {
 841                                 reg = <0x7410200 0x200>,
 842                                         <0x7410400 0x130>,
 843                                         <0x7410600 0x1a8>;
 844                                 #phy-cells = <0>;
 845
 846                                 clock-output-names = "usb3_phy_pipe_clk_src";
 847                                 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
 848                                 clock-names = "pipe0";
 849                         };
 850                 };
 851
 852                 hsusb_phy1: phy@7411000 {
 853                         compatible = "qcom,msm8996-qusb2-phy";
 854                         reg = <0x7411000 0x180>;
 855                         #phy-cells = <0>;
 856
 857                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 858                                 <&gcc GCC_RX1_USB2_CLKREF_CLK>;
 859                         clock-names = "cfg_ahb", "ref";
 860
 861                         vdda-pll-supply = <&pm8994_l12>;
 862                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 863
 864                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 865                         nvmem-cells = <&qusb2p_hstx_trim>;
 866                         status = "disabled";
 867                 };
 868
 869                 hsusb_phy2: phy@7412000 {
 870                         compatible = "qcom,msm8996-qusb2-phy";
 871                         reg = <0x7412000 0x180>;
 872                         #phy-cells = <0>;
 873
 874                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 875                                 <&gcc GCC_RX2_USB2_CLKREF_CLK>;
 876                         clock-names = "cfg_ahb", "ref";
 877
 878                         vdda-pll-supply = <&pm8994_l12>;
 879                         vdda-phy-dpdm-supply = <&pm8994_l24>;
 880
 881                         resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
 882                         nvmem-cells = <&qusb2s_hstx_trim>;
 883                         status = "disabled";
 884                 };
 885
 886                 usb2: usb@7600000 {
 887                         compatible = "qcom,dwc3";
 888                         #address-cells = <1>;
 889                         #size-cells = <1>;
 890                         ranges;
 891
 892                         clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>,
 893                                 <&gcc GCC_USB20_MASTER_CLK>,
 894                                 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 895                                 <&gcc GCC_USB20_SLEEP_CLK>,
 896                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 897
 898                         assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
 899                                           <&gcc GCC_USB20_MASTER_CLK>;
 900                         assigned-clock-rates = <19200000>, <60000000>;
 901
 902                         power-domains = <&gcc USB30_GDSC>;
 903                         status = "disabled";
 904
 905                         dwc3@7600000 {
 906                                 compatible = "snps,dwc3";
 907                                 reg = <0x7600000 0xcc00>;
 908                                 interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>;
 909                                 phys = <&hsusb_phy2>;
 910                                 phy-names = "usb2-phy";
 911                         };
 912                 };
 913
 914                 usb3: usb@6a00000 {
 915                         compatible = "qcom,dwc3";
 916                         #address-cells = <1>;
 917                         #size-cells = <1>;
 918                         ranges;
 919
 920                         clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>,
 921                                 <&gcc GCC_USB30_MASTER_CLK>,
 922                                 <&gcc GCC_AGGRE2_USB3_AXI_CLK>,
 923                                 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 924                                 <&gcc GCC_USB30_SLEEP_CLK>,
 925                                 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
 926
 927                         assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
 928                                           <&gcc GCC_USB30_MASTER_CLK>;
 929                         assigned-clock-rates = <19200000>, <120000000>;
 930
 931                         power-domains = <&gcc USB30_GDSC>;
 932                         status = "disabled";
 933
 934                         dwc3@6a00000 {
 935                                 compatible = "snps,dwc3";
 936                                 reg = <0x6a00000 0xcc00>;
 937                                 interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>;
 938                                 phys = <&hsusb_phy1>, <&ssusb_phy_0>;
 939                                 phy-names = "usb2-phy", "usb3-phy";
 940                         };
 941                 };
 942
 943                 agnoc@0 {
 944                         power-domains = <&gcc AGGRE0_NOC_GDSC>;
 945                         compatible = "simple-pm-bus";
 946                         #address-cells = <1>;
 947                         #size-cells = <1>;
 948                         ranges;
 949
 950                         pcie0: pcie@600000 {
 951                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
 952                                 status = "disabled";
 953                                 power-domains = <&gcc PCIE0_GDSC>;
 954                                 bus-range = <0x00 0xff>;
 955                                 num-lanes = <1>;
 956
 957                                 reg = <0x00600000 0x2000>,
 958                                       <0x0c000000 0xf1d>,
 959                                       <0x0c000f20 0xa8>,
 960                                       <0x0c100000 0x100000>;
 961                                 reg-names = "parf", "dbi", "elbi","config";
 962
 963                                 phys = <&pciephy_0>;
 964                                 phy-names = "pciephy";
 965
 966                                 #address-cells = <3>;
 967                                 #size-cells = <2>;
 968                                 ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>,
 969                                         <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>;
 970
 971                                 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
 972                                 interrupt-names = "msi";
 973                                 #interrupt-cells = <1>;
 974                                 interrupt-map-mask = <0 0 0 0x7>;
 975                                 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
 976                                                 <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
 977                                                 <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
 978                                                 <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
 979
 980                                 pinctrl-names = "default", "sleep";
 981                                 pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>;
 982                                 pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>;
 983
 984
 985                                 vdda-supply = <&pm8994_l28>;
 986
 987                                 linux,pci-domain = <0>;
 988
 989                                 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
 990                                         <&gcc GCC_PCIE_0_AUX_CLK>,
 991                                         <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
 992                                         <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
 993                                         <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
 994
 995                                 clock-names =  "pipe",
 996                                                 "aux",
 997                                                 "cfg",
 998                                                 "bus_master",
 999                                                 "bus_slave";
1000
1001                         };
1002
1003                         pcie1: pcie@608000 {
1004                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1005                                 power-domains = <&gcc PCIE1_GDSC>;
1006                                 bus-range = <0x00 0xff>;
1007                                 num-lanes = <1>;
1008
1009                                 status  = "disabled";
1010
1011                                 reg = <0x00608000 0x2000>,
1012                                       <0x0d000000 0xf1d>,
1013                                       <0x0d000f20 0xa8>,
1014                                       <0x0d100000 0x100000>;
1015
1016                                 reg-names = "parf", "dbi", "elbi","config";
1017
1018                                 phys = <&pciephy_1>;
1019                                 phy-names = "pciephy";
1020
1021                                 #address-cells = <3>;
1022                                 #size-cells = <2>;
1023                                 ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>,
1024                                         <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>;
1025
1026                                 interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
1027                                 interrupt-names = "msi";
1028                                 #interrupt-cells = <1>;
1029                                 interrupt-map-mask = <0 0 0 0x7>;
1030                                 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1031                                                 <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1032                                                 <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1033                                                 <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1034
1035                                 pinctrl-names = "default", "sleep";
1036                                 pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>;
1037                                 pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>;
1038
1039
1040                                 vdda-supply = <&pm8994_l28>;
1041                                 linux,pci-domain = <1>;
1042
1043                                 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
1044                                         <&gcc GCC_PCIE_1_AUX_CLK>,
1045                                         <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
1046                                         <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
1047                                         <&gcc GCC_PCIE_1_SLV_AXI_CLK>;
1048
1049                                 clock-names =  "pipe",
1050                                                 "aux",
1051                                                 "cfg",
1052                                                 "bus_master",
1053                                                 "bus_slave";
1054                         };
1055
1056                         pcie2: pcie@610000 {
1057                                 compatible = "qcom,pcie-msm8996", "snps,dw-pcie";
1058                                 power-domains = <&gcc PCIE2_GDSC>;
1059                                 bus-range = <0x00 0xff>;
1060                                 num-lanes = <1>;
1061                                 status = "disabled";
1062                                 reg = <0x00610000 0x2000>,
1063                                       <0x0e000000 0xf1d>,
1064                                       <0x0e000f20 0xa8>,
1065                                       <0x0e100000 0x100000>;
1066
1067                                 reg-names = "parf", "dbi", "elbi","config";
1068
1069                                 phys = <&pciephy_2>;
1070                                 phy-names = "pciephy";
1071
1072                                 #address-cells = <3>;
1073                                 #size-cells = <2>;
1074                                 ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>,
1075                                         <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>;
1076
1077                                 device_type = "pci";
1078
1079                                 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1080                                 interrupt-names = "msi";
1081                                 #interrupt-cells = <1>;
1082                                 interrupt-map-mask = <0 0 0 0x7>;
1083                                 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1084                                                 <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1085                                                 <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1086                                                 <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1087
1088                                 pinctrl-names = "default", "sleep";
1089                                 pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>;
1090                                 pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >;
1091
1092                                 vdda-supply = <&pm8994_l28>;
1093
1094                                 linux,pci-domain = <2>;
1095                                 clocks = <&gcc GCC_PCIE_2_PIPE_CLK>,
1096                                         <&gcc GCC_PCIE_2_AUX_CLK>,
1097                                         <&gcc GCC_PCIE_2_CFG_AHB_CLK>,
1098                                         <&gcc GCC_PCIE_2_MSTR_AXI_CLK>,
1099                                         <&gcc GCC_PCIE_2_SLV_AXI_CLK>;
1100
1101                                 clock-names =  "pipe",
1102                                                 "aux",
1103                                                 "cfg",
1104                                                 "bus_master",
1105                                                 "bus_slave";
1106                         };
1107                 };
1108         };
1109
1110         adsp-pil {
1111                 compatible = "qcom,msm8996-adsp-pil";
1112
1113                 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
1114                                       <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1115                                       <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1116                                       <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1117                                       <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
1118                 interrupt-names = "wdog", "fatal", "ready",
1119                                   "handover", "stop-ack";
1120
1121                 clocks = <&xo_board>;
1122                 clock-names = "xo";
1123
1124                 memory-region = <&adsp_region>;
1125
1126                 qcom,smem-states = <&adsp_smp2p_out 0>;
1127                 qcom,smem-state-names = "stop";
1128
1129                 smd-edge {
1130                         interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
1131
1132                         label = "lpass";
1133                         qcom,ipc = <&apcs 16 8>;
1134                         qcom,smd-edge = <1>;
1135                         qcom,remote-pid = <2>;
1136                 };
1137         };
1138
1139         adsp-smp2p {
1140                 compatible = "qcom,smp2p";
1141                 qcom,smem = <443>, <429>;
1142
1143                 interrupts = <0 158 IRQ_TYPE_EDGE_RISING>;
1144
1145                 qcom,ipc = <&apcs 16 10>;
1146
1147                 qcom,local-pid = <0>;
1148                 qcom,remote-pid = <2>;
1149
1150                 adsp_smp2p_out: master-kernel {
1151                         qcom,entry-name = "master-kernel";
1152                         #qcom,smem-state-cells = <1>;
1153                 };
1154
1155                 adsp_smp2p_in: slave-kernel {
1156                         qcom,entry-name = "slave-kernel";
1157
1158                         interrupt-controller;
1159                         #interrupt-cells = <2>;
1160                 };
1161         };
1162
1163         modem-smp2p {
1164                 compatible = "qcom,smp2p";
1165                 qcom,smem = <435>, <428>;
1166
1167                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
1168
1169                 qcom,ipc = <&apcs 16 14>;
1170
1171                 qcom,local-pid = <0>;
1172                 qcom,remote-pid = <1>;
1173
1174                 modem_smp2p_out: master-kernel {
1175                         qcom,entry-name = "master-kernel";
1176                         #qcom,smem-state-cells = <1>;
1177                 };
1178
1179                 modem_smp2p_in: slave-kernel {
1180                         qcom,entry-name = "slave-kernel";
1181
1182                         interrupt-controller;
1183                         #interrupt-cells = <2>;
1184                 };
1185         };
1186
1187         smp2p-slpi {
1188                 compatible = "qcom,smp2p";
1189                 qcom,smem = <481>, <430>;
1190
1191                 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
1192
1193                 qcom,ipc = <&apcs 16 26>;
1194
1195                 qcom,local-pid = <0>;
1196                 qcom,remote-pid = <3>;
1197
1198                 slpi_smp2p_in: slave-kernel {
1199                         qcom,entry-name = "slave-kernel";
1200                         interrupt-controller;
1201                         #interrupt-cells = <2>;
1202                 };
1203
1204                 slpi_smp2p_out: master-kernel {
1205                         qcom,entry-name = "master-kernel";
1206                         #qcom,smem-state-cells = <1>;
1207                 };
1208         };
1209
1210 };
1211 #include "msm8996-pins.dtsi"